JP3106756B2 - Alarm status control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an alarm status control device, and more particularly to an alarm status control device in an ATM (Asynchronous Transfer Mode).

[0002]

2. Description of the Related Art In circuit switching using a synchronous method (STM:
In Synchronous Transfer Mode, paths are time-division multiplexed on one physical line. Therefore, the alarm bit indicating the alarm state (Ais or game alarm) at the relay point and terminal point of each path can be received periodically.

Therefore, even if the detection circuit generates an alarm signal when, for example, three consecutive alarm bits are input, it takes a period from the input of the previous alarm bit to the input of the current alarm bit. Since the time is already known,
It is only necessary to count only the number of times without measuring the time.

A new transfer mode called ATM, which has been used in recent years, is a periodic (time-division) type as in the past.
Are not transmitted to the same destination path, and the data is transmitted asynchronously in the order of the data received by the transmission source device. For example, when there is transmission data from the device A and there is no transmission data from the other devices B, C,..., The transmission data only from the device A is continuously transmitted so that no idle time is created. I have to.

In this transmission system, fixed-length data called a "cell" is used as a transmission unit, and identification of each cell to be transmitted (identification of a virtual path) is made by an identifier provided in a header of each cell. Done by

Therefore, even if the input timing of the alarm cell is asynchronous and, for example, a predetermined number of alarm cells have arrived consecutively, the input of the current alarm cell is started from the timing at which the previous alarm cell was input. If the time until the operation is extremely long, it may not be possible to reliably determine that an abnormality has occurred. Therefore,
An alarm is detected based on whether or not the number of alarm cells arriving within a predetermined time T ₀ (for example, within 3 seconds) has reached a predetermined number N _0. Conversely, the alarm cell is detected within the predetermined time T ₀ . If it does not arrive, the number n of alarm cells that have arrived so far is cleared.

FIG. 4 shows a conventional alarm state control circuit which operates as described above. First, at the preceding stage of this circuit, there is a discriminating circuit for discriminating whether a transmitted cell is a normal cell or an alarm cell. Only the alarm cell is selected and input to the sorting circuit 1. The alarm cells input to the distribution circuit 1 are alarm state control circuits 100 (100 (1), 100 (2)... 100 (1024) corresponding to paths and types of alarms (there are four types of alarms for each path). )).

Each alarm state control circuit 100 has the following configuration. The alarm cells sorted by the sorting circuit 1 as described above are input to the number holding circuit 104, where the number n is incremented. Here, when the incremented number n is larger than a predetermined number N ₀ (for example, when “1” is set in the most significant bit of the output) and when the time detection circuit 103 described below does not reset, An alarm signal is output.

The alarm cells distributed by the distribution circuit 1 as described above are also inputted to a counter reset circuit 101, and the counter reset circuit 101 outputs a reset signal to the next-stage counter 102. The timer value immediately before resetting of the counter 102 reset by the reset signal is input to the time detecting circuit 103, and the time t is determined. Here, the counter 1
When the time t 2 indicated by 02 is shorter than the predetermined set time T _{0, the} number n held by the number holding circuit 104 is held as it is. Conversely, the time t indicated by the counter 103 is equal to the predetermined set time T.
_If it is longer than _0, it means that the predetermined set time T ₀ has elapsed from the arrival of the previous alarm to the arrival of the current alarm, so the number n held in the number holding circuit 104 is meaningless and reset. You.

[0010]

Since there are 256 (8 bits) types of virtual path identifiers and four types of alarm status for each path, a total of 1024 alarm statuses are provided.

If the above-mentioned predetermined time T ₀ is 3 seconds, a clock of 19.44 MHz is used.
There a 6-bit counter is necessary to use one per alarm condition, therefore, the counted the predetermined time T ₀ for each alarm status in 1024, 26-bit counter is 1024 required.

[0012] Therefore, the conventional circuit as described above requires an enormous amount of counters, increases the volume of the apparatus, and significantly increases the cost. The present invention has been proposed in view of the above-mentioned conventional circumstances, and has as its object to provide an alarm state control device in which the number of counters is significantly reduced, the circuit volume is reduced, and the cost is reduced. And

[0013]

The present invention employs the following means to achieve the above object. First, the present invention invention is premised on the alarm condition control device for outputting an alarm signal when an alarm cell input within the predetermined time has entered a predetermined number N ₀ or more. As shown in FIG. 1, in this type of alarm state control device, as shown in FIG. 1, an identifier assigned to the header of the alarm cell and specifying the destination of the alarm cell is used as an address, Storage means 10 for storing t as data
And increments the number n in the data read from the predetermined address of the storage means 10,
A number increment circuit 40 for clearing the time t and storing new data at the same address of the storage means 10; and determining whether the time t read from a predetermined address of the storage means 10 is within a predetermined time T ₀ . Time determination circuit 50 for determining the time t, and the time t
Is less than the predetermined time T ₀ , the read time t is incremented, and the new time t is stored in the storage means 10.
Time increment circuit 60 for storing at the same address
If, as a result of the determination in time determination circuit 50, if the read time t is over the predetermined time T _0, with clears the number n read out the storage data of the clear state It has a clear circuit 70 stored at the same address of the means 10.

The address at the time of the above number increment processing is given from the alarm cell, and the address at the time increment processing is given from the counter 30.
Therefore, a switching means 30 for switching an address given from an alarm cell or a counter 30 in a stage preceding the storage means 10, and when an address from the alarm cell is selected by the switching means 30, the number increment circuit 40 When the output is selected and the address is selected from the counter 30, the time increment circuit 6
Switching means 80 for selecting 0 or the output of the clear circuit 70 and returning the output to the storage means 10 is provided.

[0015]

When the alarm cell arrives, the number of times n of inputting the corresponding alarm cell and the elapsed time t from the previous input are read from the storage means 10 using the identifier written in the header of the alarm cell as an address. The number n of alarm cell inputs is incremented (+1) by the number increment circuit 40, and the time t is cleared and written to the same address in the storage means 10 again. At this time,
When the incremented number n reaches the predetermined number N ₀ (for example, when “1” is set in the most significant bit), an alarm signal is output.

On the other hand, the output of the counter 30 is also input to the storage means 10 as an address of the storage means 10. In this case, the time t is read time t in the time decision circuit 50 whether or not over a predetermined time T ₀ is determined.

Here, when the storage time t exceeds the predetermined time T ₀ , even if an alarm cell arrives after this, the alarm cell arrives after the predetermined time T _0. For this purpose, both the time t and the number n are cleared by the clear circuit 70, and the cleared time and number, that is, the value “0” are stored again in the same address of the storage means 10.

When the storage time t is less than the predetermined time T ₀ in the time determination circuit 50, the storage time t is incremented (+1) and stored at the same address in the storage means 10.

In the above, the process of incrementing the number n (the process when an alarm arrives) and the process of incrementing (or clearing) the time t must be performed in a time-division manner. Therefore, the address from the alarm cell and the counter 3
From 0, the address is selectively switched by a switching control clock Sc synchronized with the cell transmission speed. Also,
Similarly, the output of the number increment circuit 40 and the output of the time increment circuit 60 (or the clear circuit 70) are switched by the switching control clock Sc.

[0020]

FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a time chart thereof.

Addresses corresponding to the type of path and the type of alarm are assigned to the storage means 10, and the number n of alarms arriving at the predetermined time T ₀ and the time t since last arriving are written in each address. It has become.

The alarm cells are sequentially transmitted on the transmission line in accordance with a transmission clock having a predetermined period, and the address As of the alarm cell shown in FIG. On the other hand, the address counter 30 is driven by the transmission clock, and its output is input to the selector 20 as the address Ac of the storage means 10 as shown in FIG. The selector 20 is controlled by a switching control clock Sc (FIG. 3B) having the same cycle as the transmission clock, and selects, for example, an address Ac output from the counter 30 in the first half of the switching control clock Sc. In the latter half of Sc, the address As of the alarm cell obtained from the input line is selected.

The address As of the alarm cell selected in this way or the address Ac from the counter 30 is input to the storage means 10 at the next stage. Here, the selector 20
When the address As of the alarm cell is selected, the address As is input to the storage means 10 in the latter half of the switching control clock Sc. As shown in FIG. 3D, in the first half when the address As of the alarm cell is selected, the read / write signal Srw input to the storage means 10 is in the read enable state. As input of As, the storage means 10
The number n and the time t stored in the address As are read out and latched in the register 90. Then, this data is input to the number increment circuit 40, and the number n is incremented by one. On the other hand, the time t read from the storage means 10 indicates the result of measuring the time t from the arrival of a new alarm cell to the arrival of the next alarm cell. The meaning is lost when a new alarm cell arrives, and is cleared by the number increment circuit 40.

The number n thus incremented,
Alternatively, the cleared time t (t = 0) is determined by the selector 80
Is input to The selector 80 is connected to the increment circuit 40 side by the switching control clock Sc at this time, and the read / write signal Srw is in the write enable state as shown in FIG. The number n and the cleared time t are written to the same address of the storage means 10 again.

When the arriving address is not the address As of the alarm cell, the read / write signal of the storage means 10 is masked by the alarm discriminating circuit (not shown).

The address Ac is given to the storage means 10 by the counter 30 in the first half of the switching control clock Sc. Thus, the read number n of the alarm cell corresponding to the address Ac and the time t since the last arrival of the alarm cell are latched in the register 90 as described above.

The time t in the data latched in this way register 90 is input to the time decision circuit 50 where it is compared with a predetermined time T _0. As a result, the time t
Select circuit 8 but when less than the predetermined time T _0, there is a possibility that further alarm cell arrives at a predetermined time T in _0, and +1 time t in the time increment circuit 60
The time t incremented from 0 (the count data remains unchanged) is stored in the storage means 10.

When the time t is longer than the predetermined time T ₀ ,
This means that the previous alarm cell arrived before the predetermined time T ₀ . Therefore, even if an alarm cell arrives next time, it is difficult to determine whether or not the abnormality actually continues. In this case, both the number n and the time t are cleared by the clear circuit 70, and Cleared data (n
= 0, t = 0) is stored at the original address of the storage means 10.

According to the above configuration, it is not necessary to use a counter for each type of path and alarm, and processing can be performed with only one storage unit 10 and address counter 30.

[0030]

As described above, according to the present invention, it is not necessary to use a counter for each type of path and alarm, so that the circuit capacity can be significantly reduced and the cost can be significantly reduced.

[Brief description of the drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a block diagram of one embodiment of the present invention.

FIG. 3 is a time chart of the present invention.

FIG. 4 is a block diagram of a conventional example.

[Explanation of symbols]

Reference Signs List 10 storage means 20 selector 30 counter 40 number increment circuit 50 time judgment circuit 60 time increment circuit 70 clear circuit 80 switching means T ₀ predetermined time N ₀ predetermined number n alarm input times

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04L 12/56 H04L 12/28 H04L 12/24 H04L 12/26

Claims (1)

(57) [Claims] 1. An alarm status control device for outputting an alarm signal when a predetermined number (No) of alarm cells input within a predetermined time (To) is input, wherein the alarm cell attached to a header of the alarm cell is provided. Storage means (10) for storing the number of times of input of the alarm (n) and the elapsed time (t) since the previous input as data, with an identifier designating the destination of the destination as an address; A number increment circuit (40) for incrementing the number (n) of the data read from the address of (i), clearing the time (t) and storing new data at the same address of the storage means (10); A time determination circuit (50) for determining whether a time (t) read from a predetermined address of the storage means (10) is within a predetermined time (To), and a time determination circuit (50). Time read as a result of judgment
If (t) is less than the predetermined time (To), the read time (t) is incremented, and a new time (t) is stored in the same address of the storage means (10). 60) and as a result of the determination by the time determination circuit (50), when the read time (t) exceeds a predetermined time (To), the read number (n) and the time (t) is cleared and the data in the cleared state is stored in storage means (10)
A clear circuit (70) to be stored at the same address and a preceding stage of the storage means (10), a
The address given by the alarm cell and the transmission unit
And the address given by the counter (39) in the predetermined period of
The selector (20) to be switched and the address from the alarm cell by the selector (20)
Is selected from the increment circuit (40) when
Output, and the address from the counter (30)
When selected, the time increment circuit (60) or
The output of the rear circuit (70) is selected, and the output is stored in storage means (10).
Switching means (80) for returning to the alarm
State control device.