JPH06216929A - Atm switch - Google Patents

Abstract

PURPOSE:To use equally arranged memory capacities to process the concentrated arrival of cells to a specific input line by providing a multiplexing control circuit with a means which controls the read quantity in accordance with the stored quantity of each cell buffer in conformity with a prescribed logic at each opportunity of cell sending of the cell buffer. CONSTITUTION:When the number of cells in the queue of a cell buffer 111 is 0, a token is transferred to a next cell buffer 112. When the number of cells in the queue of the cell buffer 111 is smaller than a first threshold, the token is transferred to the next cell buffer 112 after one cell is sent. When the number of cells in the queue of the cell buffer 111 is equal to or larger than the first threshold and is smaller than a second threshold, the token is transferred to the next cell buffer 112 after two cells are sent. When the number of cells in the queue of the cell buffer 111 is equal to or larger than the second threshold and is smaller than a third threshold, the token is transferred to the next cell buffer 112 after three cells are sent. When the number of cells in the queue of the cell buffer 111 is equal to or larger than the third threshold, the token is transferred to the next cell buffer 112 after four cells are sent.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention finds use in digital telecommunications switching equipment. In particular, it relates to a technique for improving throughput of an ATM (asynchronous transfer mode) switching device.

[0002]

2. Description of the Related Art A having N incoming lines and N outgoing lines
As a TM switch, there is a one-stage matrix switch in which a cell buffer is arranged at each intersection of N × N matrix switches. A conventional example will be described with reference to FIGS. 6 and 7.
FIG. 6 is a block diagram of a conventional device. FIG. 7 is a diagram showing a cell buffer and a multiplexing control circuit of a conventional device.

Cells asynchronously input from the input lines 211 to 21n are multiplexed and output to the output lines 221 to 22n. At this time, contention control between cells input from the incoming lines 211 to 21n is performed. As a result, cells that have missed the transmission opportunity are not discarded, so that the incoming lines 211 to 21
n and the output lines 221 to 22n have cell buffers 111 to 1nn at the respective intersections and address filters 911 to 9n.
The corresponding cells selected by n are the incoming lines 211 to 21.
The input cells from n are temporarily stored in the cell buffers 111 to 1nn.

In this ATM switch, the outgoing line 221
The cell multiplexing to 22n is arranged at each intersection of the incoming lines 211 to 21n and the outgoing lines 221 to 22n, and the outgoing lines 221 to 2 are arranged between the distributed cell buffers 111 to 1nn.
The cell read order to 2n is determined, and outgoing lines 221 to 22
It is realized by performing cell multiplexing on n.

In FIG. 6, cell buffers 111 to 1n are shown.
n is the internal wiring 811 to 8nn for the multiplex control signal 71 to 7n when the multiplex request signal is present in each buffer.
Notify via. The multiplex control circuits 71 to 7n poll the multiplex request signals of the cell buffers 111 to 1nn in a predetermined order, and output one cell of the head cell of the cell buffers 111 to 1nn which has issued the connection request to the outgoing line 221 to 221.
22n. For example, when the cells of the cell buffer 111 are connected last time, the cells are first accumulated in the cell buffer 112 and the subsequent cells, and the cell buffers 111 to 1nn generating the connection request are connected to the outgoing lines 221 to 22n. Repeat the operation. By this operation, cells from the plurality of cell buffers 111 to 1nn can be multiplexed and output. As shown in FIG. 7, the cell which has obtained the cell transmission right 51 is transmitted under the control of the multiplexing control circuits 71 to 7n.

Another conventional example will be described with reference to FIGS. FIG. 8 is a block diagram of another conventional device.
FIG. 9 shows another conventional example of the multiplex control circuits 311 to 3n.
It is a figure which shows n. FIG. 10 is a diagram showing the output status of the conventional device. In the conventional device shown in FIG. 8, multiplex control circuits 311 to 3nn are provided in the cell buffers 111 to 1nn, respectively. FIG. 9 shows multiple control circuits 311 to 3n.
n connections are shown. The cell transmission right 51 is circulated on the internal wirings 41 to 4n. A token carrying the cell transmission right 51 is circulated between the multiplex control circuits 311 to 3nn.
Multiplex control circuits 311 to 311 which have received the cell transmission right 51
When there is a cell to be sent to the cell buffers 111 to 1nn managed by the multiplexing control circuits 311 to 3nn, the 3nn connects the first cell from the cell buffers 111 to 1nn to the outgoing lines 221 to 22n. Cell buffer 111-
If there is no cell to be transmitted in 1nn, the cell transmission right 51
Is immediately circulated to the next multiplex control circuits 311 to 3nn. In each of the multiplex control circuits 311 to 3nn,
By performing this operation, the plurality of cell buffers 111 to 111
Cells from 1nn can be multiplexed and output.

As shown in FIG. 10, the cell buffer 111
The cells accumulated at the head of 1n4 are outgoing lines 221 to 22
After being multiplexed into n, the second and subsequent cells from the beginning are sequentially multiplexed.

[0008]

In such multiplex control to the outgoing line of the ATM switch, polling by the central control means of the cell buffer accumulating cells or
By circulating the cell transmission right among the multiplexing control circuits, cell multiplexing is realized by avoiding cell discard due to cell collision at the time of outgoing line multiplexing. However, in such a scheme, when cells are arriving at multiple inputs on average, there is no problem,
It is necessary to prepare a large-scale memory in the corresponding cell buffer to suppress cell discard under the traffic condition where the input is biased to a specific incoming line. In order to guarantee a sufficiently low cell loss rate for arbitrary traffic, the cell buffer needs to have a very large buffer capacity.

When applied to an ATM switch operating at high speed, the transfer time of the connection request signal and cell transmission right between the multiplex control circuit and each cell buffer or the transfer time of the cell transmission right between a plurality of multiplex control circuits. Is a factor and causes a problem in performing high-speed cell multiplexing with control.

The present invention has been made against such a background, and an ATM switch capable of processing the arrival of cells biased to a specific incoming line by using the memory capacity evenly arranged on each incoming line. The purpose is to provide.

[0011]

SUMMARY OF THE INVENTION The present invention comprises a plurality of incoming lines to which cells arrive and a plurality of outgoing lines to which cells are sent out.
A cell buffer, which is provided at each intersection of the incoming line and the outgoing line, temporarily stores cells waiting to pass through the intersection, and a multiplex control circuit for controlling cell reading of the cell buffer to the outgoing line. ATM switch.

Here, a feature of the present invention is that the multiplex control circuit includes means for controlling the read amount for each cell transmission opportunity of each cell buffer according to a predetermined logic according to the accumulated amount of the cell buffer. It is included.

It is preferable that the predetermined logic is a logic that sets a plurality of thresholds for the cell accumulation amount of the cell buffer and controls the cell read amount depending on which one of the thresholds is reached.

Means for counting the cell accumulation amount of each cell buffer may be provided, and the predetermined logic may be a logic for controlling the cell read amount according to the count value of the counting means.

It is also possible to provide means for calculating the arrival interval of the cell transmission right, and the predetermined logic may be a logic for controlling the cell read amount according to the arrival interval and the count value.

The cell stored in the cell buffer is provided with means for giving arrival time information of the cell, and means for calculating a difference between the arrival time information and the arrival time of the cell transmission right is provided, and the predetermined value is provided. The logic may be configured to control the cell read amount according to the value of this difference. Further, the predetermined logic may be a logic for controlling the cell read amount according to the arrival time information of the cell and the arrival interval of the cell transmission right.

[0017]

According to the number of cells accumulated in the queue of each incoming line, a plurality of cells are transmitted at one cell transmission opportunity. That is, the number of cells to be transmitted in one cell transmission opportunity is changed based on the number of cells accumulated in the queue of each incoming line.

Further, the congestion state of the contention control of the entire ATM switch is estimated from the arrival interval of the cell transmission right to control the number of cells transmitted. That is, if the arrival interval of the cell transmission right is long, the contention control is congested, and if it is short, it is vacant. A large number of stored cells are sent out when the cells are free, and a small number are sent when the cells are congested to equalize the number of waiting cells in all cell buffers.

Further, the arrival time information of the cell is recorded in the cell, and the number of transmission cells is controlled based on this arrival time information.
That is, the waiting time after the arrival of the cell is referred to on the basis of the arrival time of the cell transmission right or the arrival cycle of the cell transmission right, and the cell having the waiting time longer than a certain value is transmitted.

As a result, a large amount of cells are transmitted from a cell buffer having a large load, and the uneven cell load can be eliminated.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of the first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a block diagram of an ATM switch. FIG. 2 is a diagram showing a multiplex control circuit and a cell buffer according to the first embodiment of the present invention.

According to the present invention, N incoming lines 2 from which cells arrive
11 to 21n and N outgoing lines 221 to which cells are sent
22n, and the incoming lines 211 to 21n and outgoing line 2
Cell buffers 111 to 11 that are provided at each intersection of 21 to 22n and temporarily store cells waiting to pass through this intersection
1nn and the outgoing line 2 of the cell buffers 111 to 1nn
Multiplexing control circuit 61 for controlling cell reading to 21 to 22n
1 to 6nn.

Here, the feature of the present invention is that the multiplex control circuits 611 to 6nn are provided in each cell buffer 11.
It includes means for controlling the read amount for each cell transmission opportunity of 1 to 1nn according to the predetermined logic according to the accumulated amount of the cell buffers 111 to 1nn.

In the first embodiment of the present invention, the predetermined logic is a logic that sets three levels of thresholds for the cell accumulation amounts of the cell buffers 111 to 1nn and controls the cell read amount depending on which of the thresholds is reached. Is.

Next, the operation of the first embodiment of the present invention will be described. As shown in FIG. 1, the tokens circulating in the internal wirings 41 to 4n are the cell buffers 111 connected to the multiplexing control circuits 611 to 6nn that have received the tokens.
Cell grant is given to ~ 1nn. This token simply goes around the multiplex control circuits 611 to 6nn. In the multiplexing control circuits 611 to 6nn that have received the token, the number of cells to be transmitted is set based on the number of cells stored in the cell buffers 111 to 1nn.

The procedure for setting the cell read amount will be described with reference to FIG. In FIG. 2, when the number of cells in the queue of the cell buffer 111 is zero, the token is passed to the next cell buffer 112. When the number of cells in the queue of the cell buffer 111 is less than the first threshold value, one cell is transmitted. Then, pass the token to the next cell buffer 112, cell buffer 1
If the number of cells in the queue of 11 is equal to or more than the first threshold and less than the second threshold, 2 cells are transmitted, and then the token is passed to the next cell buffer 112. If it is equal to or more than the threshold value and less than the third threshold value, 3 cells are transmitted and then the token is sent to the next cell buffer
When the number of cells in the queue of the cell buffer 111 to be passed to 12 is equal to or larger than the third threshold value, 4 cells are transmitted and then the token is passed to the next cell buffer 112.

In FIG. 2, the cell buffer 111 and the multiplexing control circuit 611 have been described for the sake of easy understanding, but all the cell buffers 111 to 1n are described.
The same applies to n and the multiplex control circuits 611 to 6nn.

Although the thresholds are set at equal intervals in the first embodiment of the present invention, they may be set logarithmically. Also, the number of transmissions is the first threshold in the first embodiment of the present invention,
Although 1 cell, 2 cells, and 3 cells are set in the order of the second threshold value and the third threshold value, weighting such as 1 cell, 4 cells, and 8 cells may be adopted.

Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 3 shows a cell buffer 11 according to the second embodiment of the present invention.
1 is a diagram showing 1 and a multiplex control circuit 611 and a counter 611 _1. FIG. In the second embodiment of the present invention, the counter 611 ₁
It is characterized in that it is configured to include. Counter 611
₁ is counted up when a cell is written in the cell buffer 111 and is counted down when read. That is, the count value of the counter 611 ₁ is the current number of cells in the cell buffer 111. Operation of the multiple control circuit 611 sets the read amount based on the value of the counter 611 _1, there are two modes of the counter 611 value of ₁ and token sets the read amount, based on the time interval arrives.

Regarding the mode, a threshold value is set as in the first embodiment of the present invention, and the number of transmission cells is set based on this. In addition to this, various functions may be programmed to set the number of transmission cells.

Regarding the mode, the CPU of the multiplex control circuit 611 calculates the difference between the time when the previous token arrived and the time when the current token arrived, and the congestion status of the other cell buffers 112 to 11n, that is, the entire ATM switch. Estimate the congestion status of.

If the token returns in a short time,
This shows that the number of waiting in the other cell buffers 112 to 11n is small. At this time, the number of cells in the cell buffer 111 indicated by the value of the counter 611 ₁ is referred to, and cells are positively transmitted in proportion to the number of cells. On the contrary, if the token returns for a relatively long time,
The number of cells in the cell buffer 111, that is, the counter 611.
Send a small number of cells even if the value of ₁ is large. As a result, the number of waits in all the cell buffers 111 to 1nn can be substantially equalized.

In FIG. 3, in order to make the explanation easy to understand,
Although the cell buffer 111, the multiplex control circuit 611 and the counter 611 ₁ have been described, all the cell buffers 111 to 1nn, the multiplex control circuits 611 to 6nn and the counters 611 _{1 to} 6nn ₁ can be similarly described.

A third embodiment of the present invention will be described with reference to FIGS. FIG. 4 is a diagram showing a cell buffer 111, a multiplexing control circuit 611 and a time stamp counter 611 _{2 according} to the third embodiment of the present invention. FIG. 5 is a diagram showing the output status of the third embodiment of the present invention. The third embodiment of the present invention is
Characterized in that it is configured to include a time stamp counter 611 _2. When a cell arrives timestamp counter 611 ₂ its arrival time is written the cell buffer to 1
It is stored in 11. Multiplex control circuit 6 that received the token
The CPU 11 reads the cell buffer 111. As the control of the CPU, the cell is continuously read and transmitted until the difference between the current time and the time stamp TS in the cell buffer 111 reaches a certain value. As a result, it is possible to avoid the occurrence of a cell that continues to wait in the cell buffer 111 for a certain period of time or more.
All the cells waiting for a time longer than T (K ≧ 1) are transmitted, and the cycle T of the past L times that the token has circulated
, T2 + T2 + T3 in consideration of 1, T2, T3, ..., TL
There are three modes: send out all cells waiting longer than + ... + TL. As a result, the number of cells optimally controlled by the token cycle period and the number of waiting cells can be read. Further, the multiplexed output can be output from the input having the highest load, as shown in FIG.

[0035]

As described above, according to the present invention, the control of the cell buffers in a distributed manner by simply circulating the tokens makes the load of the cell traffic between the cell buffers uneven. Even if there is, the cell loss can be minimized by time-sharing the outputs from each other.

Furthermore, by performing these controls in a distributed manner, the ATM switch scale can be easily expanded.

[Brief description of drawings]

FIG. 1 is a block diagram of an ATM switch.

FIG. 2 is a diagram showing a cell buffer and a multiplexing control circuit according to the first embodiment of the present invention.

FIG. 3 is a diagram showing a cell buffer, a counter, and a multiplexing control circuit according to a second embodiment of the present invention.

FIG. 4 is a diagram showing a cell buffer, a time stamp counter, and a multiplexing control circuit according to a third embodiment of the present invention.

FIG. 5 is a diagram showing an output situation of the third embodiment of the present invention.

FIG. 6 is a configuration diagram of a conventional example.

FIG. 7 is a diagram showing a conventional cell buffer and a multiplexing control circuit.

FIG. 8 is a configuration diagram of another conventional example.

FIG. 9 is a diagram showing another conventional multiplex control circuit.

FIG. 10 is a diagram showing an output situation of a conventional example.

[Explanation of symbols]

111~1nn cell buffer 211~21n incoming line 221~22n outgoing line 311~3nn, 611~6nn, 71~7n multiplex control circuit 41~4n, 811~8nn internal wiring 51 cells send right 611 ₁ ~6nn ₁ Counter 611 ₂ ~ 6nn ₂ Time stamp counter 911-9nn Address filter

Claims (6)

[Claims] 1. A plurality of incoming lines to which cells arrive, a plurality of outgoing lines to which cells are sent, and a cell which is provided at each intersection of these incoming lines and outgoing lines and which waits to pass through these intersections. In an ATM switch equipped with a cell buffer for accumulating and a multiplex control circuit for controlling cell reading of the cell buffer to the output line, the multiplex control circuit determines the read amount for each cell transmission opportunity of each cell buffer. An AT including means for controlling according to a predetermined logic in accordance with an accumulated amount of a cell buffer
M switch. 2. The ATM switch according to claim 1, wherein the predetermined logic is a logic that sets a plurality of thresholds in a cell storage amount of the cell buffer and controls a cell read amount depending on which one of the thresholds is reached. . 3. The AT according to claim 1, further comprising means for counting the cell accumulation amount of each cell buffer, wherein the predetermined logic is a logic for controlling the cell read amount according to the count value of the counting means.
M switch. 4. The ATM switch according to claim 3, further comprising means for calculating an arrival interval of cell transmission rights, wherein the predetermined logic is a logic for controlling a cell read amount according to the arrival interval and the count value. 5. The cell accumulated in the cell buffer is provided with means for giving arrival time information of the cell, and means for calculating a difference between the arrival time information and the arrival time of the cell transmission right is provided. 2. The ATM switch according to claim 1, wherein the predetermined logic is a logic that controls a cell read amount according to the value of the difference. 6. The cell stored in the cell buffer is provided with a means for giving arrival time information of the cell, and the predetermined logic is configured so that the cell arrives according to the arrival time information of the cell and the arrival interval of the cell transmission right. The ATM switch according to claim 1, which is a logic for controlling a read amount.