JP3043232B2 - Display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly, to a display device capable of optimally adjusting the phases of control signals such as a clamp signal, a blanking signal, and a phase comparison inhibition signal on a screen.

[0002]

2. Description of the Related Art In a display device currently used for displaying a computer image, a clamp signal for processing a video signal, a blanking signal, and a phase comparison inhibition signal required for a PLL circuit are previously provided. It is set to the optimal value. The phase comparison inhibit signal is generated during the vertical retrace period so that the PLL circuit does not malfunction due to an aperiodic pulse signal included in the vertical retrace period of the horizontal sync signal and the phase of the horizontal sync signal does not change indiscriminately. Is a signal for inhibiting the phase comparison.

[0003]

By the way, for a display device for a computer, various types of devices for converting signals supplied from the computer to the display device are commercially available. When such a signal conversion device is used, the above-described clamp signal, blanking signal,
The optimum value of the phase such as the phase comparison prohibition signal may be different from the preset value. Therefore, in order to display an optimal image based on such a converted signal, it is necessary to reset the phases of a clamp signal, a blanking signal, a phase comparison inhibition signal, and the like using an oscilloscope or other device. did not become.

The present invention has been made to solve the above problems, and has as its object to control signals having a predetermined phase relationship with a synchronization signal, such as a clamp signal, a blanking signal, and a phase comparison inhibit signal. It is an object of the present invention to provide a display device that can easily adjust the phase of the display device.

Another object of the present invention is to provide a display device capable of adjusting the phase of such a control signal on a screen.

[0006]

According to the present invention, there is provided a display apparatus for displaying an image from a video signal by reproducing a synchronous signal and a control signal having a predetermined phase relationship with the synchronous signal, and the synchronous signal. A supply unit that supplies the control signal as the video signal to the display unit; a shift unit that shifts a phase of a synchronization signal supplied to the display unit; and an adjustment unit that adjusts the phase of the control signal. .

[0007]

In the display device according to the present invention,
Control signals such as a synchronization signal and a clamp signal, a blanking signal, and a phase comparison inhibition signal are supplied to the display means as video signals, and the original synchronization signal is supplied to the display means with its phase shifted. The synchronization signal and the control signal are displayed on the screen. Therefore, the phase of the control signal can be easily adjusted on the screen so that the control signal has a predetermined phase relationship with the synchronization signal.

[0008]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing an overall configuration of a display device according to an embodiment of the present invention. Referring to FIG. 1, this display device includes a liquid crystal panel 10 that displays an image based on a video signal including a red signal R, a green signal G, and a blue signal B, and a drive that drives each liquid crystal cell of the liquid crystal panel 10. And a timing control circuit 12 for generating the signal φ. As a device for displaying an image, a CRT or the like may be used instead of the liquid crystal panel 10.

The display device further includes a clamp circuit 14 for clamping the video signals R, G, and B to predetermined values.
And a blanking circuit 16 for inserting a predetermined blanking period into the video signals R, G, B, and another video signal R, G, B combined with the video signals R, G, B and supplied to the liquid crystal panel 10 And an on-screen circuit 18. Therefore, the video signals R, G, B are supplied to the liquid crystal panel 10 via the clamp circuit 14, the blanking circuit 16, and the on-screen circuit 18. The image based on the video signals R, G, B inserted from the on-screen circuit 18 is displayed on the liquid crystal panel 10 with the image based on the video signals R, G, B supplied from the outside as a background.

The display apparatus further includes a clamp signal generation circuit 20 for generating a clamp signal CL, a blanking signal generation circuit 22 for generating a blanking signal BL, and a phase comparison inhibition signal generation for generating a phase comparison inhibition signal PH. A circuit 24, an adjustment circuit 26 which can manually adjust the phases of these signals CL, BL, PH, and a stable clock signal CK based on a composite synchronization signal CS supplied from the outside, and the timing of the clock signal CK A PLL circuit 34 that supplies the control circuit 12 with the control signal. Here, the composite synchronization signal CS is a signal obtained by superimposing a vertical synchronization signal, an equalization pulse, and the like on a horizontal synchronization signal.

The adjusted clamp signal CLA is supplied to a clamp circuit 14, which clamps the video signals R, G, and B in response to the adjusted clamp signal CLA. The adjusted blanking signal BLA is supplied to the blanking circuit 16 and the blanking circuit 16
Inserts a predetermined blanking period into the video signals R, G, B in response to the adjusted blanking signal BLA. The adjusted phase comparison inhibit signal PHA is output to the PLL circuit 3
4 is supplied. The PLL circuit 34 synchronizes the clock signal CK with the composite synchronizing signal CS by comparing the phase of the clock signal CK with the phase of the composite synchronizing signal CS. The adjusted phase comparison inhibition signal PHA is supplied. During this time, such a phase comparison is not performed in the PLL circuit 34. Accordingly, the stable clock signal CK is supplied from the PLL circuit 34 even though the composite synchronizing signal CS has various non-periodic pulses within the vertical blanking period.

The display device further includes video signals R, G, and G for supplying to the on-screen circuit 18 in response to control signals CT1 and CT2 supplied from outside.
An on-screen input switching circuit 28 for switching B and an OR gate 30 for supplying a logical sum signal to the timing control circuit 12 in response to the control signals CT1 and CT2.

The switching circuit 28 is supplied with the composite synchronizing signal CS, and receives the video signals R,
G and B are supplied. When the control signals CT1 and CT2 are both L (logic low), the switching circuit 28
Are supplied to the on-screen circuit 18. When control signal CT1 is at H level and control signal C
When T2 is at the L level, the switching circuit 28 outputs the composite synchronizing signal C
The inverted signal of S is supplied to the on-screen circuit 18 as a green signal B in the video signal, and the adjusted phase comparison inhibition signal PHA is supplied to the on-screen circuit 18 as a red signal R in the video signal.

When the control signal CT1 is at the L level and the control signal CT2 is at the H level, the switching circuit 28 supplies the inverted signal of the composite synchronizing signal CS to the on-screen circuit 18 as a green signal G, and adjusts the adjusted clamp signal. CL
A is supplied to the on-screen circuit 18 as a red signal R. When the control signals CT1 and CT2 are both at the H level, the switching circuit 28 supplies the inverted signal of the composite synchronizing signal CS to the on-screen circuit 18 as a green signal G, and turns on the adjusted blanking signal BLA as a red signal R. Supply to the screen circuit 18.

The timing control circuit 12 includes an OR gate 3
When the output signal of 0 is at the H level, the phase of the horizontal synchronizing signal for driving the liquid crystal panel 10 is shifted by (１ ／) horizontal period, and the vertical synchronizing signal is shifted by (１ ／) vertical period. It is configured as follows.

Next, the operation of this display device will be described with reference to FIG.
This will be described with reference to the timing chart of FIG.

(1) Normal operation mode In a normal operation mode, for example, when a signal such as a video signal is directly supplied to the display device from a standard computer, the control signals CT1 and CT
2 are both at L level. Therefore, the CPU 32
Are supplied to the on-screen circuit 18 via the switching circuit 28. Further, since the L level OR output is supplied to the timing control circuit 12,
Normal horizontal and vertical synchronizing signals and PLL circuit 34
The image is displayed on the liquid crystal panel 10 in an optimal state based on the clock signal CK from the CPU.

(2) Adjustment mode of phase comparison inhibition signal When adjusting the phase of the phase comparison inhibition signal PH, the control signal CT1 is set to the H level and the control signal C
T2 is set to L level. Therefore, the composite synchronization signal C
S is inverted in the switching circuit 28, and the green signal G
And supplied to the on-screen circuit 18 as
The adjusted phase comparison inhibition signal PHA is supplied to the on-screen circuit 18 as a red signal R via the switching circuit 28. In the timing control circuit 12, the horizontal synchronizing signal is changed to (1/1) in response to the H level logical sum signal.
2) The signal is shifted by the horizontal period and the vertical synchronizing signal is (1).
/ 2) Shift by vertical period.

The composite synchronization signal CS is, as shown in FIG.
It is essentially composed of the horizontal synchronizing signal HS and includes the vertical synchronizing signal VS and the equalizing pulse EP. When the PLL circuit 34 operates in response to the composite synchronizing signal CS, the image on the liquid crystal panel 10 is not stable because the composite synchronizing signal CS includes an aperiodic signal. Therefore, during a period in which an aperiodic signal is included, the phase comparison in the PLL circuit 34 is prohibited. However, when the composite synchronizing signal CS is supplied from the computer via the above-described signal converter, as shown in FIG. 2, the phase of the phase comparison inhibition signal PH starts from a period in which a non-periodic signal is included. It may be off.

When the horizontal and vertical synchronizing signals of the liquid crystal panel 10 are shifted, a blanking period of the video signal is displayed on the liquid crystal panel 10 as shown in FIG. Further, since the inverted signal of the composite synchronizing signal CS is supplied to the on-screen circuit 18 as a green signal G, a vertical green line indicating the horizontal synchronizing signal HS is displayed during the horizontal retrace period, and during the vertical retrace period. A green horizontal line indicating the vertical synchronization signal VS is displayed. Since the equalization pulse EP is inserted before and after the vertical synchronization signal VS, it is displayed above and below the vertical synchronization signal VS.

The on-screen circuit 18 is further supplied with a phase comparison prohibition signal as a red signal R, so that this phase comparison prohibition signal is also displayed on the liquid crystal panel 10. When the unadjusted phase comparison inhibition signal PH is supplied to the on-screen circuit 18, the red color indicating the phase comparison inhibition signal PH is parallel to the horizontal line indicating the vertical synchronization signal VS as shown in FIG. A horizontal line is displayed.

When the phase of the phase comparison inhibition signal PH is adjusted by the adjustment circuit 26 and shifted to the non-periodic period of the composite synchronization signal CS as shown in FIG. 2, the adjustment is performed as shown in FIG. The red horizontal line indicating the phase comparison inhibition signal PHA moves to the green horizontal line indicating the vertical synchronization signal VS. Therefore, the portion where the green portion and the red portion overlap is displayed in yellow.

As described above, even when the phase comparison prohibition signal deviates from the optimum state, the phase comparison prohibition signal can be easily reset to the optimum state on the screen.

(3) Adjustment Mode of Clamp Signal When adjusting the phase of the clamp signal CL, the control signal CT1 is set to L level and the control signal CT2 is set to H level. Therefore, the horizontal and vertical synchronizing signals of the liquid crystal panel 10 are shifted by a predetermined period as described above, and the inverted signal of the composite synchronizing signal CS is supplied to the on-screen circuit 18 as a green signal G.

An unadjusted clamp signal C as shown in FIG.
When L is supplied to the screen circuit 18 as a red signal R via the switching circuit 28, as shown in FIG. 4A, the red clamp signal CL is parallel to and separated from the green horizontal synchronization signal HS. It is displayed vertically.

Although this clamp signal CL is located near the center of the horizontal period as shown in FIG. 2, it is originally located between the end of the horizontal synchronizing signal and the start of the effective display period. Have to do it.

Therefore, when such a clamp signal CL is adjusted by the adjustment circuit 26 to be in an optimum state, FIG.
As shown in (b), the red clamp signal CL moves to the left. That is, the adjusted clamp signal CL
A is displayed immediately to the right of the green horizontal synchronization signal HS.
The adjusted clamp signal CLA does not overlap with the video signal.

As described above, since the horizontal synchronization signal and the clamp signal are displayed on the screen, the phase of the clamp signal can be optimally adjusted on the screen.

(4) Blanking Signal Adjustment Mode When adjusting the phase of the blanking signal BL, both the control signals CT1 and CT2 are set to the H level. Therefore, the horizontal and vertical synchronizing signals of the liquid crystal panel 10 are shifted by a predetermined period as in the adjustment mode.

Since the composite synchronizing signal CS is inverted by the switching circuit 28 and supplied to the on-screen circuit 18 as a green signal G, the horizontal and vertical synchronizing signals are applied to the liquid crystal panel 10 in the same manner as in the adjustment mode. Is displayed. Further, the blanking signal is supplied to the on-screen circuit 18 as a red signal R via the switching circuit 28, so that the blanking signal is also displayed on the liquid crystal panel 10. As described above, since the blanking signal is displayed on the screen together with the horizontal and vertical synchronization signals, the blanking signal can be optimally adjusted on the screen.

As described above, according to this embodiment, the phase comparison inhibit signal, the clamp signal and the blanking signal are displayed on the screen together with the horizontal and vertical synchronizing signals. State can be set. Therefore, even if the phase of the phase comparison prohibition signal, the clamp signal, and the blanking signal are deviated from the optimal state due to the use of the above-described commercially available signal converter, they can be easily obtained without using an oscilloscope or the like. Can be reset to an optimal state.

In this embodiment, the switching circuit 28 and the on-screen circuit 18 correspond to supply means for supplying the composite synchronizing signal, the phase comparison inhibiting signal, the clamp signal, and the blanking signal to the liquid crystal panel 10 as video signals. The timing control circuit 12 corresponds to a shift unit that shifts the phase of the horizontal and vertical synchronization signals to be supplied to the liquid crystal panel 10. The adjusting circuit 26 corresponds to adjusting means for adjusting the phases of the phase comparison signal, the clamp signal, and the blanking signal. The liquid crystal panel 10 corresponds to display means for reproducing and displaying an image from a video signal in accordance with a horizontal and vertical synchronizing signal and a phase comparison inhibiting signal having a predetermined phase relationship with the synchronizing signal, a clamp signal, and a blanking signal.

[0034]

As described above, according to the present invention, a synchronization signal is displayed on a screen, and a control signal which must have a predetermined phase relationship with the synchronization signal is also displayed on the screen. In addition, since the phase of the control signal can be adjusted while checking it on the screen, the phase of the control signal can be easily adjusted to an optimum state without using a special device such as an oscilloscope. .

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of a display device according to an embodiment of the present invention.

FIG. 2 is a timing chart showing waveforms of respective signals in the display device shown in FIG.

FIG. 3 is a diagram showing a state where a horizontal and vertical synchronization signal and a phase comparison inhibition signal are displayed on a screen;
Shows a state in which only the horizontal and vertical synchronization signals are displayed, (b) shows a state in which an unadjusted phase comparison prohibition signal is also displayed, and (c) shows a state in which the adjusted phase comparison prohibition signal is displayed in the vertical synchronization state. This shows a state in which the display is superimposed on the signal.

4A and 4B are diagrams illustrating a state where a horizontal and vertical synchronization signal and a clamp signal are displayed on a screen, and FIG. 4A illustrates a state where an unadjusted clamp signal is displayed in addition to the horizontal and vertical synchronization signals. , (B) shows a state in which the adjusted clamp signal is displayed.

[Explanation of symbols]

 Reference Signs List 10 liquid crystal panel 12 timing control circuit 18 on-screen circuit 26 adjustment circuit 28 on-screen input switching circuit 32 CPU R, G, B video signal CL, CLA clamp signal BL, BLA blanking signal PH phase comparison inhibition signal CS composite synchronization signal HS Horizontal sync signal VS Vertical sync signal

Continuation of the front page (56) References JP-A-6-632 (JP, A) JP-A-4-207864 (JP, A) JP-A-4-349491 (JP, A) JP-A-4-78283 (JP) (A) JP-A-2-161885 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G09G 5/00 G09G 5/12 G09G 5/18 H04N 5/06 H04N 5/445

Claims (3)

(57) [Claims] [Claim 1] A sync signal is therefore a video signal and display means for displaying reproduced images, video supplied to the display means in response to a clamp signal
Clamp means for clamping a signal to a predetermined value; supply means for supplying the synchronization signal and the clamp signal to the display means as the video signal; shift means for shifting the phase of the synchronization signal supplied to the display means And a clamp supplied to the clamping means and the supply means.
A display device comprising: an adjusting unit that adjusts a phase of a pump signal. 2. A display means for reproducing and displaying an image from a video signal in accordance with a synchronization signal, and a blanking means for inserting a predetermined blanking period into a video signal supplied to the display means in response to a blanking signal. Supply means for supplying the synchronization signal and the blanking signal to the display means as the video signal; shift means for shifting the phase of the synchronization signal supplied to the display means; and the blanking means and the supply Adjusting means for adjusting the phase of the blanking signal supplied to the means. 3. A display means for reproducing and displaying an image from a video signal in accordance with a clock signal, a phase of a decoded synchronization signal including a synchronization signal and an aperiodic pulse signal, and a phase of a clock signal supplied to the display means. And a PLL circuit that synchronizes the clock signal with the decoding synchronization signal and does not perform the phase comparison while the phase comparison inhibition signal is supplied. Supply means for supplying the display means as a video signal; shift means for shifting the phase of a synchronization signal supplied to the display means; and adjustment of the phase of the phase comparison inhibition signal supplied to the PLL circuit and the supply means. A display device comprising: an adjusting unit that performs adjustment.