JP2000032296A - Planar display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the breakdown voltage of a display driving circuit. SOLUTION: This planar display device changes the level of the horizontal blanking period of video signals from video signal sources 11 and 12 by a selected voltage value from a voltage generation circuit 18, samples the voltage by a sampling clock from a timing generation circuit 15, latches it to a signal line driving circuit 21 and displays it corresponding to an aspect ratio on a planar display panel 14 together with scanning signals from a scanning line driving circuit 22.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat display device used for a car navigation system, for example.

[0002]

2. Description of the Related Art Hi-vision television receivers and car navigation systems which have recently become widely used have a flat display screen having an aspect ratio of 9:16. In particular, car navigation systems are designed to drive a flat display panel, such as a liquid crystal display panel, with a 12 volt DC power supply from a battery. If the pixel electrodes for driving the liquid crystal are increased in density to increase the resolution of the displayed image, the insulation characteristics of the panel will also be reduced, so a display drive circuit that drives the liquid crystal display panel with the lowest possible voltage is required. I do.

[0003]

However, a video signal needs to have a relatively large voltage amplitude between a black level and a white level in order to obtain sufficient contrast in an image displayed on a flat panel display. In addition, this video signal requires a voltage amplitude corresponding to the amplitude of the horizontal synchronizing signal incorporated therein. For this reason, it was difficult to lower the withstand voltage of the display drive circuit in the design.

An object of the present invention is to provide a flat display device having a configuration capable of reducing the withstand voltage of a display drive circuit.

[0005]

According to the present invention, there is provided a flat display panel and an analog video signal which is set to a reference level during a horizontal blanking period and changes from this reference level to a maximum level during a horizontal effective video period. And a display drive circuit for generating a display drive signal for driving the flat panel display panel based on the analog video signal from the video signal input unit. There is provided a flat panel display including a level conversion unit for converting a reference level of a video signal into an intermediate level selected from a range from the reference level to a maximum level.

In this flat panel display, the level converter converts the reference level of the analog video signal into an intermediate level selected in a level range corresponding to, for example, a black level and a white level during the horizontal blanking period. Therefore, when the horizontal synchronization signal is superimposed on the video signal during the horizontal blanking period, the maximum amplitude of the video signal can be limited. That is, since the ratio of the voltage amplitude of the horizontal synchronizing signal to the voltage amplitude of the video signal can be reduced, the withstand voltage of the display drive circuit can be reduced without deteriorating the contrast.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment in which the present invention is applied to a liquid crystal display device will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a circuit configuration of the liquid crystal display device 10.

The liquid crystal display device 10 is configured as, for example, a car navigation device, for example, an external video signal source 11 for generating an analog video signal representing an image having an aspect ratio of 9:16 together with a synchronizing signal, such as a high-definition television, and an NTSC television. An analog video signal representing an image having an aspect ratio of 3: 4, such as an image signal, is connected to an external video signal source 12 that generates an analog video signal together with a synchronizing signal, and one of these video signals is selected and captured by a video selection circuit 13. It is configured as follows.

The liquid crystal display device 10 includes a liquid crystal display panel 14 having a screen aspect ratio set to 9:16 as shown in FIG. Therefore, the high-vision signal image having the aspect ratio of 9:16 is displayed on the liquid crystal display panel 14.
Will be displayed on the entire screen. However, when displaying an NTSC signal image having an aspect ratio of 3: 4 on the liquid crystal display panel 14, if the vertical dimension is set to 9 in accordance with the high-vision signal image having an aspect ratio of 9:16, the horizontal direction is set. When the NTSC image is displayed in the display area RM at the center of the liquid crystal display panel 14 as shown in FIG. 2, for example, the remaining areas RA and RB having an aspect ratio of 9: 2 are provided on both sides thereof. Will be done.

As is generally well known, the liquid crystal display panel 14 has a plurality of pixel electrodes arranged in a matrix in a row direction and a column direction, and is formed along a row of these pixel electrodes to form a scan. A plurality of scanning lines for transmitting signals, a plurality of data signal lines formed along the columns of the pixel electrodes so as to intersect with the scanning lines in a three-dimensional manner, and a plurality of data signal lines formed at three-dimensional intersections of the scanning lines and the data signal lines An array substrate including a plurality of switching elements, and a counter substrate including a counter electrode commonly facing the plurality of pixel electrodes, and a liquid crystal layer held between the array substrate and the counter substrate. You.

Each switching element comprises a thin film transistor (TFT) having a gate connected to a scanning line and a current path connected between a data signal line and a pixel electrode. The thin film transistor is supplied to the gate via the scanning line. And the potential of the data signal line set according to the data signal is applied to the pixel electrode.

The screen of the liquid crystal display panel 14 is composed of a plurality of pixels including a plurality of pixel electrodes and switching elements corresponding to the pixel electrodes, a liquid crystal layer portion, and a counter electrode portion. It is controlled by a potential difference applied between the electrode and the counter electrode.

In the video selection circuit 13 of FIG. 1, a mode signal representing the selected video signal is formed, and this mode signal is supplied to the timing generation circuit 15. On the other hand, the selected video signal itself is supplied to the signal synthesis circuit 16.
The signal synthesizing circuit 16 is further configured to be supplied with a predetermined voltage signal generated by a voltage generating circuit 18 via a voltage selecting circuit 17 at a predetermined timing corresponding to a horizontal blanking period. The signal synthesizing circuit 16 outputs the selected video signal and voltage signal to the timing generating circuit 15.
This is a circuit for synthesizing in accordance with the switching control signal Ts generated during the horizontal blanking period from the step S1 as described later in detail.

The video signal synthesized by the signal synthesis circuit 16 is supplied to a gamma correction circuit 19. Generally, a received television image signal is subjected to gamma correction on the assumption that an image is reproduced on a screen of a CRT. Therefore, if an image is reproduced on the liquid crystal display panel 14 as it is, image reproduction between the CRT and the liquid crystal is performed. The difference in characteristics is reflected in the image density, and the quality of the reproduced image is not good. In particular, in the case of a color image, color reproducibility deteriorates. For this reason, the gamma correction circuit 19 is a circuit for restoring the gamma characteristic corrected for the CRT and further correcting the gamma characteristic in accordance with the image reproduction characteristic of the liquid crystal display panel 14.

The composite video signal corrected by the gamma correction circuit 19 is supplied to a polarity inversion circuit 20, and is output, for example, as a video signal whose polarity is inverted every horizontal period. This will be described later in detail.

The video signal whose polarity has been inverted is supplied to a signal line driving circuit 21 composed of a shift register circuit and latched, and a sampling clock signal CPH and a horizontal start signal supplied from a timing generation circuit 15 which will be described in detail later. The video signal latched in response to the signal STH is supplied to a signal line of the liquid crystal display panel 14 at a predetermined timing.

As described above, the signal line driving circuit 21 sequentially samples and holds the video signals supplied from the polarity inversion circuit 20 as data signals, and drives a plurality of data signal lines of the liquid crystal display panel 14 according to these data signals. Drive operation. Although not shown, the shift registers constituting the signal line driving circuit 21 have the same configuration as each other.
It is configured as first to fourth driver ICs that respectively drive the data signal lines divided into blocks.

Here, the number of data signal lines in one block is determined irrespective of the remaining areas RA and RB provided on both sides of the display area RM of the NTSC signal image having the aspect ratio of 3: 4 on the screen of the liquid crystal display panel 14. .
The first to fourth driver ICs are connected in series for sequentially transmitting the horizontal start signal STH, and each of the at least one driver IC is configured by a plurality of flip-flops connected in series corresponding to a data signal line of one block. Of shift registers.

Each shift register performs a shift operation of the horizontal start signal STH in response to the sampling clock signal CPH. The first to fourth driver ICs sample and hold the video signal at the timing when each flip-flop outputs the horizontal start signal STH, and supply the data signal to a data signal line corresponding to the flip-flop as a data signal.

On the other hand, the timing generation circuit 15 generates a vertical start signal STV and a vertical scanning clock signal CPV based on the mode signal and the horizontal synchronization signal received from the video selection circuit 13, and these signals STV and CPV are generated.
Is supplied to the scanning line driving circuit 22. This scanning line driving circuit 22 is also a shift register circuit composed of a plurality of flip-flops.

A shift register circuit constituting the scanning line driving circuit 22 shifts the vertical start signal STV in response to the vertical scanning clock signal CPV, and scan lines corresponding to flip-flops latching the vertical start signal STV. Output a scanning signal.

FIG. 3 shows the various signals CPH, STH,
FIG. 3 is a block diagram showing in detail a circuit configuration of a timing generation circuit 15 that generates timing signals such as CPV, STV, and Ts. This timing generation circuit 15 receives the signal CP
A scanning line drive control circuit 51 for outputting V and STV, and a PL for generating an internal clock signal synchronized with the horizontal synchronization signal
It has an L circuit 52, a signal line drive control circuit 61 for generating signals CPH and STH, a video processing control circuit 57 for outputting a switching control signal Ts, and a polarity inversion signal generation circuit PG for generating an inversion instruction signal POL. .

The PLL circuit 52 includes a phase comparison circuit 53, a loop filter 54, and a voltage controlled oscillator (VCO) 55
And a counter 56. In the PLL circuit 52, for example, the phase error between the phase of the horizontal synchronization signal separated from the video signal by a synchronization separation circuit (not shown) included in the video selection circuit 13 and the phase of the reference horizontal clock signal supplied from the counter 56 is calculated. The comparison circuit 53 detects the error and generates an error signal corresponding to the phase error.

The loop filter 54 generates a signal voltage obtained by removing high-frequency components and noise from the error signal obtained from the phase comparison circuit 53. VCO 55 is a loop filter 54
And generates a pulse signal having an oscillation frequency corresponding to the signal voltage obtained as the reference sampling clock signal, and supplies the reference sampling clock signal to the counter 56. The counter 56 divides the frequency of the reference sampling clock signal based on the number of pixels for one row of the image displayed on the entire screen of the liquid crystal display panel 14 having an aspect ratio of 9:16, and outputs the frequency-divided reference horizontal clock signal to the phase comparison circuit 53. Supply. The reference horizontal clock signal and the reference sampling clock signal are further supplied to a scanning line drive control circuit 51, a signal line drive control circuit 61, and a video processing control circuit 57.

The video processing control circuit 57 includes a video selection circuit 13
And a switching control signal Ts for controlling the operation of the video signal synthesizing circuit 16 based on the mode signal M from the counter 56 and the reference horizontal clock signal from the counter 56. In the NTSC mode, the switching control signal Ts is supplied from the video processing control circuit 57 to the signal synthesizing circuit 16 in order to make the voltage signal from the voltage generation circuit 18 valid during the horizontal blanking period of the NTSC video signal.

The signal line drive control circuit 61 has a sampling start control circuit 62 for controlling the start timing of the sampling operation of the video signal, and a clock adjustment circuit 63 for adjusting the reference sampling clock signal supplied from the PLL circuit 52.

In the sampling start control circuit 62, control signals such as a horizontal start signal STH and a phase control signal are generated at a predetermined timing in synchronization with a reference horizontal clock signal supplied from the counter 56. These predetermined timings are confirmed based on the number of clocks of the reference sampling clock signal supplied from the PLL circuit 52.

The clock adjusting circuit 63 has a sampling clock generating circuit 65 for generating a sampling clock signal CPH of the first or second frequency from the reference sampling clock signal. This circuit 65 is controlled by the sampling start control circuit 62. The control is performed by a clock frequency control circuit 64 and a sampling start control circuit 62 which generate a frequency switching signal for controlling the switching between the first and second frequencies. Further, the clock adjustment circuit 63 has a clock stop control circuit 66 that generates a prohibition signal for temporarily stopping the sampling clock signal CPH. First of sampling clock signal CPH
The frequency is a sampling frequency for a Hi-Vision video signal, and the second frequency is a frequency for an NTSC video signal.

The frequency switching signal from the clock frequency control circuit 64 selects the first frequency in the HDTV mode. In the NTSC mode, it selects the first frequency during the horizontal blanking period of the NTSC video signal, and selects one horizontal line of the NTSC video signal. In the image display (or effective video) period excluding the horizontal blanking period from the scanning period, a lower second frequency is selected.

The inhibit signal is not generated in the high vision mode, but is generated in the NTSC mode corresponding to the first and second frequency transition periods of the sampling clock signal CPH. That is, in the sampling clock signal generation circuit 65, the sampling clock signal CP
The frequency of H is switched according to the frequency switching signal during the duration of the inhibit signal.

At this time, the sampling clock signal CP
The phase of H is appropriately adjusted by the phase control signal from the sampling start control circuit 62.

Here, the configuration and operation of the sampling clock signal generation circuit 65 will be described in more detail with reference to FIGS. As described above, in this liquid crystal display device, the high vision video signal is displayed as an image having an aspect ratio of 9:16 on the entire screen of the liquid crystal display panel 14 shown in FIG. 2 in the high vision mode, and the NTSC video signal is displayed in FIG. Display area RM shown
Is displayed as an image having an aspect ratio of 3: 4.

Therefore, the high-definition video signal and N
The TSC video signal needs to be sampled by the number of pixels corresponding to these aspect ratios in the effective video period T1 in each horizontal scanning period (1H), an example of which is shown in FIG. Since one horizontal scanning period (1H) is common between the HDTV video signal and the NTSC video signal, the sampling frequency fl of the HDTV video signal and the sampling frequency f2 of the NTSC video signal have a relationship of 3f1 / 4 = f2, Therefore, there is a relationship of 3 × fl = 4 × f2 (1).

Since one horizontal scanning period (1H) of a video signal includes a horizontal blanking period (B1 + B2) as shown in FIG. 6A, a period T1 excluding the horizontal blanking period (B1 + B2) is included. This is a substantial sampling period of the video signal. Since this blanking period occupies about 20% of the whole, the sampling period T1 is, for example, as follows.

T1 = 0.8H (2) In the NTSC mode, the remaining areas RA and RB remain on both sides of the display area RM of the NTSC signal image in FIG. 2. Here, the aspect ratio is 9: 2
May be displayed.

The synthesizing circuit 16, the voltage selecting circuit 17 and the voltage generating circuit 18 shown in FIG. 1 are circuits for displaying the left and right auxiliary images.
The total voltage of the voltage Vs of the horizontal synchronization signal Hsync and the maximum amplitude voltage Vd of the black level and the white level during the sampling period T1 of the substantial video signal shown in (a) is the signal line drive circuit 21 and the scan line drive. In order to prevent the voltage from being applied to the circuit 22, a plurality of voltages V2, V3, V4, V5 as shown in FIG. At such timing, one of these voltages is selected by the switching signal Ts generated from the timing generation circuit 15 and synthesized with the video signal.

For example, when the voltage V2 is selected, FIG.
As shown in the figure, the voltage amplitude of the horizontal synchronization signal Hsync is Vs
From the voltage V2, and the voltage load on the drive circuit is reduced accordingly. At this time, there is no change in the black level during the horizontal blanking period.
The display of B is black.

On the other hand, when the voltage V4 or V5 is selected, the voltage level in the combined horizontal blanking period becomes higher than the black level. If this part is sampled and displayed as the left and right auxiliary images, the remaining area R
The display of A and RB changes from black to gray.

At this time, the horizontal blanking period (B1
+ B2) is a substantial video signal sampling period, and there is no change in the display content during this period.
Moreover, the voltage burden on the drive circuit is reduced by the voltage amplitude of the horizontal synchronization signal.

In order to display the auxiliary image in the remaining areas RA and RB, the auxiliary image signal has an aspect ratio of 9: 4 during a blanking period (B1 + B2) of 0.2H.
Need to be sampled by the number of pixels corresponding to

The number of pixels is, as shown in FIG. 6A, a sampling period T2 of the auxiliary image signal corresponding to the left auxiliary image and a sampling period T3 of the auxiliary image signal corresponding to the right auxiliary image and the product of the sampling frequency f3. And the product of the sampling frequency f4 and the relationship between the number of pixels and the number of pixels which is the product of the sampling period T1 of the NTSC video signal and the sampling frequency f2, as shown in the following equation, This corresponds to the relationship between the total aspect ratio 9: 4 and the aspect ratio 9:12 of the display area RM.

T1 × f2: T2 × f3 + T3 × f4 = 12: 4 (3) When T1 in the above equation is arranged as 0.8, this relational expression is expressed as T2 × f3 / f2 + T3 × f4 / f2 = 0.8H / 3 ... (4)

Here, the sampling frequency f3 of the auxiliary video signal corresponding to the left auxiliary image and the sampling frequency f4 of the auxiliary video signal corresponding to the right auxiliary image are (4)
In order to satisfy the expression, it is necessary to set the sampling frequency f2 higher than the sampling frequency f2 of the NTSC video signal.

The sampling clock signal generating circuit 65 shown in FIG. 3 has such sampling frequencies f3 and f3.
4 are not required to be generated independently.

FIG. 4 shows the circuit configuration of the sampling clock signal generation circuit 65 in more detail, and FIG. 5 shows signals obtained in the sampling clock signal generation circuit 65. In this sampling clock signal generation circuit 65,
The first frequency clock signal CK1 is used as the sampling frequency fl of the HDTV video signal, and the second frequency clock signal CK2 is used as the sampling frequency f2 of the NTSC video signal.

Further, the first frequency CK1 is the second frequency CK
Since it is set higher than 2, it can be used as the sampling frequencies f3 and f4 of the auxiliary video signal. That is, the sampling clock signal generating circuit 65 includes a first frequency dividing circuit 71, a second frequency dividing circuit 72, a switching circuit 73, and a prohibiting circuit 74.

The first frequency divider 71 divides the frequency of the reference sampling clock signal into a clock signal CKI of a first frequency.
The second frequency divider 72 divides the frequency of the reference sampling clock signal into a clock signal CK2 of a second frequency. In the first frequency dividing circuit 71 and the second frequency dividing circuit 72, the phases of these clock signals CKI and CK2 are controlled by the phase control signal from the sampling start control circuit 62.

The switching circuit 73 switches between the clock signal CKI and the clock signal CK2 according to the clock switching signal from the clock frequency control circuit 64, and outputs these as the output clock signal CK3. The prohibition circuit 74 masks the output clock signal CK3 obtained from the switching circuit 73 with the prohibition signal from the clock stop control circuit 66 and outputs it as a sampling clock signal CPH.

Here, the operation of the above-described liquid crystal display device will be described.

When the video selection circuit 13 selects the high vision mode, the mode selection signal M is supplied to the timing generation circuit 15 and the horizontal synchronizing signal Hsync for the high definition video signal is generated through a switch circuit (not shown). It is supplied to the circuit 15. At the same time, the high definition video signal is supplied to the signal synthesizing circuit 16.

On the other hand, when the video selection circuit 13 selects the NTSC mode, the horizontal synchronizing signal for the NTSC video signal is supplied to the timing generation circuit 15 via the switch circuit, and the NTSC video signal and the voltage generation circuit 18 The selected voltage and the selected voltage are supplied to the signal synthesizing circuit 16 via a switch circuit for forming a synthetic video signal.

The timing generation circuit 15 outputs the horizontal synchronizing signal H
generating a reference sampling clock signal from sync,
A horizontal clock signal is generated from the reference sampling clock signal, and the scanning line driving circuit 22 and the signal line driving circuit 21 are controlled every one horizontal scanning period (1H) defined by the horizontal clock signal.

In the control of the signal line driving circuit 21, the horizontal start signal STH is generated from the horizontal clock signal, and the sampling clock signal CPH is generated from the reference sampling clock signal.

The scanning line driving circuit 22 sequentially drives a plurality of scanning lines in one vertical scanning period. In each horizontal scanning period, a scanning signal is continuously supplied to the corresponding scanning line. The signal line drive circuit 21 drives a plurality of signal lines in one horizontal scanning period (1H) in accordance with the video signal supplied from the signal synthesis circuit 16. In the driver IC included in the signal line driving circuit 21, the shift register performs a shift operation of the horizontal start signal STH in response to the sampling clock signal CPH. The high-definition video signal is sampled and held as a data signal at the timing when the horizontal start signal STH is stored and output in each flip-flop, and is supplied to the data signal line 34 corresponding to the flip-flop.

As a result, in the high vision mode, a high vision signal image having an aspect ratio of 9:16 is displayed on the entire screen of the liquid crystal display panel 14 shown in FIG.
In the NTSC mode, an NTSC signal image having an aspect ratio of 3: 4 is displayed in the display area RM shown in FIG. 2, and a left auxiliary image and a right auxiliary image of a predetermined gray level are displayed in the remaining areas RA and RB shown in FIG. Is done.

Here, the operation of displaying a left auxiliary image and a right auxiliary image of a predetermined gray level in the NTSC mode will be described in more detail with reference to FIG.

In the NTSC mode, the timing generation circuit 15 controls the horizontal blanking period (B) of the NTSC video signal.
1 + B2), and generates a video switching signal Ts.

The voltage selection circuit 17 receives the video switching signal Ts
, A predetermined voltage generated from the voltage generation circuit 18 is selected and supplied to the signal synthesis circuit 16 to be synthesized with the video signal from the video selection circuit 13. The synthesized video signal output from the signal synthesis circuit 16 is supplied to a polarity inversion circuit 20 via a gamma correction circuit 19.

The polarity inversion circuit 20 is for inverting the polarity of the video signal every one horizontal scanning period (1H) to prevent deterioration of the characteristics of the liquid crystal. For example, the video signal shown in FIG. The polarity is inverted by the polarity inversion circuit 20 every 1H, and a waveform as shown in FIG. 7 is obtained. The video signal shown in FIG. 7 shows a video signal waveform before performing the voltage synthesis of the present invention, and the voltage amplitude Vs of the horizontal synchronization signal Hsync is added to the voltage amplitude Vd substantially used for image display. The voltage Vs + Vd is applied to the drive circuits 21 and 22.

More specifically, the driving circuits 21 and 22 have a withstand voltage of 5
In the case of V, the voltage amplitude Vd is set to, for example, 3 V from 1 V to 4 V in consideration of the voltage loss in the drive circuits 21 and 22. Considering that the video signal is subjected to the gamma correction for the liquid crystal display panel 14, if the reference level of the video signal is set to about 2.1V which is slightly shifted from 2.5V which is an intermediate value between 1V and 4V, horizontal synchronization can be achieved. Even when the voltage amplitude Vs of the signal is superimposed on the voltage amplitude Vs video signal,
The above-described drive circuits 21 and 22 can be reliably operated at a withstand voltage of 5V.

In the present invention, if the voltage value generated by the voltage generating circuit 18 is selected more appropriately, the driving circuits 21 and 2
2 is set in the range of the voltage amplitude Vd substantially used for image display, while the left auxiliary image and the right auxiliary image of a predetermined gray level are displayed in the areas RA and RB, respectively. can do.

When displaying the left auxiliary image in the area RA, while the composite video signal is output from the polarity inversion circuit 20, the horizontal start signal STH formed based on the horizontal synchronizing signal Hsync and the sampling of the first frequency are performed. The clock signal CPH is supplied from the timing generation circuit 15 to the signal line drive circuit 21.

In the signal line driving circuit 21, the sampling of the auxiliary video signal corresponding to the left auxiliary image, that is, the sampling of the voltage of a predetermined value generated from the voltage generating circuit 18, is performed at the first frequency (CK1) after the horizontal start signal STH is supplied. This is performed in response to the sampling clock signal CPH, and data signals are generated by the number of data signal lines corresponding to the remaining area RA,
The data is supplied to these data signal lines.

When the sampling is completed for the last data signal line among the data signal lines corresponding to the remaining area RA, the inhibit signal shown in FIG. 5 is supplied from the clock stop control circuit 66 of FIG. , The sampling clock signal CPH stops for a predetermined period.

During this time, the phase control signal and the frequency switching signal are supplied from the sampling start control circuit 62 and the clock frequency control circuit 64 to the sampling clock generating circuit 65, respectively, and the video switching signal Ts is supplied from the voltage generating circuit 18 Signal to video selection circuit 13
Change to switch to the NTSC video signal from.

The signal synthesizing circuit 16 outputs the video switching signal Ts
Changes from the NTSC video signal source 12
Outputs SC video signal. When the supply of the above-described prohibition signal shown in FIG. 5 is stopped with the output of the NTSC video signal, the sampling clock generating circuit 65 starts generating the sampling clock signal CPH of the second frequency (CK2).

In the signal line driving circuit 21, sampling of the NTSC video signal is performed in response to the sampling clock signal CPH of the second frequency (CK2), and data signals are generated by the number of data signal lines corresponding to the display area RM. And supplied to these data signal lines. When this sampling is completed for the last data signal line among the data signal lines corresponding to the display area RM, the prohibition signal is supplied again from the clock stop control circuit 66 to the sampling clock generation circuit 65, and the sampling clock signal CPH is output only for a predetermined period. Stop.

During this time, the phase control signal and the frequency switching signal are supplied from the sampling start control circuit 62 and the clock frequency control circuit 64 to the sampling clock generating circuit 65, respectively, and the video switching signal Ts is set to NT.
It changes to switch the SC video signal to the auxiliary video signal for displaying the right region RB.

The signal synthesizing circuit 16 outputs the video switching signal Ts
Voltage generating circuit 18 for the auxiliary video signal in accordance with the change of
Output the auxiliary video signal from. When the supply of the above-described prohibition signal is stopped with the output of the auxiliary video signal, the sampling clock generation circuit 65 starts generating the sampling clock signal CPH of the first frequency (CK1). In the signal line drive circuit 21, the sampling of the auxiliary video signal corresponding to the right auxiliary image is performed in response to the sampling clock signal CPH of the first frequency (CK1), and the data signal is output to the data signal line corresponding to the remaining area RB. The number is generated and supplied to these data signal lines.

Subsequently, the sampling operation of the auxiliary video signal corresponding to the next left auxiliary image is performed, and the above-described operation is repeated.

In this way, the left auxiliary image is displayed as shown in FIG.
The sampling operation in the first half period T2 of the horizontal blanking period (B1 + B2) shown in (a) is displayed in the left residual area RA, and the NTSC signal image is displayed in the display area RM by the sampling operation in the period T1. The right auxiliary image is displayed in the remaining area RB by the sampling operation in the latter half period T3 of the horizontal blanking period (B1 + B2).

In the liquid crystal display device of the embodiment described above, N
The TSC video signal is sampled in synchronization with the sampling clock signal CPH of the second frequency CK2, and the auxiliary video signal is output from the first frequency CK higher than the second frequency CK2.
The sampling is performed in synchronization with one sampling clock signal CPH.

Therefore, the sampling of the auxiliary video signal can be completed using the horizontal blanking period of the NTSC video signal. Therefore, the signal line driving circuit 21
Does not need to independently drive the plurality of data signal lines corresponding to the remaining areas RA and RB provided on both sides of the NTSC signal image display area RM from the plurality of data signal lines corresponding to the NTSC signal image display area RM. . For this reason,
The number of data signal lines of one block driven by each of the driver ICs can be set regardless of the number of data signal lines corresponding to the remaining areas RA and RB. That is, in this liquid crystal display device, when an image having a high aspect ratio is switched to an image having a low aspect ratio, the center of the image having a low aspect ratio is centered on the image having a high aspect ratio so as not to give an uncomfortable feeling to an observer. Can be easily matched to

Further, the configuration of this liquid crystal display device does not require an increase in circuit occupation area and cost depending on the number of driver ICs.

Further, since the sampling clock signal CPH of the first frequency CK1 is for a high-definition video signal, an independent sampling clock signal generating circuit is not required for sampling the auxiliary video signal. Further, the sampling clock signal generation circuit 65 temporarily stops the generation of the sampling clock signal CPH during a period necessary for switching the clock frequency under the control of the clock stop control circuit 66. Can be set to a phase suitable for the sampling of.

In this embodiment, since the selected voltage generated by the voltage generation circuit 18 and synthesized by the signal synthesis circuit with the video signal is supplied to the gamma correction circuit 19,
A plurality of voltages generated from the voltage generation circuit 18 are selectively supplied to the gamma correction circuit 19, and this voltage is used for correcting the gamma curve. Therefore, since the selected voltage value is known, the degree of gamma correction has a one-to-one correspondence with the selected voltage value. Therefore, adjustment of gamma correction and operation confirmation can be easily and accurately performed through this voltage value.

In the conventional gamma correction, the gamma curve is displayed on an oscilloscope and is visually checked, which is troublesome and inaccurate. If the color displayed on the display device is different due to the individual difference of the operator performing the adjustment. However, in the present invention, the degree of gamma correction is accurately indicated by the voltage value with the selected voltage value, and extremely excellent gamma correction can be performed.

The above description has been given of the embodiment in which the present invention is applied to a liquid crystal display device. However, the present invention is not limited to this, and can be applied to various flat display devices such as a plasma display device.

[0080]

As described above, according to the present invention, when an image having an aspect ratio of 3: 4 is displayed on a flat display panel having an aspect ratio of 9:16, a video signal during a horizontal blanking period is displayed. Since the level of the horizontal synchronizing signal is selectively changed by a plurality of voltage values from the voltage generation circuit to reduce the maximum voltage value applied to the display drive circuit,
It is possible to provide a flat display device which can be designed by lowering the withstand voltage value of the display drive circuit and can be easily and accurately performed gamma correction.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a circuit configuration according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram in a case where an image having an aspect ratio of 3: 4 (9:12) is displayed on a display panel having an aspect ratio of 9:16.

FIG. 3 is a block diagram showing an internal configuration of the timing generation circuit of FIG. 1 in detail.

FIG. 4 is a block diagram showing an internal configuration of a sampling clock signal generation circuit of FIG. 3 in detail;

FIG. 5 is a timing chart showing an operation of the circuit of FIG. 4;

FIG. 6 is a signal waveform diagram illustrating an operation of the embodiment of FIG. 1;

FIG. 7 is a diagram illustrating a video signal whose polarity is inverted.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Liquid crystal display device 11, 12 ... Video signal source 13 ... Video selection circuit 14 ... Liquid crystal display panel 15 ... Timing generation circuit 16 ... Signal synthesis circuit 17 ... Voltage selection circuit 18 ... Voltage generation circuit 19 ... Gamma correction circuit 21, 22 … Drive circuit

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H04N 5/202 H04N 5/202 5/66 5/66 D

Claims (6)

[Claims] 1. A flat display panel, a video signal input unit receiving an analog video signal which is set to a reference level in a horizontal blanking period and changes in a range from the reference level to a maximum level in a horizontal effective video period, and A display driving circuit for driving the flat panel display panel based on an analog video signal from a signal input unit, wherein the display driving circuit changes a reference level of the analog video signal from the reference level to a maximum level during a horizontal blanking period. A flat display device, comprising: a level conversion unit for converting an intermediate level selected in a range. 2. A flat display panel comprising a plurality of pixels and having a display screen having a first aspect ratio, wherein the analog video signal is superimposed with a horizontal synchronizing signal in the horizontal blanking period, and in the horizontal effective video period. The display drive circuit is configured to represent an image having a second aspect ratio larger than the first aspect ratio, and the display driving circuit is configured to display the image on the display screen of the flat panel display panel in the horizontal effective image period. A sampling section for sampling the analog video signal during the horizontal blanking period to display an image in a remaining area where the image of the second aspect ratio is not displayed in the display area. Item 2. The flat panel display according to item 1. 3. The level conversion section includes a voltage generation section that generates a plurality of voltage levels different from each other, and a plurality of voltages generated by the voltage generation section is selectively superimposed on the video signal during the horizontal blanking period. The flat panel display according to claim 2, further comprising a signal synthesizing unit. 4. The flat display device according to claim 3, wherein the display drive circuit further includes a polarity inversion circuit for inverting the polarity of the video signal every predetermined period. 5. The flat display device according to claim 4, wherein the display driving circuit includes a gamma correction circuit for performing gamma correction on the video signal at a stage preceding the polarity inversion circuit. 6. The gamma correction circuit according to claim 1, wherein the video signal is C
The flat display device according to claim 5, wherein when the gamma correction is performed for RT, the gamma correction is canceled and the gamma correction is performed for the flat display panel.