JPH084331B2 - Image display device - Google Patents

Description

The present invention relates to an image display device for displaying an image of a television signal on an image display having a liquid crystal display element or the like as a pixel, and the like. In particular, the present invention relates to an apparatus adapted to display a television signal transmitted by a plurality of television systems having different horizontal scanning lines in one field.

(Prior Art) Recently, an image display (liquid crystal panel) having a liquid crystal display element as a pixel has been widely used because of its small size and low power consumption. In particular, in television receivers, twisted nematic (NT) mode liquid crystal capable of gradation display is often used. further,
At present, a liquid crystal color television receiver capable of color display has also appeared by combining with color filters of three primary colors of red (R), green (G) and blue (B).

FIG. 6 shows a color television receiver using such a conventional liquid crystal panel. That is, reference numerals 11, 12, and 13 in the figure are input terminals to which the color signals R, G, and B are supplied, respectively. The respective color signals R, G, B supplied to these input terminals 11, 12, 13 are respectively supplied to the polarity inverting circuit 14 composed of the positive polarity amplification circuits 14a, 14b, 14c and the negative polarity amplification circuits 14d, 14e, 14f. It

Here, the polarity inversion circuit 14 amplifies each color signal R, G, B with positive polarity and negative polarity, respectively, and generates a bipolar signal for enabling AC drive necessary to prevent deterioration of the liquid crystal. It is a thing. The output signal of the polarity reversing circuit 14 is the polarity switching circuit 15 composed of the switches 15a, 15b, 15c.
Is supplied to. The polarity switching circuit 15 synchronizes with the frame pulse FP output from the timing generation circuit 16 and the positive polarity amplification circuits 14a, 14b, 14c and the negative polarity amplification circuits 14d, 14e, 1
An AC signal is generated by selecting each output of 4f.

Then, the color signals R, G, selected by the polarity switching circuit 15 are
B is supplied to the color switching circuit 17 including switches 17a, 17b and 17c. This color switching circuit 17 is the timing generation circuit described above.
The color signals R, G, B output to the signal lines a, b, c are switched in synchronization with the horizontal timing signal HP output from 16.

Here, the color signals R, G, B output to the signal lines a, b, c
Is supplied to the X driver 18. This X driver 18
Is the clock SCK output from the timing generation circuit 16.
Shift register 19 for generating clocks in the order of S1, S2, ..., S480 based on the above, and color signals R, G, supplied to signal lines a, b, c in accordance with the output clock of this shift register 19. Based on the buffer 20 that outputs B, the line memory 21 that holds the output of this buffer 20, and the color signals R, G, and B that are held in this line memory 21 based on the clock OE that is output from the timing generation circuit 16. It comprises an output buffer 22.

The clock SCK is obtained by equally dividing the image display period during the horizontal scanning period by the number of horizontal pixels (480), and the clock OE is generated during the blanking period in synchronization with the horizontal scanning synchronization signal. Is.

And the output of the above X driver 18, D1, D2, ..., D480
Are supplied to the column electrodes 23a, 23a, ... Of the liquid crystal panel 23, respectively. The liquid crystal panel 23 includes the column electrodes 23a, 23a, ...
, And the row electrodes 23b, 23b, ... Orthogonal to the column electrodes 23a, 23a ,.
, And a plurality of pixels 24, 24, ... Which are arranged in a matrix in the horizontal and vertical directions. And
The pixels 24, 24, ... connected to the row electrodes 23b, 23b, ... to which signals are supplied are output D1, D2, ..., D of the X driver 18.
A display corresponding to 480 is performed.

Here, the row electrodes 23b, 23b, ...
Signals are selectively supplied by the outputs L0, L1, ..., L219 of the shift register 26 of FIG. That is, the shift register 26
Is L0, L1, ..., L219 based on a clock HCK generated in synchronization with the horizontal scanning synchronization signal from the timing generation circuit 16.
The signals are generated in the order of, and each row electrode 23b, 23b, ...
Are sequentially scanned in the vertical direction.

Therefore, each pixel 24, 24, ... Has a color signal R, which is sampled by the X driver 18 for the number of horizontal pixels.
G and B are supplied so as to be scanned in the vertical direction for each horizontal scanning period, and image display is performed.

In this case, the shift register 26 outputs the output signals L0, L to the row electrodes 23b, 23b, ... While the gate pulse GE is generated from the timing generation circuit 16 in response to the clock HCK.
1, ..., L219 are generated and are cleared based on the clear pulse FCL generated in synchronization with the vertical blanking period.

Here, in the pixels 24, 24, ..., As shown in FIG. 7, the control electrodes are connected to the row electrodes 23b, 23b ,. The connected thin film transistor (hereinafter referred to as TFT) 24a and the liquid crystal 24b connected in parallel between the other controlled electrode of this TFT 24a and the common electrode.
And a capacitor 24c. When a signal is supplied from the Y driver 25 to the row electrodes 23b, 23b, ..., The TFT 24a is turned on and the output of the X driver 18 is supplied to the liquid crystal 24b and the capacitor 24c. in this case,
The signal level supplied to the liquid crystal 24b is held constant by the capacitor 24c for at least one vertical scanning period.

FIG. 8 is a timing chart showing the operation of the liquid crystal color television receiver described above. That is, when the clock SCK is supplied to the shift register 19, the outputs S1, S2, ..., S480 are sequentially generated in synchronization with the rising edge thereof.
Now, assuming that the horizontal timing signal HP is at L (low) level and the color signals R, G, B are supplied to the signal lines a, b, c, respectively, the outputs S1, S2, ..., Of the shift register 19 are output. By S480,
The color signals are sequentially sampled in the order of R, G, B, R, G, B, ... And held in the line memory 21.

When the sampling for one horizontal pixel is completed, the clock OE generated during the horizontal blanking period becomes H (high) level, and the content of the line memory 21 is output via the buffer 22 to the output D1, of the X driver 18. D2, ..., D480
Are simultaneously supplied to the respective column electrodes 23a, 23a, ... Of the liquid crystal panel 23. At this time, the horizontal timing signal HP becomes H level in synchronization with the clock OE, the switches 17a, 17b, 17c of the color switching circuit 17 are switched, and the color signals B, R, G are respectively supplied to the signal lines a, b, c. Will be supplied.

On the other hand, when the gate pulse GE is supplied, the shift register 26 of the Y driver 25 sets any one of its outputs L0, L1, ..., L219 (L0 in FIG. 8) to the H level.
Then, all the TFTs 24a constituting the 480 pixels 24, 24, ... In the first row in the horizontal direction are turned on, and
The liquid crystal display of the line is performed.

After that, when the clock HCK is generated, the clock OE becomes L level, and the shift register 26 tries to set the output L0 to L level and the output L1 to H level. However, since the gate pulse GE is not generated at this point, the output
L1 remains L level.

Then, the X driver 18 sets 1 based on the clock SCK.
Color signals for the number of horizontal pixels are sampled and clocked
The liquid crystal display of the second row in the horizontal direction is performed in synchronization with OE and the gate pulse GE, and the same operation is repeated for 220 lines, so that the image display for one field is performed.

By the way, as described above, in the small liquid crystal panel 23 of 4 inches or less having the number of horizontal lines of about 220, as shown in FIG. 9, the odd fields Om, Om + of the television signal are
1, Om + 2, ... signals and even fields Em, Em + 1, Em +
By supplying the signals of 2, ... To the same horizontal line, one frame is displayed.

However, for example, in the case of an NTSC television signal, since the number of effective horizontal scanning lines in one field is about 240, the liquid crystal panel 23 having 220 horizontal lines has 8.3
% Overscan rate will occur. Also, PA
Since the number of effective horizontal scanning lines in one field is generally about 285 in the L system television signal, the liquid crystal panel 23 has an overscan rate of 22.8%.

That is, since the liquid crystal panel 23 has a fixed number of horizontal lines unlike a cathode ray tube, for example, in a liquid crystal panel in which the number of horizontal lines is set corresponding to the number of horizontal scanning lines of the NTSC system, the PAL system (horizontal scanning) is used. There is a problem that it is not possible to display satisfactorily the number of lines is 100 more per frame than the NTSC system.

Therefore, conventionally, in order to absorb the difference in the number of scanning lines due to the difference in such a television system and enable the display of the PAL system television signal even in the liquid crystal panel for NTSC, for example, as shown in FIG. A color television receiver provided with various conversion means has been considered. That is, in the figure
51 is an input terminal for NTSC television signals and PAL
The television signal of the system is selectively supplied.

First, when a television signal of the NTSC system is supplied to the input terminal 51, the television signal is demodulated into a luminance signal YN, a color signal CN and a synchronizing signal SN by the signal processing circuit 52 for NTSC, and then the NTSC signal. The luminance signal YN and the color signal CN are demodulated by the use matrix circuit 53 into the three primary color signals RN, GN and BN. The three primary color signals RN, GN, BN are derived by the NTSC / PAL changeover switch 54 which is switched to the switching state opposite to that shown in the drawing, and the polarity switching circuit 55 having the same configuration as that described in FIG. It is supplied to the liquid crystal panel 56 for NTSC via and is used for image display.

When a PAL system television signal is supplied to the input terminal 51, the television signal is demodulated by the PAL signal processing circuit 57 into a luminance signal YP, a chrominance signal CP, and a synchronization signal SP, and then PAL. The luminance signal YP and the color signal CP are demodulated by the use matrix circuit 58 into the three primary color signals RP, GP and BP. The three primary color signals RP, GP, BP are respectively converted by the PAL / NTSC conversion circuits 59, 60, 61 into three NTSC synchronous three primary color signals RN ', G.
After being converted into N ', BN', it is led out by the NTSC / PAL conversion switch 54 which is switched to the switching state shown in the figure, supplied to the liquid crystal panel 56 for NTSC via the polarity switching circuit 55, and provided for image display. It

Here, the PAL / NTSC conversion circuit 59 will be described.
However, since the other PAL / NTSC conversion circuits 60 and 61 have the same configuration as the PAL / NTSC conversion circuit 59, the description thereof will be omitted.
That is, the analog primary color signal RP output from the PAL matrix circuit 58 is supplied to the A / D (analog / digital) conversion circuit 59a, quantized into about 8 bits at a sampling frequency of about 17.7 MHz, and converted into digital data. To be converted. Of the digital data output from the A / D conversion circuit 59a, the odd field component is the frame memory.
59b, the even field components are stored in frame memory 5
Stored in 9c.

Here, the digital data stored in the frame memories 59b and 59c are read so that one horizontal line is thinned out for every predetermined number of horizontal lines, and the line memory 59d is read.
After being read at the NTSC sync timing with
The (digital / analog) conversion circuit 59e converts it into an NTSC-synchronized analog primary color signal RN 'and outputs it to the NTSC / PAL switch 54. That is, when a PAL system television signal is supplied, PAL / NTSC conversion circuits 59, 60, 61
LCD panel for NTSC 56 by thinning out horizontal lines with
The PAL system television signal image display is enabled.

However, the conversion means as described above requires three PAL / NTSC conversion circuits 59, 60, 61 for digitizing the three primary color signals RP, GP, BP and thinning out horizontal lines. In many cases, the structure is complicated and economically disadvantageous. For example, it is not suitable for a so-called small-sized television receiver such as a pocket type or a vehicle-mounted type.

(Problems to be Solved by the Invention) As described above, in the conventional image display device using the liquid crystal panel, all the television signals transmitted by the systems having different horizontal scanning lines cannot be displayed well. I have a problem. In particular, a means for converting a PAL system television signal into an NTSC system has a disadvantage that it has a complicated structure, is not suitable for miniaturization, and is economically disadvantageous.

Therefore, the present invention has been made in consideration of the above circumstances, and can cope with the display of television signals transmitted by a plurality of television systems in which the number of horizontal scanning lines in one field is different, and has a simple configuration. It is an object of the present invention to provide an extremely good image display device which is suitable for miniaturization and is economically advantageous.

[Structure of the Invention] (Means for Solving the Problems) That is, the image display device according to the present invention has a pixel at each intersection of a plurality of horizontal signal lines and vertical signal lines arranged in a matrix. And a television signal sampled by the number of pixels in the horizontal direction are supplied to each of the vertical signal lines of the image display in which the television signal is installed in synchronization with the horizontal scanning period of the television signal. By supplying the horizontal direction driving means and a clock synchronized with the horizontal scanning period of the input television signal,
The horizontal signal lines are supplied to the vertical signal lines of the image display device by the horizontal driving means so that the horizontal signal lines of the image display device are sequentially scanned in the vertical direction in synchronization with the horizontal scanning period of the television signal. And a vertical drive means for supplying a signal for displaying a television signal to each pixel.

Then, based on the control signal of the first polarity, a clock synchronized with the horizontal scanning period of the input television signal is thinned out in a predetermined cycle and supplied to the vertical driving means,
A gate means is provided which is switched based on the control signal of the second polarity so as to supply the clock synchronized with the horizontal scanning period of the input television signal to the vertical driving means without thinning out. is there.

(Operation) According to the above configuration, when the number of horizontal scanning lines of the input television signal is larger than the number of horizontal signal lines of the image display device, the gate means has the first polarity. By supplying the control signal of (1), the operation of the vertical driving means can be temporarily stopped at every predetermined horizontal scanning cycle of the input television signal, and the number of horizontal scanning lines of the input television signal is displayed on the image display device. If the number of signal lines in the horizontal direction substantially corresponds to the number of horizontal signal lines, it is possible to prevent the operation of the vertical drive means from being stopped by supplying the control signal of the second polarity to the gate means. It is possible to cope with the display of television signals transmitted by a plurality of television systems having different horizontal scanning lines, and further, it is possible to reduce the size with a simple structure, which is economically advantageous. In particular, since the clock supplied to the vertical driving means is controlled by the gate means, even if the type or number of television systems to be displayed is changed, the vertical driving means corresponds to one type of television system. It will suffice if the items are prepared, and the simplification of the configuration can be promoted.

(Embodiment) Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. In FIG. 1, the same parts as those in FIG. 6 are designated by the same reference numerals, and only different parts will be described here. That is, each pixel 24, 24, ... Of the liquid crystal panel 23.
Is different from the conventional one in that the function of the Y driver 27 for sequentially scanning the vertical direction is changed to give control to the vertical scanning.

Here, the liquid crystal panel 23 has the number of pixels in the vertical direction corresponding to the image display of the television signal transmitted by the NTSC system, and the television signal transmitted by the PAL system and the NTSC system.
A case where a television signal transmitted by the method is displayed as an image will be described as an example.

That is, the Y driver 27 switches the switch 28 to the power supply Vcc side when the PAL system television signal is supplied,
By switching the switch 28 to the ground side when the TSC system television signal is supplied, each pixel 24, 24, ...
The vertical scanning of ... is controlled by different forms so that the image display of both types of television signals can be performed well.

FIG. 2 shows the details of the Y driver 27. Reference numeral 29 in the figure denotes an input terminal to which the clock HCK is supplied, which is a clock input terminal CK of the 5-bit shift register 30,
They are connected to the input terminal of the knot circuit 31 and the input terminal of the AND circuit 32, respectively. Further, reference numeral 33 in the figure is an input terminal to which the gate pulse GE is supplied and is connected to the gate pulse input terminal GI of the shift register 34 of 220-stage output.

Further, reference numeral 35 in the drawing denotes an input terminal to which the frame pulse FP is supplied, which is connected to an input terminal of a NAND circuit 36 and also connected to an input terminal of a NAND circuit 38 via a knot circuit 37. Reference numeral 39 in the drawing denotes an input terminal to which the clear pulse FCL is supplied, which is the shift register 30, 34 and D.
Type flip-flop circuit (hereinafter called D-FF circuit)
It is connected to each of the 40 clear inputs CL.

Here, reference numeral 41 in the drawing denotes an input terminal to which a pulse ST generated at the start of display is supplied for each vertical synchronization signal. The input terminal 41 is connected to the input terminal D of the shift register 34 and the input terminal of the OR circuit 42.
Reference numeral 43 in the drawing denotes an input terminal to which the power supply level Vcc or the ground level selected by the switch 28 is supplied,
They are connected to the input terminals of the NAND circuits 36 and 38, respectively.

Here, the third and fifth output terminals QC and QE of the shift register 30 are connected to the input terminals of the NAND circuits 36 and 38, respectively, and the output terminals of the NAND circuits 36 and 38 are connected to the AND circuit. Connected to the input of circuit 32. The output terminal of the AND circuit 32 is connected to the clock input terminal CK of the shift register 34.

Also, the fifth output terminal QE of the shift register 30 is
Is connected to the input terminal D of the D-FF circuit 40, and this D-
The output terminal Q of the FF circuit 40 is connected to the input terminal of the OR circuit 42. Further, the output terminal of the OR circuit 42 is connected to the input terminal D of the shift register 30.

Here, in the shift register 30, since the pulse ST becomes H level at the start of display, the input terminal D becomes H level. Then, the shift register 30 sets the output terminal QA to the H level in synchronization with the rising of the clock HCK. Then, at the next rising edge of the clock HCK, the pulse ST is at L level, so the output terminal QA becomes L level,
The output terminal QB becomes H level. After that, shift register 30
Keeps clock HCK until its output terminal QE goes high.
The shift operation is repeated in synchronization with.

When the output terminal QE of the shift register 30 becomes H level, the H level output is latched in the D-FF circuit 40 at the falling edge of the clock HCK. Therefore, the input terminal D of the shift register 30 becomes H level again, and the output terminal QA becomes H level.
After reaching the level, the same operation is repeated thereafter. Here, the above operation of the shift register 30 is continued until the clear pulse FCL is generated at the end of the vertical scanning.

Therefore, the H level is supplied to the number circuit 36 at the third H from the start of the display, and thereafter the H level is supplied every 5H. Therefore, now, the frame pulse FP, which is inverted every vertical scanning, is at the H level, and the switch 28 is at the power source
If it is connected to the c side (H level), the output of the NAND circuit 36 will be L every 3H, 8H, 13H, 18H, ... after the display starts.
It becomes the level, and becomes H level in the other periods.

Further, the NAND circuit 38 operates similarly. However, in this case, when the frame pulse FP is at L level and the switch 28 is connected to the power supply Vcc side (H level), the output of the NAND circuit 38 is 5H, 10H, 15H, 2 after the start of display.
0H: L level every time, and H level during other periods.

Therefore, while the outputs of the NAND circuits 36 and 38 are at the L level, the clock HCK is not supplied to the shift register 34 by the action of the AND circuit 32, and the shift operation is not performed.

Further, the frame pulse FP is inverted and input to each of the NAND circuits 36 and 38. Therefore, in the NAND circuits 36 and 38, either one of the outputs can be fixed at the H level during one vertical scanning period, and only the other output can be at the L level as described above.

Here, the frame pulse FP is set to H level during the odd field period and set to L level during the even field period. Therefore, the output of the NAND circuit 38 is fixed to the H level during the odd field period, and the output of the NAND circuit 36 is fixed to the H level during the even field period. Therefore, the output of the AND circuit 32 is 3H, 8H, 13H, 18H, and 8H after the start of display during the odd field period.
...... L level at the eye, and 5H, 10H, 15H, 20H after the start of display during the even field period.

In other words, the shift register 34 does not perform the shift operation at 3H, 8H, 13H, 18H, ... Eyes after the start of display during the odd field period, and 5th after start of display during the even field period.
H, 10H, 15H, 20H, ... No shift operation for the eyes.

The shift register 34 receives the pulse ST at the input terminal D.
It becomes an operating state by being supplied to. Then, every time the gate pulse GE is supplied, the output L0, L1, ..., L219
Any one of them is set to the H level. Further, in synchronism with the output of the AND circuit 32, for example, if the output L0 is at H level, the output that becomes H level is L0, L1, L2,
It is sequentially shifted in the order of …….

FIG. 3 is a timing chart showing the operation of the Y driver 27. The polarities of the color signals supplied to the signal lines a, b, and c are inverted every vertical scanning period. Except for overscan at the top of the screen, the pulse ST becomes H level at the start of display, and the shift register 3 is synchronized with the clock HCK.
The output terminal QA of 0 becomes H level. After that, every time the clock HCK is supplied, the output terminals QB, QC, ... Of the shift register 30.
The operation of becoming the H level is repeated in the order of.

Here, during the odd field period, since the frame pulse FP is at the H level, the output of the NAND circuit 36 is
The output terminal QC of the shift register 30 goes to the L level in synchronization with the H level. Also, during the even field period, the frame pulse FP is at the L level, so the output of the NAND circuit 38 is at the output terminal QE of the shift register 30 at the H level.
It becomes L level in synchronization with the level.

Therefore, the output of the AND circuit 32 has the clock HCK of 5
In every odd field, the outputs L1, L5, ... Of the shift register 34 are generated twice in succession.
In the even field, the output of the shift register 34 L3, L7, ...
Will be generated twice in succession.

Therefore, in the odd field, the output of the X driver 18 is continuously supplied for 2H to the pixels 24, 24, ... in the 2,6,10, ... row from the top of the liquid crystal panel 23 shown in Fig. 1. The signal supplied in the first 1H of the 2H is overwritten and erased, that is, thinned out. In the even field, the output of the X driver 18 is continuously supplied for 2H to the pixels 24, 24, ... in the 4,8,12, ... row from the top of the liquid crystal panel 23 shown in Fig. 1. The signal supplied in the first 1H of the 2H is overwritten and erased, that is, thinned out.

FIG. 4 shows a vertical scanning mode of the liquid crystal panel 23 by the Y driver 27 as described above, and the thinned horizontal scanning lines are shown by dotted lines. In this way, the odd fields Om, Om + 1, Om + 2, ...
, And the signals of even fields Em, Em + 1, Em + 2, ... are alternately thinned out every 5H, so that the number of pixels in the vertical direction can be made to correspond approximately to the number of horizontal scanning lines of the television signal of the NTSC system. Even with the liquid crystal panel 23 set to 220, 275 horizontal scanning lines can be displayed with an overscan rate of 3.5% in one field of a PAL system television signal.

Also, when the switch 28 is switched to the ground side, the outputs of the NAND circuits 36 and 38 are both fixed at the H level,
All the clocks HCK are supplied to the shift register 34, and the thinning operation described above is not performed. Therefore, it is possible to display an NTSC television signal in the same operation as the conventional one.

By the way, when the horizontal scanning lines are thinned out as described above, as shown in FIG.
It is conceivable to thin out the 5, 10, 15, 20th eye, but in this case, since two consecutive signals disappear per field, discontinuity is likely to be noticeable in image quality.

On the other hand, as shown in the above embodiment, the thinning-out horizontal scanning lines are dispersed so as not to be continuous in the odd and even fields, so that the discontinuity in the image quality becomes less noticeable. Especially for small LCD televisions,
Since the odd-numbered field and the even-numbered field are overlapped and supplied to the same horizontal pixel line, the resolution in the vertical direction is deteriorated, and the PAL thinned out in the format as in the above embodiment is used.
Almost no deterioration is recognized in the television signal of the system.

The present invention is not limited to the above-described embodiment, and can be variously modified and implemented without departing from the scope of the invention.

[Effects of the Invention] Therefore, according to the present invention as described in detail above,
A very good image which can correspond to the display of television signals transmitted by a plurality of television systems having different horizontal scanning lines in one field, has a simple configuration, is suitable for miniaturization, and is economically advantageous. A display device can be provided.

[Brief description of drawings]

FIG. 1 is a block configuration diagram showing an embodiment of an image display device according to the present invention, FIG. 2 is a block configuration diagram showing in detail the essential parts of the same embodiment, and FIG. 3 is a diagram showing the operation of the same embodiment. FIG. 4 is a timing diagram for explaining the thinning operation of the same embodiment, FIG. 5 is a diagram for explaining an undesirable example of the thinning operation of the same embodiment, and FIG. 6 is a conventional image display device. FIG. 7 is a block diagram showing the details of a pixel, FIG. 7 is a circuit diagram showing details of a pixel, FIG. 8 is a timing diagram for explaining the operation of the conventional device, and FIG. 9 is a horizontal scanning line processing means by the conventional device. FIG. 10 is a block diagram showing a conventional PAL / NTSC conversion means. 11 to 13 …… Input terminal, 14 …… Polarity reversing circuit, 15 …… Polarity switching circuit, 16 …… Timing generation circuit, 17 …… Color switching circuit, 18 …… X driver, 19 …… Shift register, 20…
... buffer, 21 ... line memory, 22 ... buffer, 23
…… Liquid crystal panel, 24 …… Pixels, 25 …… Y driver, 26
...... Shift register, 27 …… Y driver, 28 …… Switch, 29 …… Input terminal, 30 …… Shift register, 31 ……
Knot circuit, 32 ... AND circuit, 33 ... input terminal, 34 ...
... shift register, 35 ... input terminal, 36 ... NAND circuit, 37 ... knot circuit, 38 ... NAND circuit, 39 ... input terminal, 40 ... D-FF circuit, 41 ... input terminal, 42 ... … OR circuit, 43 …… input terminal, 51 …… input terminal, 52 …… NTSC signal processing circuit, 53 …… NTSC matrix circuit, 54 …… NT
SC / PAL selector switch, 55 …… Polarity selector circuit, 56 …… NTSC
LCD panel, 57 …… PAL signal processing circuit, 58 …… PAL matrix circuit, 59 to 61 …… PAL / NTSC conversion circuit.

Claims (1)

[Claims] 1. An image display device in which a pixel is installed at each intersection of a plurality of horizontal signal lines and a vertical signal line arranged in a matrix, and each vertical signal line of the image display device. A horizontal direction driving means for supplying a television signal sampled by the number of pixels in the horizontal direction in synchronization with the horizontal scanning period of the television signal, and a clock synchronized with the horizontal scanning period of the input television signal. Is given to each of the horizontal signal lines of the image display device so that the horizontal display means sequentially scans the image signals in the vertical direction in synchronization with the horizontal scanning period of the television signal. And a vertical drive means for supplying a signal for displaying a television signal supplied to each vertical signal line of the display device on each pixel. Then, based on the control signal of the first polarity, the clock synchronized with the horizontal scanning period of the input television signal is thinned out at a predetermined cycle and supplied to the vertical driving means, and the clock of the second polarity is supplied. It is characterized by further comprising gate means for switching, based on a control signal, a clock synchronized with a horizontal scanning period of the inputted television signal so as to supply the clock to the vertical driving means without thinning out. Image display device.