JP2994642B2 - Data processing device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a data processing device, for example, a data processing device having data storage means such as an external register. 2. Description of the Related Art Conventionally, a clock / calendar device that performs a count-up, a time adjustment, and a date adjustment by rewriting the contents of a register / counter of a date, hour, minute, and second by a processor such as a CPU is described in US Pat. It was configured as shown in the figure. [Problems to be Solved by the Invention] In such a device, when the CPU 1 starts malfunctioning for some reason (hereinafter, runaway), the register 3 of the clock / calendar or the register of the counter display 5 is rewritten during the runaway. Sometimes, the date and time went out of order. Usually, in order to prevent this, a watch dog timer (Watch Dog
A timer input from the WDT 4 to the INT terminal of the CPU 1 puts the CPU into an initial state and automatically recovers from a runaway state. However, WDT4 may be cleared by an instruction randomly generated while CPU1 is running out of control.
It was impossible to completely detect runaway and protect the contents of each register by T4. Such a problem is not limited to a clock register, and is a problem commonly occurring in a data processing device having data storage means of another device, for example, a RAM, a recording medium, or the like. SUMMARY OF THE INVENTION It is an object of the present invention to solve the above problems and to provide a data processing apparatus capable of reliably protecting data stored in a data storage unit even when a processor runs away. [Means for Solving the Problems] In order to solve the above-mentioned problems, the present invention makes it possible to output a data storing means for holding data and a signal for clearing data of the data storing means. A processing circuit; a first power supply unit for supplying power to the data storage unit and the processing circuit; a second power supply unit for supplying power to the data storage unit; Detecting means for detecting the voltage of the second power supply means, and selecting the higher one of the voltages detected by the detection means from the first and second power supply means, Selecting means for supplying power;
When the second power supply unit is selected by the selection unit, a prohibition unit that prohibits input of a write signal from the processing circuit to the data storage unit is provided. FIG. 1 is a block diagram showing the configuration of a first embodiment of the present invention. In FIG. 1, 1 is a CPU, 2 is an address decoder for decoding an address port output of the CPU 1, 3 is a register / counter having a clock / calendar function, and 4 is a WD.
T, 5 is a display for outputting a clock / calendar and displaying to a user, 6, 7 are Lock registers for prohibiting (Lock) access to the register 3, WDT4, respectively, 8, 9 are Lock registers 6, respectively. , 7 and the address decoder 2. Next, in order to explain the operation of the present embodiment in detail, CPU 1, address decoder 2, WDT 4, Lock register 7, AN
The configuration of the D gate 9 will be described with reference to FIG. In FIG. 2, PA, PD, and WRG are output ports of the CPU 1 and each output address data and a write pulse to an external register. The AND gates 10 and 11 are for decoding A5H (hereinafter hexadecimal numbers are suffixed with H and distinguished from decimal numbers) and 5AH from the output of the address port of the CPU 1, respectively, and are included in the address decoder 2. I have. The AND gate 12 receives the output of the latch circuit 7 'which is the lock register 7.
The C3H is decoded, and the AND gate 13 has a function of decoding 3CH from the output of the data port of the CPU 1. 14 is a WDT4 counter, which counts up by clock input and, unless cleared by access from CPU1, counts a certain number to output a signal from the CO pin,
It is configured to interrupt U1. Next, the operation will be described. In order for the CPU 1 to clear the counter 14, first write C3H to the address A5H and then write (C3H to the latch 7 ').
), Then write 3CH to address 5AH (AND gate 1
3 output high). Also, when the counter 14 is cleared, the latch 7 'is also cleared. Therefore, to clear the counter 14 once, and then to clear the counter 14, the CPU 1 writes C3H to the address A5H again, and then 3CH must be written to address 5AH. That is, the latch 7 'at address A5H has the function of locking the clear operation of the WDT counter 14, and the value C3
H can be said to be a keyword that removes Lock. The probability of clearing the WDT by the above procedure while the CPU 1 is running away is extremely low. Therefore, even if the CPU 1 goes out of control, the WDT data can hardly be cleared by the signal from the CPU. In FIG. 2, the counter 14 of the WDT has been described. However, the register 3 for the clock and the register 5 for the display are also prevented from being erroneously rewritten (updated) by the rewrite command from the CPU 1 during the runaway. Can be done. Next, as another embodiment of the present invention, FIG. 3 is a block diagram showing the configuration in the case where the lock is doubled, and FIG. 4 is a detailed circuit diagram of each unit such as the WDT unit. In this embodiment, in addition to the first embodiment, the number of lock registers 16 is increased,
7 is 69H from address and 96H from register 16 output, respectively
Is an AND gate that decodes In such a configuration, the CPU 1 clears the WDT counter 14 by performing a series of operations of 1) writing C3H to A5H, 2) writing 96H to 69H, and 3) writing 3CH to 5AH. At this time, the WDT counter 14 is not cleared even if any of the above series of operations is missing or the order is changed. AND gate 17 is locked
Since the register 7 'and the AND gate 13 clear the Lock register 16, respectively, in order for the CPU 1 to clear the WDT counter 14 again, the above series of operations must be repeated. Therefore, according to the present embodiment, the counter
The probability of completing 14 is even lower, and there is virtually no problem. Next, the configuration of a third embodiment of the present invention is shown in FIG. This embodiment is a case where the present invention is applied to a device having a block that continuously operates like a clock 3 and a block that stops when the device is not used, such as a CPU or a WDT. For example, a personal computer having a calendar function, a clock, a camera, and the like can be considered. In this embodiment, in addition to the previous embodiment, a back-up power supply for supplying electricity to the main power supply 20, which is a power supply for the CPU 1, etc., the constant clock 3, its lock register 6 ', the AND gate 8, etc.
21, a detection unit 22 for detecting supply of electricity from the main power supply 20,
A switching device 23 for switching the power supply to the clock 3 and the like functioning as a register, and a switch 2 connected to the main power supply 20
Has 5 In an embodiment having such a configuration, the switch 25
Is closed and the main power supply 20 is being supplied, the switching unit 23 is controlled by the detection unit 22 so that the power of the timepiece 3 is supplied from the main power supply 20. When the power is not supplied from the main power supply 20 because the switch 25 is opened or the main power supply 20 is exhausted, the detection unit 22 detects the power supply and clears the Lock register 6 ′ through the OR gate 24. , The write signal of the clock 3 is prohibited. At the same time, the Lock register 6 ',
The clock 3 and the like are supplied with electricity from the backup power supply 21 by the switching device 23. In this embodiment, the switching device 23 is switched by a signal from the detector 22. However, a higher voltage is selected from the main power supply 20 and the backup power supply 21 to supply power to the lock register 6 'and the timepiece 3. You may do so. According to the present embodiment, the operation of the CPU 1 to which power is supplied from the main power supply increases the possibility of runaway or the like due to a decrease in the power supply voltage of the main power supply, or the state of each terminal of the CPU 1 If the signal stabilizes without being stabilized, this is detected by the detection unit 22 and the Lock register 6 'is cleared, so that the contents of the clock 3 are not changed until a specific address is newly generated from the address decoder 2. It can be controlled not to be rewritten. As described above, according to the present embodiment, by providing the Lock register for restricting the rewriting and clearing of the register, the probability of register destruction due to runaway of the CPU or the like is reduced, and the accuracy of runaway detection by the WDT is improved. To increase the reliability of the system. In this embodiment, WDT is used as a data storage means.
However, the present invention is not limited to the WDT, but other registers, other data storage means, RAMs, recording media, and the like may be used. Further, in this embodiment, a clock device is shown, but another device may be used, or a CPU is shown as a processor, but another large computer or the like may be used. Further, in the present embodiment, the store means is not updated even if an update instruction is output from the processor until the fixed address data given from the processor is output. Until a change data, for example, a signal based on data input from outside the processor is output, even if an update instruction is output from the processor, the updating of the storage means may not be performed. [Effects of the Invention] According to the present invention, even if a processor runs away, even if an instruction for updating the contents of the data storage means is output by mistake during the runaway, the update by the erroneous instruction can be prevented. . Further, a higher voltage can be supplied to the data storing means.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a configuration of a first embodiment of the present invention, FIG. 2 is a circuit diagram relating to a WDT section in FIG. 1, and FIG. 3 is a second embodiment. FIG. 4 is a circuit diagram relating to the WDT unit of FIG. 3, FIG. 5 is a block diagram showing the configuration of the third embodiment, and FIG. 6 is a diagram showing a conventional example. 1 is a CPU 2 is an address decoder 3 is a clock / calendar 4 is a WDT 5 is a display 6,7 is a Lock register 8,9,10,11,12,13 is an AND gate 14 is a WDT counter 15,16 is a Lock register 17, 18, 19: AND gate 20: Main power supply 21: Backup power supply 22: Main power detector 23: Power supply switch 24: OR gate

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-61-228545 (JP, A) JP-A-61-125660 (JP, A) JP-A-56-79317 (JP, A) JP-A-59-1979 202526 (JP, A) JP-A-58-205999 (JP, A) JP-A-61-177523 (JP, A) Japanese Utility Model Application No. 58-43700 (JP, U) Japanese Utility Model Application No. 57-42430 (JP, U) Japanese Utility Model Application No. 59-84625 (JP, U) Japanese Utility Model Application No. 57-123525 (JP, U) (58) Fields investigated (Int. Cl. ⁶ , DB name) G06F 11/00 G06F 12/16

Claims (1)

(57) [Claims] Data storing means for holding data; a processing circuit capable of outputting a signal for clearing data in the data storing means; a first power for supplying power to the data storing means and the processing circuit Supply means; second power supply means for supplying power to the data storage means; detection means for detecting voltages of the first and second power supply means; and first and second powers Selecting means for selecting the higher one of the voltages detected by the detecting means from among the supplying means to supply power to the data storing means; and selecting the second power supplying means by the selecting means And a prohibiting means for prohibiting input of a write signal from the processing circuit to the data storing means.