JP2962329B2 - Image processing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing method,
In particular, correct uncorrectable data using other data.
Image processing method .

[0002]

2. Description of the Related Art In an image transmission system for digitizing a moving image signal and transmitting image data via a transmission line such as an optical fiber or a communication satellite or a recording medium such as a magnetic tape,
An error correction code for detecting and correcting a transmission error is used, and the transmission error is corrected on the receiving side (or the reproducing side) using the error correction code. And, for the uncorrectable error by the error correction code, it is corrected by interpolation to form an approximate value from the peripheral pixels is performed.

[0003]

In order to prevent the image quality from deteriorating in the interpolation process, it is necessary that peripheral pixels used for the interpolation have no error. In recent years, when high efficiency coding (image compression) widely used is adopted, peripheral pixels available for interpolation are limited. For example, in a DPCM (Differential Pulse Code Modulation) system that is reset every line, if an uncorrectable error occurs, the original data cannot be reproduced on the line containing the error. Therefore, only pixels included in the upper and lower lines can be used for interpolation in this case. Further, in an encoding method using an orthogonal transform such as a discrete cosine transform (DCT), when an uncorrectable error occurs, all pixels included in a transmission block (for example, 8 pixels vertically by 8 pixels horizontally) are converted to original pixels. Signals cannot be reproduced, and image quality degradation cannot be prevented by interpolation using upper and lower lines.

As described above, even if interpolation is performed within the same frame, the effect may not be expected at all depending on the encoding method.

An object of the present invention is to provide an image interpolation method capable of obtaining a more natural interpolated image regardless of the encoding method.

[0006]

An image processing method according to the present invention is an image processing method for correcting uncorrectable data in digital moving image data transmitted from a transmission side device by using other data. , those in the transmitting device
Detecting the correlation between frames of the digital video data
The corresponding inter-frame correlation information
Data along with the transmitted inter-frame correlation information.
Therefore, it is characterized in that the uncorrectable data is corrected using the image data of the selected frame.

[0007]

According to the above-mentioned means, since image data having a high correlation in the time direction is used, a natural interpolated image can be obtained regardless of the compression encoding method in a frame.

[0008]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. 10 is an input terminal for an analog image signal, and 12 is an A / D for converting the analog image signal into a digital image signal.
A converter 14 is an encoder for encoding digital image signals with high efficiency, and 16 is a detector for detecting and correcting a transmission error occurring in a recording / reproducing system such as a magnetic tape or an optical disk, or a communication transmission system such as an optical fiber or a communication satellite. An ECC adding circuit for adding an error detection and correction code (ECC). 18
Is a transmission system, specifically, a recording / reproducing system such as a magnetic tape or an optical disk, or a communication transmission system such as an optical fiber or a communication satellite.

Reference numeral 20 denotes an EC corresponding to the ECC adding circuit 16.
The C decoding circuit 22 is a decoder corresponding to the encoder 14. The ECC decoding circuit 20 outputs the error-corrected data to the decoder 22, and outputs an error-correctable signal (flag) for the data that cannot be corrected. This error-correctable signal (flag) is transmitted to the frame memories 33, 3
5, and is supplied to a switch control circuit 36 to be described later. Reference numerals 24, 26 and 28 denote serially connected frame memories, each of which is a FIFO.
(First in first out) memory. 30 is a decoder 22
Is a correlation detection circuit for detecting a correlation between the output of the frame memories 24, that is, an inter-frame correlation, and a correlation detection circuit 32 for detecting an inter-frame correlation from the outputs of the frame memories 24, 24. 34 is a frame memory 2
Switches for selecting outputs of 4, 26 and 28. The switch control circuit 36 switches the switch 34 according to the error correction impossible flag from the ECC decoding circuit 20 and the detection result of the correlation detection circuits 30 and 32. Reference numeral 38 denotes a D / A converter for converting the data selected by the switch 34 into an analog signal, and reference numeral 40 denotes an output terminal for a reproduced analog image signal.

FIG. 2 shows a circuit configuration example of the correlation detection circuits 30 and 32. 42 and 44 are input terminals for image data;
Is a subtractor for calculating the difference between the image data input from the input terminals 42 and 44. 48 is an adder, 50 is an adder 4
8 is a D flip-flop that delays the output of 8 by one sample period and feeds it back to the adder 48. The adder 48 and the D flip-flop 50 constitute an integrator. The output of the adder 48 obtained by adding the output of the subtractor 46 for one frame is output from the output terminal 52.

The operation of FIG. 1 will be described. A / D converter 12
Samples an analog image signal input to the input terminal 10 at a predetermined sampling rate, and outputs 8 bits or 16 bits.
Convert to a digital signal of bits. The encoder 14 compresses the digital image signal output from the A / D converter 12, that is, performs high-efficiency encoding by DPCM encoding or ADCT encoding. This embodiment is not limited by the high efficiency coding method itself. ECC addition circuit 16
Adds an error detection and correction code by a predetermined method.

The output of the ECC adding circuit 16 is input to an ECC decoding circuit 20 via a transmission system 18 including a recording / reproducing system and a communication transmission system. During the transmission of the transmission system 18, a transmission error occurs with a predetermined probability. The ECC decoding circuit 20 detects the presence or absence of an error, the position of the error, and whether or not the data can be corrected for the data input from the transmission path 18, corrects the correctable error, and outputs the corrected data to the decoder 22. Also,
If there is an uncorrectable error, an uncorrectable error flag is output to the switch control circuit 36.

The decoder 22 decodes (decompresses) the data compressed by the encoder 14 and outputs the original image data to the frame memory 24 and the correlation detection circuit 30. Since the frame memories 24, 26, and 28 perform a FIFO operation and are cascaded, the frame memories 24, 26, and 28 store data of three consecutive frame images. The correlation detection circuit 30 detects the correlation between the current frame (the output of the decoder 22) and the immediately preceding frame (the output of the frame memory 24), and the correlation detection circuit 32 detects the correlation between the current frame (the output of the decoder 22). output)
, The correlation between the immediately preceding frame (output of the frame memory 24) and the immediately preceding frame (output of the frame memory 26) is detected. Correlation detection circuits 30, 32
Stores the difference between the input image signals of two frames for one frame, and calculates the correlation amount.

The switch 34 is connected to the frame memory 24,
26 and 28 outputs can be selected.
The output of the memory 26 is selected. Switch control circuit 3
Reference numeral 6 indicates the screen position of the uncorrectable error from the error-correctable flag from the ECC decoding circuit 20,
From the outputs 0 and 32, it is possible to know which of the previous screen and the rear screen has a higher correlation with the output image of the frame memory 26. That is, the switch control circuit 36
Switches the switch 34 in accordance with the error correction impossible flag from the ECC decoding circuit 20 so as to select the image data at the same position on the screen with higher correlation.

A D / A converter 38 converts the image data output from the switch 34 into an analog signal, and
An analog image signal reproduced from 0 is output.

FIG. 3 is a block diagram showing the configuration of another embodiment of the present invention. The present embodiment employs AD
The CT method is used.

Reference numeral 110 denotes an input terminal for an analog image signal,
Reference numeral 12 denotes an A / D converter, 114 denotes an ADCC encoder, and a DCT block, for example, a DCT block in 8 × 8 pixels.
The DC component is separated into a DC component and an AC component by T-transform, DPCM coding is performed on the DC component between the DC component and the previous DCT block, and run-length processing and Huffman coding are performed on the AC component. An ECC adding circuit 116 adds an error detection and correction code to the coded output of the AC and DC components from the ADCT encoder 114.

Reference numeral 118 denotes a transmission system, 120 denotes an ECC decoding circuit corresponding to the ECC adding circuit 116, and 122 denotes an ADCT decoder corresponding to the ADCT encoder 14. 12
Reference numerals 4, 126, 128 denote serially connected frame memories, each of which is a FIFO (first in first out) memory. Reference numerals 129 and 130 denote FIFO type frame memories which delay the DC component output from the ADCT decoder 122 by one frame, and are cascaded for correlation detection. 131 is the output of the decoder 122 and the frame
A correlation detection circuit 132 for detecting an inter-frame correlation with the output of the memory 129;
This is a correlation detection circuit that detects an inter-frame correlation from the output of 0. Reference numeral 134 denotes a switch for selecting an output from the frame memories 24, 26, and 28. Switch control circuit 136
Switches the switch 134 according to the error correction impossible flag from the ECC decoding circuit 120 and the detection result of the correlation detection circuits 131 and 132. 138, a D / A converter for converting the data selected by the switch 34 into an analog signal;
Reference numeral 40 denotes an output terminal for a reproduced analog image signal.

The characteristic operation of FIG. 3 will be described. The A / D converter 112 converts an analog image signal input to the input terminal 110 into a digital signal, and converts the analog image signal into a digital signal.
Performs DCT conversion on the digital image signal output from the A / D converter 112 in the DCT block, performs DPCM encoding on the DC component with the previous DCT block, and performs run-length processing and Huffman encoding on the AC component. The ECC adding circuit 116 adds an error detection and correction code to the AC component output and the DC component output of the ADCT encoder 114 by a predetermined method.

The output of the ECC addition circuit 116 is
18 to the ECC decoding circuit 120. ECC
The decoding circuit 120 receives AC and DC input from the transmission line 118.
For the component data, the presence / absence of an error, the position of the error, and whether or not the error can be corrected are detected, and the correctable error is corrected and output to the ADCT decoder 122. If there is an uncorrectable error, an error uncorrectable flag is output. This error correction impossible flag is stored in the frame memory 13.
3, 135, and is supplied to the switch control circuit 136 after being delayed by two frames.

The ADCT decoder 122 converts the DC component into the DP
CM decoding, Huffman decoding and run-length decoding of the AC component, and inverse DCT transform to restore the original image data. The image data restored by the ADCT decoder 122 is applied to the frame memory 124, and the inverse DC
The DC component before T conversion is a DC component frame memory 12
9 and the correlation detection circuit 131. The frame memories 124, 126, and 128 are, like the frame memories 24, 26, and 28 in FIG.
One frame image data is stored. Since the frame memories 129 and 130 are also cascaded, the DC components of adjacent frames are stored for one frame. The correlation detection circuit 131 detects the correlation between the current frame (the output of the decoder 122) and the immediately preceding frame (the output of the frame memory 129) based on the DC component. , The correlation between the immediately preceding frame (output of the frame memory 129) and the immediately preceding frame (output of the frame memory 130) is detected. The correlation detection circuits 131 and 132 may have the same circuit configuration as in FIG. 2, and store the difference between the DC components of the input two-frame images for one frame. Thereby, an inter-frame correlation amount is obtained.

The switch 134 is connected to the frame memory 12
Outputs of 4, 126 and 128 can be selected, and the output of the frame memory 26 is normally selected. The switch control circuit 136 is similar to the switch control circuit 36 of FIG.
The switch 134 is controlled. That is, the switch 134
For data for which error correction is not possible, image data at the same position on the screen with higher correlation is selected. D / A converter 1
Reference numeral 38 converts the image data output from the switch 134 into an analog signal, and the reproduced analog image signal is output from an output terminal 140.

In the embodiment shown in FIG. 3, since accurate correlation detection can be performed by using a DC component for correlation detection, image correction by more natural interpolation can be performed.

In the above embodiment, the decoder side (reception side)
Although the correlation detection circuit is disposed in the encoder, a correlation detection circuit may be disposed on the encoder side (transmission side) to transmit the correlation information between frames for each frame. In this way, the equipment burden on the receiving side is greatly reduced. This is suitable for a transmission system such as a television broadcast, which has a large number of recipients and requires a small and low-cost receiving device.

[0026]

As can be easily understood from the above description, according to the present invention, a plurality of frames can be obtained from inter- frame correlation information .
Since the error-correctable data is corrected using the optimum frame in the frame , more natural correction can be performed, and a reproduced image (received image) with less unnaturalness can be provided.

[Brief description of the drawings]

FIG. 1 is a configuration block diagram of an embodiment of the present invention.

FIG. 2 is a circuit configuration example of correlation detection circuits 30 and 32;

FIG. 3 is a configuration block diagram of another embodiment of the present invention.

[Explanation of symbols]

10: Analog image signal input terminal 12: A / D converter 14: Encoder 16: ECC addition circuit 18: Transmission system 20: ECC decoding circuit 22: Decoder 24, 2
6, 28, 33, 35: Frame memory 30, 3
2: Correlation detection circuit 34: Switch 36: Switch control circuit 38: D / A converter 40: Output terminals 42, 4
4: Input terminal 44: Subtractor 48: Adder 50: D
Flip-flop 52: Output terminal 110: Image signal input terminal 112: A / D converter 114: ADCT encoder 116: ECC addition circuit 118: Transmission system 1
20: ECC decoding circuit 122: ADCT decoder 1
24, 126, 128, 129, 130, 133, 13
5: Frame memory 131, 132: Correlation detection circuit 134: Switch 136: Switch control circuit 13
8: D / A converter 140: output terminal

Claims (1)

(57) [Claims] (1)From the sending deviceDigital motion transmitted
Uncorrectable data in image data is used for other data
Image processing method to correctIn the transmitting device, the digital moving image data
Detects the correlation between frames and generates the inter-frame correlation information.
Transmitted with the digital video data, According to the transmitted inter-frame correlation information chosen
Correct the uncorrectable data using the image data of the frame.
An image processing method characterized by correcting.