JPH05308524A - Image processor - Google Patents

Abstract

PURPOSE:To prevent picture quality from being degraded at the time of error generation with simple hardware configuration by providing an error detecting means specific to run length decoding. CONSTITUTION:Data are inputted to an input terminal and decoded to run length codes by an entropy decoder 733. At a run length decoder 751, run length decoding is performed, the codes are outputted to an inverse zig-zag scanner 737, and the number of conversion coefficients is outputted to a counter 753. At the counter 753, the number of conversion coefficients is counted for each prescribed period. A comparator 757 compares a value inputted from a processing unit setter 755 with the counter 753 and when they are not coincident, the comparator judges the existence of error and outputs the judged result to a delayer 759. On the other hand, an inverse conversion encoder 741 outputs inversely converted picture elements to a terminal (a) and a frame memory 761. Corresponding to the judged result from the delayer 759, a switch 763 selects the terminal (a) when there is no error or selects a terminal (b) when there is any error.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus, and more particularly to an image processing apparatus having an image decoding means having a function of expanding compressed image data.

[0002]

2. Description of the Related Art Conventionally, there has been known a technique of frequency-converting image data block by block, compressing the data, and transmitting the data. Particularly, by separating the frequency component, the high frequency component, and the low frequency component and encoding each separately, the image compression efficiency is improved.

[0003]

However, in the above-mentioned conventional example, when an error occurs during the transmission of encoded data, an image signal including erroneous pixel data is reproduced, which causes a large deterioration in image quality. There was a drawback. Furthermore, when a variable code is used for encoding the above-mentioned high-frequency component, even the number of data is not accurately reproduced, and there is a case where a very large deterioration in image quality occurs such as loss of image data.

Further, conventionally, since there is a large amount of information when digitally transmitting an image, various encoding methods for reducing the amount of information and transmitting it have been proposed.

Among them, a method is known in which, after orthogonal transformation, the transformed coefficients are quantized and variable length coding is carried out for transmission.

However, in the above-mentioned conventional example, when an error occurs in the transmission line, it cannot be corrected because there is no error detecting means, and the image quality is greatly deteriorated.

In particular, when the transmitted encoded data is decoded, for example, when the dynamic range that can be decoded and reproduced is exceeded, the image quality is deteriorated.

Further, in an image transmission system in which a moving image signal is digitized and image data is transmitted through a transmission line such as an optical fiber or a communication satellite or a recording medium such as a magnetic tape, an error correction code for detecting and correcting a transmission error. Is used,
The receiving side (or the reproducing side) corrects the transmission error using the error correction code. Then, for an error that cannot be corrected by the error correction code, an interpolation process for forming an approximate value from the peripheral pixels is performed.

In order to prevent deterioration of image quality in the interpolation process,
Peripheral pixels used for interpolation must be error-free. Highly efficient coding (image quality compression) widely used in recent years
When the is adopted, peripheral pixels available for interpolation are limited. For example, DPCM reset every line
In the (differential pulse code modulation) method, when an uncorrectable error occurs, the original data cannot be reproduced on the line including the error. Therefore, only pixels included in the upper and lower lines can be used for interpolation in this case. In addition, in an encoding method using an orthogonal transform such as the discrete cosine transform (DCT), when an uncorrectable error occurs, all pixels included in a transmission block (for example, vertical 8 pixels × horizontal 8 pixels) have the same original value. The signal cannot be reproduced, and deterioration of image quality cannot be prevented even by interpolation using upper and lower lines.

As described above, even if the interpolation is performed within the same frame, the effect may not be expected at all depending on the encoding method.

In addition, various encoding methods have been proposed in order to reduce the amount of transmission data when digitally transmitting information such as images and sounds. A run-length coding method is known in which the number of consecutive 0s in one of them is paired with a value other than 0 and is coded. On the other hand, predictive differential encoding (hereinafter referred to as DPC) that compresses information by utilizing the correlation between adjacent sample values.
Abbreviated as M. )It has been known. There is also an encoding method that uses the above two methods together. FIG. 14 is a block diagram showing an encoding method that uses the above two methods together. Input terminal 1
The 8-bit image data input from 1 is output to the DPCM encoder 13 and 4-bit DPCM encoded. The DPCM encoder 13 assigns a 4-bit DPCM code to the difference values shown in Table 1.

Generally, in an image, there is a correlation between sample values which are close to each other, and many difference signals are generated by 0, and the DPCM code is also 0.
Often occurs. The 4-bit encoded DPCM code is output to the run-length encoder 15. In the run-length encoder 15, as shown in FIG.
The non-zero DPCM code and the number of consecutive zeros before this DPCM code (hereinafter referred to as 0 run length) are paired with the DPCM code of 1.

In this case, if the 0 run length is limited to 16 at maximum, the run length code can be represented by 8 bits. The 8-bit run-length code encoded by the run-length encoder 15 is output to the output terminal after the transmission format section 17 adds a reset sync as shown in FIG. For example, the reset sync is added after processing one line.

FIG. 13 is a block diagram showing the structure of a decoding device for the encoding unit shown in FIG. The run length code transmitted through the transmission line and the reset sync are input to the input terminal 21, and the run length decoder 23 inserts 0's for each run length 0 before the DPCM code until the reset sync comes. Then, it is decoded into a DPCM code. D
The data decoded into the PCM code is the DPCM decoder 2
5 and is decoded into 8-bit image data, and then output to the output terminal 27.

[0015]

[Table 1]

However, in the above-mentioned conventional example, when an error occurs in the transmission line, the error cannot be corrected because there is no error detecting means, and the image quality is greatly deteriorated.

Further, various encoding methods have been proposed in order to reduce the amount of transmission data when digitally transmitting information such as images and sounds. A run-length coding method is known in which the number of consecutive 0s and a value that is not 0 are paired and coded. On the other hand, transform coding is known in which pixels to be transmitted are orthogonally transformed and the transformed data are quantized. There is also an encoding method that uses the above two methods together.

However, in the above-mentioned conventional example, when an error occurs in the transmission line, the error cannot be corrected because there is no error detecting means, and the image quality is greatly deteriorated.

The present invention has been made in view of the above-mentioned prior art, and an object of the present invention is to provide an image processing apparatus capable of favorably controlling the amount of compressed data.

[0020]

In order to solve the above-mentioned problems, the image processing apparatus of the present invention comprises means for decoding data which has been run-length encoded after orthogonal transform, and means for executing the run by the decoding means. And a determination unit that determines whether or not the number of length-decoded data matches a predetermined number.

[0021]

(First Embodiment) A video decoding apparatus according to the present invention described below includes means for detecting and correcting an error occurring during transmission or reproduction from a recording medium, and an error generated by the detection and correction means. It is characterized by comprising means for replacing the decoded data in the block with a predetermined set value based on the information, detecting an error that has occurred on the transmission line, and performing a correction process, If there is no error in the DC component and an uncorrectable error remains in the AC component, all the data in the block is replaced with the value of the DC component by using the information, and each pixel of the block is replaced. You can replace the value with a value closer to the true value.

FIG. 1 shows a block diagram of a configuration of an image decoding apparatus according to an embodiment of the present invention and an image encoding apparatus corresponding to the image decoding apparatus.

Reference numeral 401 is an encoding device, and 402 is a decoding device, both of which are connected via a transmission line 403. Here, the transmission line 403 is a transmission medium such as optical fiber, sanitation, terrestrial radio wave such as microwave, optical space, etc. for immediate transmission.
In the case of storage transmission, it is a tape-shaped medium such as a digital VTR or DAT, a disk-shaped medium such as a floppy disk or an optical disk, and a storage medium such as a solid medium such as a semiconductor memory.

First, a video signal input from an image reader including a CCD sensor, a television camera, a video recorder, a host computer, etc., is encoded by an encoding device 40.
The data is input to one input terminal 404, and is divided into blocks composed of a plurality of data in the block forming circuit 406, such as a block composed of 8 × 8 pixels. The block data is converted into the orthogonal transformation circuit 4
At 07, for example, DCT (discrete cosine transform) or the like is performed to convert each block into a frequency component. The converted data has a low frequency component and a high frequency component, for example, DC.
The output is divided into a component (DC component) and the other AC component (AC component), which are separately encoded by the encoding circuits 408 and 409 in order to compress the amount of information. Here, as an example of encoding, DC component is PCM encoded, AC component is
There is a method such as run length Huffman coding of the component. The encoded data output from the encoding circuits 408 and 409 are subjected to error detection and correction encoding in the ECC encoding circuits 410 and 411 as a countermeasure against errors during transmission, and then combined in time series in the combining circuit 412. Further, the synchronization adding circuit 413 adds a synchronization signal for transmission or recording for each of a plurality of blocks, and sends out to the transmission path 403.

On the other hand, in the image decoding apparatus 402, the sync signal is detected from the received transmission data by the sync detection circuit 101, and the following signal processing is performed with the detected sync signal as a reference.

First, the transmission data is separated by the separation circuit 102 into coded data corresponding to the DC component and coded data corresponding to the AC component. At this time, it is assumed that the format of the coded data is such that the DC component and the AC component can be reliably separated in one synchronization block as shown in FIG.

Each separated data is input to the ECC decoding circuits 103 and 104, and an error during transmission is detected and corrected. Then, the ECC decoding circuits 103 and 104 send the corrected data to the decoding circuits 105 and 106, and at the same time, the error information is converted into DC data according to the correction results.
It is sent to the replacement circuit 108.

The coded data corresponding to the DC component and the AC component after the correction process are input to the decoding circuits 105 and 106, respectively, and are subjected to the decoding process to be restored to the information of the DC component and the AC component. If an error remains in the encoded data, it goes without saying that the correct information cannot be restored.

When variable length coding is used as the AC component coding method, for example, the decoded value of the AC component may not be a true value, and may not be restored to the number of data. ..

The decoded data output by the restoration circuits 105 and 106 are restored by the orthogonal inverse transformation circuit 107 from the value indicating the frequency component to the data indicating the pixel value in the block. However, as mentioned above, E
When the error correction is not completed in the CC decoding circuits 103 and 104, the input value itself of the orthogonal inverse transform circuit 107 is not correct information, and therefore the output value of the orthogonal inverse transform circuit 107 is correct pixel data. Will be completely different data.

Therefore, in the DC replacement circuit 108, E
The error information generated by the CC decoding circuit 103 indicates that there is no error in the DC component of the block, and the error information generated by the ECC decoding circuit 104 indicates an uncorrectable error in the AC component of the block. If it is indicated that all the pixel values in the block are replaced with the values represented by the DC component.

By this operation, even when there is an error that cannot be corrected as described above, the pixel value in the block is the average value. The value can be the value of the DC component, and although it is not the true value, it can be restored to a value relatively close to the true value.

Then, the data is converted into the time base conversion circuit 10.
9, the video signals input to the encoding device are rearranged on the same time axis and output from the output terminal 110. The output terminal 110 is connected to a monitor or printer for image formation.

With the above-mentioned device, even when an uncorrectable error occurs on the transmission path, the image quality deterioration can be minimized.

(Second Embodiment) FIGS. 3 and 4 show a second embodiment of the present invention.

FIG. 3 shows the DC replacement circuit 108 shown in FIG.
The function corresponding to is realized by the 0 substitution circuit 308. The other circuit blocks are the same as those in FIG.

The 0-replacement circuit 308 is used in the ECC decoding circuit 10.
When the error information output from Nos. 3 and 104 indicates that there is no error in the DC component of the block and that there is an uncorrectable error in the AC component, as in the above-described embodiment. , All values of the AC component are set to 0. By this operation, the input data of the orthogonal inverse transform circuit 107 is
The AC component becomes 0, so that the output of the orthogonal inverse transform circuit 107 has all the values in the block as the value of the DC component, and has the same effect as that of the above-described embodiment.

(Third Embodiment) FIG. 4 is an example showing that the present invention can be applied even when the error detection and correction code construction method is different. The ECC decoding circuit 104 in FIG. The position of the ECC encoding circuit 411 in the encoding device of FIG. 1 is located in the front stage of the separation circuit 102 and the rear stage of the combining circuit 412, and the former is the ECC decoding circuit 3
04 and the latter is an ECC encoding circuit 311 and shows a case where the error detection and correction code is encoded with respect to the data after combining the DC component and the AC component.

In this case as well, the error information output from the ECC decoding circuit 304 indicates whether or not an error exists, and E
If the error information output from the CC decoding circuit 103 indicates that there is no error, the replacement with the DC component is effective.
The present invention can be implemented by the DC replacement circuit 108 similar to that shown in FIG.

As described above, according to the embodiment of the present invention, means for detecting / correcting an error occurring during transmission or reproduction from a recording medium and error information generated by the detecting / correcting means are provided. Originally, by using a means of replacing all the decoded data in the block with the value of the DC component or a means equivalent thereto, it is possible to minimize the image quality deterioration even when an uncorrectable error occurs. It is possible to realize a decoding device that can do so and also has a small amount of hardware to be added.

In particular, in the above embodiment, since the frequency transform coefficient by orthogonal transform is divided into the DC component and the AC component and encoded, the DC component can be used for the error correction when the AC component cannot be error-corrected.

As described above, according to the embodiments of the present invention, it is possible to reduce the deterioration of the image quality in the image decoding apparatus.

(Fourth Embodiment) An image processing apparatus according to a fourth embodiment of the present invention described below is provided with a means for generating error detection information when the dynamic range of a predetermined conversion coefficient is exceeded, and is erroneously decoded. The above-mentioned problems are solved by providing means for correcting the obtained data.

FIG. 6 is a block diagram showing an embodiment of the present invention.

In FIG. 6, the image data input to the input terminal 41 is discrete cosine transform (hereinafter abbreviated as DCT).
Output to the converter 43, and a two-dimensional D is obtained for each block of 8 × 8 pixels.
CT is given. For example, in this case, it is assumed that a 12-bit conversion coefficient is obtained for 8-bit image data.

After that, the two-dimensional DCT is performed and the transform coefficient is linearly quantized by the quantizer 45. The quantization step size differs for each transform coefficient, and the quantization step size for each transform coefficient is as shown in Table 2, for example, and each quantization coefficient generated from the 8 × 8 quantization matrix unit 49 is multiplied by 2 ^S. Value. Here, S is called a scaling factor and is output to the multiplier 47 and the multiplexer 61. The multiplier 47 multiplies the output of the quantization matrix unit 49 by 2 ^S and outputs the quantized coefficient obtained as a result of the multiplication to the quantizer 45. In this way, the image quality and the amount of generated data are controlled by S. That is, as the scaling factor S is larger, the data amount is reduced but the image quality is deteriorated. When the scaling factor S is smaller, the data amount is increased and the image quality is improved.

[0047]

[Table 2]

The orthogonal transform coefficient quantized by the quantizer 45 is predicted by the one-dimensional predictor 53 for the DC component, and the prediction error is Huffman coded by the Huffman coder 55 and output to the multiplexer 61. In this Huffman encoder 55, the output of the prediction error is divided into 16 groups as shown in Table 3, the identification number SSSS of the group to which the prediction error belongs is Huffman-encoded, and then any value in the group is shown. Represented by isometric codes. In the case of Table 3, the code length of the equal-length code is equal to the value of the group identification number SSSS.

For the AC components other than the DC component, the output of the quantizer 45 is output to the zigzag scanner 57. The zigzag scanner 57 performs zigzag scanning from low frequency components to high frequency components as shown in FIG. After that, it outputs to the Huffman encoder 59.

[0050]

[Table 3]

In the Huffman encoder 59, the transform coefficient whose quantization result is not 0 (hereinafter referred to as a significant coefficient) is classified into 15 groups as shown in Table 4 based on the value, and the group identification number is SSSS. .. Further, the number of transform coefficients (hereinafter referred to as insignificant coefficients) having a quantization result of 0 sandwiched between the immediately preceding significant coefficients is defined as a run length NNNN, where the group identification number SSSS and the run length are shown as shown in Table 5. Huffman coding is performed in combination with NNNN. Then, in Table 4, which value in the group is represented by an isometric code.

In the case of Table 4, the code length of the equal-length code is equal to the value of the group identification number SSSS, and when the value of the run length NNNN is 16 or more, R16 of Table 5 is used.
Is dealt with by repeating the operation of subtracting 15 from the run length NNNN until the remaining number becomes 15 or less. Further, if the coding of all the significant coefficients in the block is completed, finally the EOB (End of
Block)

[0053]

[Table 4]

[0054]

[Table 5] Send the code.

The multiplexer 61 multiplexes the Huffman coded DC component and the Huffman coded AC component, adds a scaling factor S to the output terminal 6
Output to 3.

FIG. 5 is a block diagram of a decoding device corresponding to the encoding device of FIG.

The transmitted data is input to the XO terminal 11 and output to the divider 13. In the divider 13, the scaling factor S is output to the multiplier 29, the DC component data is output to the Huffman decoder 15, and the AC component data is output to the Huffman decoder 19. Huffman decoder 15
Then, after the Huffman code string is decoded into a difference value, it is output to the difference decoder 17. The difference decoder 17 restores the difference value to the conversion coefficient of the DC component and outputs it to the terminal C of the switch 23.

On the other hand, the AC component Huffman code data is restored by the Huffman decoder 19 into AC component conversion coefficients. After that, the conversion coefficient is restored from the zigzag scan sequence by the scan restorer 21 to the data sequence as shown in FIG.
Output to the switch 23 terminal b. The switch 23 multiplexes the conversion coefficients of the DC component and the AC component as shown in FIG.

On the other hand, in the multiplier 29, the quantization matrix 2
The matrix of 7 is multiplied by 2 ^−S and output to the inverse quantizer 25. The 8 × 8 transform coefficient is inversely quantized by the inverse quantizer 25, output to the inverse discrete cosine transformer 31, and restored to 8-bit image data.

The transform coefficient inversely quantized by the inverse quantizer 25 is output to the inverse discrete cosine transformer 31 and the determiner 37. Inverse Discrete Cosine Transform 3
The image data restored in 1 is output to the terminal a of the switch 39 and also to the frame memory 35. Since the frame memory 35 uses it as correction data when an error is detected, it delays the image data by one frame and then outputs it to the terminal b of the switch 39.

The judging device 37 compares the conversion coefficient with a predetermined dynamic range and outputs the judgment result to the switch 39.

For example, the dynamic range of the conversion coefficient is 1
If it is 2 bits, if it exceeds 12 bits, it is determined that an error has occurred in the transmission path. In the switch 39, when it is determined that there is an error based on the result of the determiner 37, the switch 39 is connected to the side b and the image data at the same place one frame before is replaced. If it is not judged to be an error, the switch 39 is connected to the a side. The image data whose error is corrected by the switch 39 is output to the output terminal 33.

In the above embodiment, the pixel group of one frame before is corrected, but it is needless to say that the pixel group in the vicinity of high correlation may be corrected. In that case, the frame memory 35 for storing the image of the previous frame is unnecessary, and the circuit configuration can be simplified.

Although the above determination is performed using the frequency component before being converted into the real space, the image data after being restored to the real space by the inverse DCT may be used.

The determination is performed for each pixel, and if at least one component is in error in the block, the entire block is replaced with the image data of the previous frame. However, a plurality of blocks or one entire screen may be replaced.

The orthogonal transform is not limited to the DCT, but Hadamard transform or the like may be used.

Further, instead of Huffman coding, other multi-valued data coding, arithmetic coding or the like may be used.

As described above, in the above-described embodiment of the present invention, it is possible to easily prevent the deterioration of image quality when an error occurs by providing the error detecting means peculiar to the decoding and the means for correcting the error. effective.

As described above, according to the present invention, it is possible to prevent the image quality from deteriorating when an error occurs and reproduce a good image quality.

(Fifth Embodiment) FIG. 9 is a block diagram showing the configuration of the fifth embodiment of the present invention. Reference numeral 210 is an analog image signal input terminal, 212 is an A / D converter for converting the analog image signal into a digital image signal, 214 is an encoder for highly efficient encoding of the digital image signal, and 216 is recording / reproducing of a magnetic tape or an optical disk. E, which adds error detection and correction code (ECC) for detecting and correcting transmission errors that occur in communication systems such as communication systems, optical fibers, communication satellites, etc.
This is a CC addition circuit. A transmission system 218 is specifically a recording / reproducing system such as a magnetic tape or an optical disk, or a communication transmission system such as an optical fiber or a communication satellite.

Reference numeral 220 is an ECC decoding circuit corresponding to the ECC adding circuit 216, and 222 is a decoder corresponding to the encoder 214. The ECC decoding circuit 220 outputs the error-corrected data to the decoder 222 and outputs an error-correction impossible signal (flag) for the error-correctable data. This error uncorrectable signal (flag) is
Delayed by 2 frames by the memories 233 and 235,
It is supplied to the switch control circuit 236 described later. 22
Reference numerals 4, 226, and 228 denote serially connected frame memories, each of which includes a FIFO (first in, first out) memory. 230 is the output of the decoder 222 and the frame
A correlation detection circuit 232 for detecting a correlation with the output of the memory 224, that is, a correlation between frames is a frame memory 2
It is a correlation detection circuit that detects the inter-frame correlation from the outputs of 24 and 226. 234 is a frame memory 224, 2
26 and 228 are switches for selecting outputs. The switch control circuit 236 switches the switch 234 according to the error uncorrectable flag from the ECC decoding circuit 220 and the detection result of the correlation detection circuits 230 and 232. 238 is a D / A converter for converting the data selected by the switch 234 into an analog signal, and 240 is an output terminal for the reproduced analog image signal.

FIG. 10 shows a circuit configuration example of the correlation detection circuits 230 and 232. Reference numerals 242 and 244 are image data input terminals, and 244 is a subtracter for calculating a difference between the image data input from the input terminals 242 and 244. Reference numeral 248 is an adder, and 250 is a D flip-flop that delays the output of the adder 248 for one sample period and returns it to the adder 248. The adder 248 and the D flip-flop 250 constitute an integrator. The output of the adder 248, which is obtained by adding the output of the subtractor 246 for one frame, is output from the output terminal 252.

The operation of FIG. 9 will be described. A / D converter 21
Reference numeral 2 samples an analog image signal input to the input terminal 210 at a predetermined sampling rate and converts it into a digital signal of 8 bits or 16 bits. Encoder 2
Reference numeral 14 compresses the digital image signal output from the A / D converter 212, that is, performs high efficiency coding by DPCM coding or ADCT coding. The present embodiment is not limited by the high efficiency encoding method itself. The ECC adding circuit 216 adds an error detection / correction code by a predetermined method.

The output of the ECC adding circuit 216 is passed through the transmission system 218, which is a recording / reproducing system or a communication transmission system, to the ECC.
Input to the decoding circuit 220. During the transmission of the transmission system 218, a transmission error occurs with a predetermined probability. The ECC decoding circuit 220, regarding the data input from the transmission line 218,
The presence / absence of an error, the position of the error, and whether or not the error can be corrected are detected, and the correctable error is corrected and output to the decoder 222. If there is an uncorrectable error, the error correction impossible flag is output to the switch control circuit 236.

The decoder 222 decodes (decompresses) the data compressed by the encoder 214 and outputs the original image data to the frame memory 224 and the correlation detection circuit 230. Frame memories 224, 226, 228 are FI
Since the FO operation is performed and the cascade connection is made, the frame memories 224, 226 and 228 store data of three consecutive frame images. The correlation detection circuit 230 detects the correlation between the current frame (output of the decoder 222) and the previous frame (output of the frame memory 224), and the correlation detection circuit 232 detects
The correlation between the frame immediately before (output of the decoder 222) and the frame immediately before (output of the frame memory 224) and the frame immediately before (output of the frame memory 226) is detected. The correlation detection circuits 230 and 232 input 2
The difference between the image signals of the frames is stored for one frame, and the correlation amount is obtained.

The switch 234 is used for the frame memory 22.
The outputs of 4, 226 and 228 are selectable, and normally the output of the frame memory 226 is selected. The switch control circuit 236 knows the screen position of the uncorrectable error from the error uncorrectable flag from the ECC decoding circuit 220, and outputs the previous screen to the output image of the frame memory 226 from the outputs of the correlation detection circuits 230 and 232. It is possible to know which of the two and the rear screen has a higher correlation. That is, the switch control circuit 236 controls the ECC decoding circuit 220.
The switch 234 is switched so as to select the image data at the same position on the screen having a higher correlation in accordance with the error uncorrectable flag from.

The D / A converter 238 converts the image data output from the switch 234 into an analog signal, and the reproduced analog image signal is output from the output terminal 240.

(Sixth Embodiment) FIG. 11 is a block diagram showing the configuration of the sixth embodiment of the present invention. In this embodiment, the ADCT method is adopted as the high efficiency coding method.

Reference numeral 1110 denotes an input terminal for an analog image signal,
Reference numeral 1112 is an A / D converter, and 1114 is an ADCT encoder, which separates a DC component and an AC component by DCT conversion in a DCT block, for example, 8 × 8 pixels,
DPCM coding is performed on the component with the preceding DCT block, and run length processing and Huffman coding are performed on the AC component. 1116 is an ADCT encoder 1114
It is an ECC adding circuit for adding an error detection correction code to the encoded output of the AC component and the DC component from the.

1118 is a transmission system, 1120 is an ECC decoding circuit corresponding to the ECC adding circuit 1116, and 1122 is A.
It is an ADCT decoder corresponding to the DCT encoder 1114. Reference numerals 1124, 1126, and 1128 denote serially connected frame memories, each of which is a FIFO (first-in first-out) memory. 1129 and 1130 are A
It is a FIFO type frame memory that delays the DC component output from the DCT decoder 1122 by one frame, and is cascaded for correlation detection. Reference numeral 1131 denotes a correlation detection circuit for detecting an interframe correlation between the output of the decoder 1122 and the output of the frame memory 1129, 113
Reference numeral 2 is a correlation detection circuit that detects interframe correlation from the outputs of the frame memories 1129 and 1130. 1134
Is a switch for selecting the output of the frame memories 224, 226, 228. Switch control circuit 1136 is E
The switch 1134 is switched according to the error correction impossible flag from the CC decoding circuit 1120 and the detection result of the correlation detection circuits 1131 and 1132. 1138 is a switch 234
A D / A converter 1140 for converting the data selected by to an analog signal is an output terminal for the reproduced analog image signal.

The characteristic operation of FIG. 11 will be described. The A / D converter 1112 converts the analog image signal input to the input terminal 1110 into a digital signal, and the ADCT encoder 1114 performs DCT conversion of the digital image signal output from the A / D converter 1112 within the DCT block,
Component is DPCM encoded with previous DCT block,
Run length processing and Huffman coding of the AC component.
The ECC adding circuit 1116 is an ADCT encoder 1114.
The error detection and correction code is added to the AC component output and the DC component output of (1) by a predetermined method.

The output of the ECC adding circuit 1116 is input to the ECC decoding circuit 1120 via the transmission system 1118.
The ECC decoding circuit 1120 detects the presence or absence of an error, the position of the error, and the correctability of the AC and DC component data input from the transmission line 1118, corrects the correctable error, and outputs the corrected error to the ADCT decoder 1122. If there is an uncorrectable error, the error uncorrectable flag is output. The error correction impossible flag is delayed by two frames by the frame memories 1133 and 1135 and supplied to the switch control circuit 1136.

The ADCT decoder 1122 outputs the DC component as D
The original image data is restored by performing PCM decoding, Huffman decoding and run-length decoding of the AC component, and inverse DCT conversion. The image data restored by the ADCT decoder 1122 is applied to the frame memory 1124, and the DC component before the inverse DCT conversion is applied to the DC component frame memory 1129 and the correlation detection circuit 1131. The frame memories 1124, 1126, 1128 respectively store the data of three consecutive frame images, like the frame memories 224, 226, 228 of FIG. Further, since the frame memories 1129 and 1130 are also connected in cascade, the DC components of adjacent frames are stored for one frame. The correlation detection circuit 1131 is DC
Depending on the component, the current frame (output of the decoder 1122) and the previous frame (frame memory 1129)
Correlation output between the output) and the correlation detection circuit 1132
Detects the correlation between the frame immediately before the present (the output of the frame memory 1129) and the frame immediately before the present (the output of the frame memory 1130). The correlation detection circuits 1131 and 1132 may have the same circuit configuration as in FIG. 10, and store the difference of the DC component of the input two-frame image for one frame. Thereby, the inter-frame correlation amount is obtained.

The switch 1134 is used for the frame memory 1
The output of 124, 1126, 1128 can be selected,
Normally, the output of the frame memory 226 is selected.
The switch control circuit 1136 is the switch control circuit 2 of FIG.
Similar to 36, it controls switch 1134. That is, the switch 1134 is
Image data at the same position on the screen with higher correlation is selected. The D / A converter 1138 converts the image data output from the switch 1134 into an analog signal, and outputs the output terminal 1
An analog image signal reproduced from 140 is output.

In the embodiment shown in FIG. 11, DC is used for correlation detection.
By using the components, accurate correlation detection can be performed, and more natural interpolation can be performed.

In the above embodiment, the correlation detection circuit is arranged on the decoder (reception side), but the correlation detection circuit is arranged on the encoder side (transmission side) to transmit the correlation information between frames frame by frame. You may do it. In this way, the equipment burden on the receiving side is greatly reduced. This is suitable for a transmission system, such as television broadcasting, which has a large number of receivers and requires a receiving device to be small in size and low in cost.

As can be easily understood from the above description,
According to the present invention, error-uncorrectable data is interpolated by inter-screen correlation information, so that more natural interpolation can be performed and a reproduced image (received image) with less unnaturalness can be provided.

(Seventh Embodiment) FIG. 12 shows a seventh embodiment of the present invention.
It is a block diagram showing an example of. The transmission data input from the input terminal 631 is D
The 0 run length is decoded to a PCM code and is output to the counter 632. The counter 632 counts the 0 run length and the number of DPCM codes until the reset sync comes. That is, the counter 632 counts the number of pixels in a predetermined processing unit. The number of pixels calculated by the counter 632 is output to the comparator 636. In addition, the comparator 636
Compares the predetermined number of pixels set by the processing unit setting unit 634 with the number of pixels output from the counter 632, and 1b
The error flag of it is output to the switch 640. That is, if they do not match, it is determined to be an error and a flag is set.

On the other hand, the DPCM code decoded by the run length decoder 633 is output to the DPCM decoder 635 and decoded into image data. DPCM decoder 635
The output image data is output to the delay device 638. The delay device 638 delays by a constant delay amount generated in the comparator 636, and adjusts the timing of the error flag and the image data. The image data output from the delay device 638 is output to the contact a of the switch 640, while 1
The signal is output to the line delay unit 639, delayed by one line, and then output to the contact b of the switch 640. The error flag output from the comparator 636 is connected to the contact a of the switch 640 when no error occurs. If an error occurs, the image data one line before the switching of the contact point b of the switch 640 is replaced and corrected. The corrected image data is output to the output terminal 637.

In the above embodiment, the coding method in which the DPCM coding and the run length coding are combined has been described, but the run length coding such as the coding for performing the run length coding after the orthogonal transform coding is performed. It is needless to say that it can be applied to all the schemes that use the conversion. It can also be used in each of the above-mentioned embodiments.

As described above, according to the present invention, by providing the error detecting means peculiar to the run length code decoding, it is possible to easily prevent the deterioration of the image quality when the error occurs.

FIG. 17 is a block diagram showing an encoding method in which the orthogonal transform encoding method and the run length encoding method are used in combination. The image data input from the input terminal 711 is blocked by the blocker 713 as shown in FIG. In this case, horizontal 8 pixels,
Blocked into 8 vertical pixels. The blocked pixel data is converted by a conversion encoder. The transform encoder 715 uses a transform coding method called discrete cosine transform (hereinafter referred to as DCT).

Generally, an image is DCTed as shown in FIG.
The converted coefficient has a low diagonal resolution, and the higher the frequency component, the smaller the value. The DCT-transformed coefficient is quantized by the quantizer 717.
The higher the frequency component of the quantized transform coefficient, the higher the probability of occurrence of 0. Therefore, the zigzag scanner 717 performs zigzag scanning as shown in FIG. By performing zigzag scanning, 0 becomes continuous. The zigzag-scanned data is paired by the run-length encoder 721 with the number of 0s and the non-zero coefficient. When the processing of one block is completed, the EOB code is output.

In the entropy encoder 723, a short code is assigned to a code with a high occurrence probability, a long code is assigned to a code with a low occurrence probability, and a transmission format section 725 is assigned.
Output to. In the transmission format unit 725, SYNC is added to every few blocks as shown in FIG.

FIG. 16 is a block diagram showing the structure of a decoding device for the coding device shown in FIG.

The data transmitted through the transmission line is input to the input terminal 31, and is decoded by the entropy decoder 33 into a run length code.

The run-length decoding unit 751 performs run-length decoding and outputs it to the inverse zigzag scanning unit 37, and outputs the number of 0 runs and the number 1 other than 0, that is, the number of transform coefficients to the counter 53. To do. The counter 53 counts the number of conversion coefficients for each predetermined period. In this case, the processing unit setting unit 55 sets the number 64 of conversion coefficients, assuming that the predetermined period is one block.

The comparator 57 compares the value input from the processing unit setting unit 55 with the value input from the counter 53, and if they match, it is judged that the data was transmitted without error. It is determined that there is, and the determination result is output to the delay device 59. The delay device 59 delays by the delay amount in the inverse zigzag scanning device 37, the inverse quantizer 39 and the inverse transform encoder 41.

On the other hand, the inverse transform encoder 41 outputs the inversely transformed pixel to the terminal a of the switch 63 and also to the frame memory 61. In the frame memory 61, the pixel delayed by one frame is used as one terminal b of the switch 63.
Output to. The switch 63 selects the terminal a during a predetermined period when there is no error based on the determination result output from the delay device 59, and selects the terminal b when there is an error. That is, when there is an error, the image is corrected by replacing it with the image of the previous frame.

The rasterizer 43 converts the block sequence into a raster sequence and outputs it to the output terminal 43.

As described above, in this embodiment, by providing the error detecting means peculiar to the run length decoding, it is possible to prevent the image quality from being deteriorated when an error occurs with a simple hardware configuration.

In the error correction in the above embodiment, either the image of the previous frame or the image of the previous field may be used.

Further, the present invention is not limited to the above-mentioned embodiments, and various modifications and applications are possible within the scope of the claims.

The combination of the above embodiments is included in the concept of the present invention.

[0105]

As described above, according to the present invention, it is possible to favorably control the data amount of compressed data.

[Brief description of drawings]

FIG. 1 is a configuration block diagram of a first embodiment of the present invention.

FIG. 2 is a diagram showing an example of a data transmission format.

FIG. 3 is a configuration block diagram of a second embodiment of the present invention.

FIG. 4 is a configuration block diagram of a third embodiment of the present invention.

FIG. 5 is a diagram showing a decoding device according to a fourth exemplary embodiment of the present invention.

FIG. 6 is a diagram showing an encoding device.

FIG. 7 is a diagram illustrating a zigzag scanner 57 in FIG.

FIG. 8 is a diagram illustrating the scan restoration device 21 in FIG. 5;

FIG. 9 is a configuration block diagram of a fifth embodiment of the present invention.

FIG. 10 is a circuit configuration example of correlation detection circuits 30 and 32.

FIG. 11 is a configuration block diagram of a sixth embodiment of the present invention.

FIG. 12 is a block diagram showing a seventh embodiment of the present invention.

FIG. 13 is a block diagram of a conventional decoding device.

FIG. 14 is a block diagram of a conventional encoding device.

15 is an explanatory diagram of the operation of FIG.

FIG. 16 is a block diagram showing an eighth embodiment of the present invention.

FIG. 17 is a block diagram of an encoding device.

FIG. 18 is an operation explanatory diagram of FIG. 17;

FIG. 19 is an operation explanatory diagram of FIG. 17;

20 is an explanatory diagram of the operation of FIG.

FIG. 21 is an operation explanatory diagram of FIG. 17;

[Explanation of symbols]

 751 Run Length Decoder 753 Counter 755 Processing Unit Setter 757 Comparator

Claims (1)

[Claims] 1. A means for decoding data subjected to run-length coding after orthogonal transformation, and a judging means for judging whether or not the number of data run-length decoded by the decoding means matches a predetermined number. An image processing apparatus comprising: