JP2956228B2 - Timing check method for digital circuits - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timing check system for designing a digital circuit having a logic element, for example, a semiconductor memory (RAM) or a nonvolatile memory.

Normally, in the timing check of a semiconductor memory (RAM) or a non-volatile memory, the specifications of the write and read timings differ depending on the type, but recently various types of the semiconductor memory (RAM) and the non-volatile memory have been diversified. The specifications of the above timing have been diversified with the development of
An effective timing check scheme is needed.

[0003]

2. Description of the Related Art FIG. 5 is a diagram for explaining a conventional timing check method for a semiconductor memory (RAM).

Conventionally, a timing check of a digital circuit equipped with a semiconductor memory (RAM) or a nonvolatile memory is performed by:
As described above, the details of the check contents are different for each memory. Therefore, each time it is dealt with by developing or modifying the program.

FIG. 5 shows an example of the configuration of the conventional timing check program. First, the type of semiconductor memory (RAM) mounted on the digital circuit (A type,
B type, ...) is determined (see processing step 60), and the program branches to a program corresponding to the type of the timing check target.

In a branch destination processing step 61, a clock pin is searched for a terminal (pin) of the digital circuit. (Refer to processing step 61) When the clock pin is detected, the semiconductor memory (RA
The delay time, pulse width, variation, etc. to the clock terminal of M) are calculated. (See processing step 62)
An address pin of the digital circuit is searched, and when the address pin is detected, a delay time, a pulse width, a variation, etc., to an address terminal of the semiconductor memory (RAM) are calculated, and the clock at the clock terminal is calculated. The relative relationships with the delay time, pulse width, and variation are compared.
Similarly, when the data pin of the digital circuit is searched and the data pin is detected, the delay time, pulse width, and variation to the data input terminal of the semiconductor memory (RAM) are determined. And the like, and the relative relationship with the clock delay time, pulse width, variation, etc. at the clock terminal is compared. (Processing step 6
The comparison result is temporarily stored in a memory or the like, and then output to an output device such as a display. (See processing steps 70 and 71)

[0007]

As described above, in the conventional method, a program for timing check is set in accordance with the type of a logic element, for example, a semiconductor memory (RAM). New, semiconductor memory (R
Every time (AM) is issued, it is necessary to develop a program or to modify an existing program corresponding to a certain type, so that it takes a lot of man-hours and takes a long time to respond.

In view of the above-mentioned conventional disadvantages, the present invention reduces the number of development steps of a check program for performing a timing check at the time of designing a digital circuit equipped with a logic element, for example, a semiconductor memory (RAM) or a nonvolatile memory. It is an object of the present invention to provide a timing check method capable of performing the above.

[0009]

The above problems can be solved by a digital circuit timing check system configured as follows.

This is a method in which a timing check at the time of designing a digital circuit equipped with a logic element, for example, a semiconductor memory (RAM) or a non-volatile memory is performed by a program, and a semiconductor memory (RAM) or a non-volatile memory is input from each input pin. Trace the circuit up to this point and create at least the maximum value, minimum value, and variation of the delay value of each path, check formulas for checking the delay value, and libraries 20, 21 of check values Means, a check value table 30 for setting the check value, and a delay value variable table 31 for setting the variable values in the check expression in the library by adding the delay value of each path by the trace. The check value table 30 is created by referring to the check value library 21 and the check expression library 20 is referred to. Then, a variable corresponding to the check formula from each pin of the digital circuit to each semiconductor memory (RAM) or nonvolatile memory is obtained, and a delay value corresponding to the variable is calculated based on the trace result. Then, the delay value variable table 31 is set in the delay value variable table 31 to create the delay value variable table 31, and the values of the created check value table 30 and the check variable table 31 and the library-based check formula are used. The timing check is performed by comparing each path delay value calculated based on the timing.

[0011]

In other words, according to the timing check method of the present invention, the setup time (TAS) and the hold time of an address line for a logic element, for example, a semiconductor memory (RAM)
A check value for checking (TAH) and a timing check formula are stored in a library, and the values of variables (clock and address variables) of the timing check formula in the library are input to the digital circuit. The delay value of each path obtained by tracing from the pin to the semiconductor memory (RAM) is calculated based on the delay value and set in the delay value variable table.

On the basis of the delay value set in the delay value variable table, a clock terminal of a semiconductor memory (RAM) and the clock terminal of a semiconductor memory (RAM) are input from the input pin of the digital circuit according to the timing check formula stored in the library. The delay value up to the address input terminal, which is an example, is calculated and compared with the check value of the semiconductor memory (RAM) in the library.

For example, in order to guarantee the setup timing (TAS) of the address signal, the maximum delay value (A) of the rising timing of the address signal is calculated from the minimum delay value (CK.EUBN: variable) of the rising timing of the clock.
D.EUBXU: variable) must be larger than the set-up time (TAS) of the address line in the library. A check formula for checking the setup time (TAS) of the semiconductor memory (RAM) is formed into an equation using the above variables, and the setup time (TAS) of the address required for the semiconductor memory (RAM) is stored in a library as a check value.

Therefore, by changing the contents of the library and creating a delay value variable table corresponding to the variables constituting the changed check formula, a timing check corresponding to an arbitrary semiconductor memory (RAM) can be performed. Can be performed without changing the program, and there is an effect that the number of steps for developing the check program can be significantly reduced.

[0015]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 to 4 are views showing one embodiment of the present invention,
(a) shows an example of a check expression library, (b) shows an example of a check value library, (c) shows a configuration example of a check value table, (d) shows a configuration example of a delay variable table, (e) shows an example of the processing flow, and (f) shows the setup time (TAS) and hold time (TA) of the address signal.
H) and a definition example.

In the present invention, the difference between the delay value of the clock signal and the delay value of the logic element mounted on the digital circuit, for example, a semiconductor memory (RAM), for example, the signal of the address line / data line, is divided by the setup time ( TAS) and a hold time (TAH)｝, and the check values are converted into a library to provide a check expression library 20 and a check value library 21, and the variables (AD.EUBN, CK.EUBXU, etc.) (delay value)
Is added to each path delay value obtained by tracing the digital circuit and set in a delay value variable table 31, and the above check value is set in a check value table 30,
The value of the variable corresponding to the check expression obtained from the check expression library 20 is stored in the delay variable table 31.
Calculate according to the check formula,
Means for comparing the calculation result with the value of the check value library 21 according to the check formula is a means necessary for carrying out the present invention. Note that the same reference numerals indicate the same object throughout the drawings.

A timing check method for a digital circuit according to the present invention will be described below with reference to FIGS. Fig. 1 (a)
Shows an example of a check expression library, <2.1U>, <2.
1D> shows an example of a check formula for checking the hold time (TAH) of the address signal, and <2.2U> and <2.2D> show examples of a check formula for the setup time (TAS) of the address signal.

In FIG. 1A, AD.EUBN (variable, hereinafter abbreviated) indicates the minimum delay value of the rising edge of the address signal, and AD.EDBN indicates the minimum delay value of the falling edge of the address signal. , AD.EUBX indicates the maximum delay value of the rising edge of the address signal, AD.EDBX indicates the maximum delay value of the falling edge of the address signal, and CK.EUB
NU indicates the minimum delay value of the rising edge of the clock signal, CK.EUBXU (not shown) indicates the maximum delay value of the rising edge of the clock signal, and CK.CYCLE indicates the clock cycle.

Therefore, the hold time (TAH) of the address signal indicated by the above check formulas <2.1U> and <2.1D> is as shown in FIG.
As is clear from (f), the minimum delay value of the rising and falling edges of the address signal (AD.EUBN, AD.EDB
This indicates that the difference obtained by subtracting the maximum delay value (CK.EUBXU) of the rising edge of the clock signal from (N) must be larger than the check value (TAH).

Similarly, the set-up time (TAS) of the address signal indicated by the above check formulas <2.2U> and <2.2D> is
As is clear from the figure (f), considering the CLK A point as a reference, the rising of the address signal from the minimum value of the clock cycle (CK.CYCLE) + the delay value of the rising of the clock signal (CK.EUBNU), Maximum falling delay value (A
D.EUBX, AD.EDBX) minus the check value (TAS)
It indicates that greater is needed.

Hereinafter, a specific timing check method will be described with reference to FIGS. 1 (a), (b), (c), FIGS. 2 (d) and 4 (f) while referring to the processing of FIG. 3 (e). This will be described using a flow. First, prior to checking the digital circuit, FIG. 1 (a), (b)
The check expression library 20 and the check value library 21 shown in FIG.

Each code on the right side (eg, AD.EUBN) in the check expression library 20 is a variable having the above meaning, and the code on the left side (TAH, TAS) is a check value.
Since the logical connection of the digital circuit and the delay value of each path are obtained in advance and stored in a delay analysis file (not shown), the delay analysis file is read. ｝ Refer to processing step 50 in Fig.3 (e)｝
For the delay value specified for start pin A,
The circuit is traced from the start pin A to the clock pin (CLK) of the semiconductor memory (RAM), and the delay value of each path stored in the delay analysis file is added.

At this time, all the values (variables) necessary for the timing check, such as the maximum delay value and the minimum delay value as described in FIG.
Clock pin delay value variable table shown in (d) 31
Set to.

Similarly, the delay value specified for the start pin E is traced from the start pin b to the address pin (AD) of the semiconductor memory (RAM), and the delay value of each path is added. It is set in the address pin delay value variable table 32 shown in FIG.

In the circuit example shown in FIG. 2D, since the address signal is clock-synchronized by the flip-flop (FF), the address signal is synchronized by the clock at the point B of FIG. 4F. The delay value is calculated as an address signal. {See processing steps 51 and 52 in FIG. 3 (e)} Read the above check value library 21 and set it in the check value table 30.処理 Processing step 5 in Fig. 3 (e)
Refer to 3｝ Read and decode the above check formula library 20, and store each variable corresponding to check formulas <2.1U>, <2.1D>, <2.2U>, <2.2D> in the clock pin variable table 31,
It is taken from the address pin variable table 32 and is calculated according to the check formula.処理 Processing steps of Fig.3 (e)
54, 55 54This calculation result and the value of the above check value table, that is, the setup time (TAS) of the address signal
And hold time (TAH). ｛Figure 3 (e)
In the above example, the setup time (TAS) and the hold time (TAH) are checked. However, there is another method such as a pulse width check.

The check value, the value of the variable used for the check, and the check result are output to an output device (not shown). << Refer to processing step 56 in FIG. 3E >> In the above embodiment, the clock pin and the address pin have been described as examples, but other input pins of the semiconductor memory (RAM), for example, data in, write enable, check The same processing is performed for select and the like.

In the above embodiment, the method of checking the delay value of each signal line from the input pin to the semiconductor memory (RAM) has been described. However, the present invention is not limited to the semiconductor memory (RAM). It goes without saying that the same timing check method can be applied to other logic elements such as files.

As described above, in the present invention, a logic element mounted on a digital circuit, for example, a semiconductor memory
(RAM), for example, the difference between the delay value of the address line / data line signal and the clock signal divided by the setup time (T
AS) and hold time (TAH) チ ェ ッ ク
The check values are converted into a library, and check expression libraries 20, 21 are provided, and the variables (A
D.EUBN, CK.EUBXU, etc.), add the delay value of each path obtained by tracing the digital circuit, set it in the delay value variable table 31, and check the above check value After setting the value in the value table 30, the value of the variable corresponding to the check formula obtained from the check formula library 20 is fetched from the variable in the delay variable table 31 and calculated according to the check formula. A feature is that comparison is made with the value of the check value library 21 according to the check formula.

[0029]

As described above in detail, the timing check method of the digital circuit of the present invention can be applied to a logic element,
For example, to check write / read timing in a semiconductor memory (RAM) or nonvolatile memory by a program, trace the circuit and determine the delay value (maximum value, minimum value, variation) of each path in advance. Calculate and library the timing check formula and check value, set the check value in the check value table, and store the path delay based on the trace result in the delay variable table for clock pins, address pins, etc. The value is added and set, and the value of the check value table and
Since the timing check is performed by comparing the value of the delay variable table with the delay value obtained by substituting the value into the above-described check formula stored in the library, the contents of the library are changed and the changed By creating a delay value variable table corresponding to the variables that make up the check formula, it is possible to perform a timing check for any semiconductor memory (RAM) without changing the program, This has the effect of greatly reducing the number of development steps.

[Brief description of the drawings]

FIG. 1 shows an embodiment of the present invention (part 1).

FIG. 2 shows an embodiment of the present invention (part 2).

FIG. 3 shows an embodiment of the present invention (part 3).

FIG. 4 shows an embodiment of the present invention (part 4).

FIG. 5 is a diagram for explaining a conventional semiconductor memory timing check method;

[Explanation of symbols]

20 Check expression library 21 Check value library 30 Check value table 31,32 Delay value variable table RAM Semiconductor memory CLK clock AD address TAH Address signal hold time TAS Address signal setup time AD.EUBN, AD.EUBXU, ~ variable

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 17/50 G06F 11/26 G01R 31/28

Claims (1)

(57) [Claims] 1. A method for performing a timing check by a program at the time of designing a digital circuit having a logic element mounted thereon, wherein the circuit is traced from each input pin to the logic element and at least the delay value of each path is calculated. ,Maximum value,
A means for finding the minimum value and variation, a check formula for checking the delay value, and a library of check values (20,
21), a check value table (30) for setting the check value, and a variable value in the check expression in the library are set by adding each path delay value obtained by the trace. Delay value variable table (3
1), the check value table (30) is created by referring to the check value library (21), and each of the pins of the digital circuit is referred to by referring to the check expression library (20). A variable corresponding to the check formula up to the logic element is obtained, a delay value corresponding to the variable is calculated based on the trace result, and the delay value variable table (31) is calculated.
To create the delay value variable table (31),
A timing check is performed by comparing the value of the created check value table (30) with each of the path delay values calculated based on the check variable table (31) and the check formula stored in the library. Digital circuit timing check method.