JP2001229211A - Method of verifying asynchronous circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of verifying asynchronous circuit which simplifies the verification operation in a function simulation on a language level and also shortens its verification TAT. SOLUTION: The method of verifying asynchronous circuit defines the metastable state of output data according to whether or not the input data of a logic circuit is different from a value held by the logic circuit when the clock signal of the logic circuit is active, generates a prescribed value accompanying the metastable state and outputs the prescribed value from the logic circuit only for a fixed period in the case of verifying the operation of an asynchronous logic circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for verifying an asynchronously operated electronic circuit, and more particularly to a method for verifying a plurality of sequential circuits operated by clock signals having different periods.
The present invention relates to a method for verifying an asynchronous circuit in which output data of each sequential circuit is combined and becomes input data of another sequential circuit.

[0002]

2. Description of the Related Art When a function of an actual device such as a gate array is tested, individual characteristics of the actual device of the same model generally vary. Therefore, in a functional tester of an actual device, an FF (flip-flop) inside the tester is used.
However, different operations may be performed due to the variation in the characteristics. Therefore, there has been a tester circuit which intentionally shifts the timing of input signals in order to induce a malfunction of the tester.

For example, there is a conventional tester circuit disclosed in Japanese Patent Application Laid-Open No. 5-189517. This conventional example is a tester simulation circuit on the premise of a functional test of an actual device, and has the purpose of changing the setup and data hold characteristics in an FF model of the tester and comparing it with parameters of the output characteristics of the actual device. Was. Therefore, the input signal from the actual device and the operation clock of the tester are connected to the FF of the tester through separate delay elements.
It has a configuration that has been introduced.

With this configuration, the synchronization timing of the operation clock with respect to the input signal is shifted back and forth by an arbitrary time to simulate a data hold function of a tester for an actual device. That is, this was to verify a malfunction in the synchronous circuit. In practice, however, practical functional simulations are often performed for asynchronous circuits having different synchronization timings.

In general, as a method of verifying an asynchronous circuit,
There is a method using a gate-level netlist. In this method, a simulation is performed in consideration of the timing of each clock signal, and thereby the setup and hold timing of each sequential circuit is verified. In recent years, hardware description languages such as HDL have been used, and it has become possible to design electronic circuits from functional design.

Therefore, it is necessary to perform functional simulation at the language level even when verifying an asynchronous circuit. As a method of verifying an asynchronous circuit that meets this demand, there is a method of performing a simulation while variously changing the conditions of the periods and phases of a plurality of clock signals in a functional simulation. According to this, it is possible to intentionally increase the probability of occurrence of a defect in the operation of the electronic circuit to be verified.

FIG. 4 is a flowchart of a method of verifying an asynchronous circuit according to a conventional example. In this conventional example, an active edge detection process B of a clock signal in a sequential circuit is performed.
1. A process S7 for holding the input data to the sequential circuit and a process S8 for outputting the held data.

[0008]

However, when the function simulation of each sequential circuit is performed at the language level by using such a conventional method of verifying an asynchronous circuit, the following technical problems are solved. Had to be kept.

In general, a sequential circuit may have a metastable state in which the logic of the output data is not determined. However, according to the above-described flowchart, there is no process for maintaining such a state for a certain period. For this reason, for each sequential circuit configured in the next stage, conditions of different clock signal periods and phases are used in various combinations to simulate an operation failure that may occur in an asynchronous circuit.

Therefore, in the conventional method for verifying an asynchronous circuit, it is necessary to perform a functional simulation at a language level in which a large number of conditions relating to clock signals are inevitably combined. As a result, the description of the test bench required for the simulation of the operation of each sequential circuit is complicated, and the entire functional simulation by the verification method tends to be complicated.

Further, when a simulation is performed by combining various conditions relating to the clock signal in this way, the simulation time for each operation of each sequential circuit becomes longer. For this reason, the verification TAT increases in the entire function simulation, and it is extremely important to collectively solve these various technical problems.

Accordingly, an object of the present invention is to provide a method of verifying an asynchronous circuit in which a verification operation in a functional simulation is simplified at a language level and a verification TAT is shortened.

[0013]

According to a first aspect of the present invention, there is provided an asynchronous circuit verification method for verifying the operation of an asynchronous logic circuit. When the clock signal is active, the process of defining that the output data is in a metastable state depending on whether the input data of the logic circuit is different from the held value of the logic circuit, and this metastable state is defined. Then, a process for generating a predetermined value and outputting it for a certain period is provided.

According to this asynchronous circuit verification method, when the active edge of the clock signal is detected by the logic circuit, if the value of the input data has changed from the value one cycle before, the operation of the logic circuit is reduced. Defined to be metastable. Then, a predetermined value based on the metastable state is formed and output as output data of the logic circuit. If the value of the input data has not changed, the output data with the value one cycle before is output as it is.

According to a second aspect of the present invention, there is provided a method for verifying an asynchronous circuit, wherein the logic circuit has one or a plurality of sequential circuits. According to this, it is widely used for various logic circuits.

According to a third aspect of the present invention, there is provided a method for verifying an asynchronous circuit, wherein the logic circuit has a flag indicating a metastable state. According to this, the metastable state is determined by the flag.

In a method for verifying an asynchronous circuit according to a fourth aspect of the present invention, the output processing generates a metastable state based on a result of checking a flag.
According to this, it can be realized by a general-purpose programming method.

According to a fifth aspect of the present invention, there is provided a method for verifying an asynchronous circuit, wherein the output process holds input data when a metastable state occurs. According to this, the value of the input data that caused the metastable state is held.

According to a sixth aspect of the present invention, in the method of verifying an asynchronous circuit, the output process is configured to output input data after a lapse of a predetermined period. According to this, the value of the input data that has caused the metastable state is output.

[0020]

Embodiments of the present invention will be described below in detail with reference to the drawings. The same parts as those in the above-described conventional example are denoted by the same reference numerals, and detailed description is omitted.

FIG. 1 is a flowchart illustrating an example of a configuration in which a method for verifying an asynchronous circuit according to an embodiment of the present invention is applied to an asynchronous circuit including a sequential circuit. This embodiment includes a process B1 for detecting an active edge of a clock signal supplied to a sequential circuit after an initial process, and a process B2 for detecting that a value of input data to the sequential circuit has changed at the active edge. A process B3 for detecting whether or not the sequential circuit is in a metastable state, a process S5 for setting a flag to true if not in a metastable state, and a process S1 for setting a flag to false in a metastable state. is there.

Further, each processing S for setting these flags is performed.
Following S1, S5, a process S2 for storing the value of the input data in the variable d, a process S3 for generating a predetermined value of the metastable state of the sequential circuit and storing it in the variable meta, and storing the stored predetermined value in the variable Qout To step S4.

Processing B for detecting a change in input data
When no change is detected in step S2, the sequential circuit does not enter the metastable state, so that the flag is set to false in step S6.
Is provided in step S7. Further, when the active edge is not detected in the process B1 for detecting the active edge of the clock signal, a process S9 for setting the flag to false is provided similarly to the process S6 described above. Further, following the processes S7 and S9, there is a process S8 for moving the value of the held data from d to Qout. The first process is a start process, and the last process is a finish process.

FIG. 2 is a circuit diagram of an example of an asynchronous circuit to which the verification method shown in FIG. 1 is applied. The operation of each sequential circuit will be described with reference to FIG. This asynchronous circuit includes an adder ALU1 and a sequential circuit F in the preceding and following stages.
F1 and FF2 are sequentially arranged, and the sequential circuit FF1
Output data Q1 from the adder ALU1
After that, it is input as input data D1 to the sequential circuit FF1. Also, the output data Q1 of the sequential circuit FF1
Is input as input data D2 to the sequential circuit FF2.

The sequential circuit FF1 has a flag MF1 indicating its metastable state, and the sequential circuit FF2 has another flag MF indicating its other metastable state.
2 are provided side by side. At this time, of the two clock signals CLK1 and CLK2 having different periods, the clock signal CLK1 is supplied to the sequential circuit FF1, and another clock signal CLK2 is supplied to the sequential circuit FF2.

[Explanation of Operation According to Embodiment] An example of the operation of the embodiment according to the present embodiment will be described below. First, a method of verifying an asynchronous circuit will be described with reference to FIGS. In this case, the clock signals CLK1,
The sequential circuit FF1 operates according to the input data D1, outputs the output data Q1, and outputs the clock signals CLK2,
The sequential circuit FF2 operates according to the input data D2 and outputs the output data Q2.

First, in the process B1, the edges of the clock signals CLK1 and CLK2 are detected. When this edge is detected (Yes), the process proceeds to processing B2. When this edge is not detected (No), the flag MF is set.
1. In step S9, MF2 is changed to false. When an edge is detected, it is detected in process B2 whether the value (Din) of the input data D1, D2 has changed. When a change in this value (Din) is detected (Yes)
Moves to processing B3, but if this is not detected (N
In o), the flags MF1 and MF2 are changed to false in step S6.

As described above, in the processes S9 and S6, the values of the flags MF1 and MF2 are set to a state that is not a metastable state (false). Subsequently, in step S7, the value (Din) is stored as a variable (d). Then, in a process S8, the variable (d) is moved to a variable (Qout) to obtain the values of the output data Q1, Q2, and the sequential circuits FF1,
Output from FF2.

By a series of these processes S6, S7 and S8, an operation can be performed when the clock signals CLK1 and CLK2 are active and the value (Din) has not changed from one cycle before. In addition, by the processes S9 and S8, the operation in the inactive state can be performed. Thereby, the sequential circuit FF
1. After the FF 2 outputs the predetermined value in the metastable state, the held data can be output in the output operation one cycle later.

When the change of the input data D1 and D2 is detected in the process B2, the flag MF
1. Check the value of MF2. Then, the flag MF
1. If MF2 is true, change to false in step S1, and after holding input data D1, D2 in step S2, generate a metastable state in step S3.
Finally, in step S4, the predetermined value in the metastable state is set as the value of the output data Q1, Q2, and the sequential circuits FF1, F2
Output from F2. In processing B3, the flags MF1, M
If F2 is false, after changing to true in step S5, the above-described steps S2, S3, and S4 are sequentially performed.

The series of processing S2, S3, S4 allows the clock signals CLK1, CL, which are a feature of the present invention.
When K2 is active and the input data D1 and D2 have changed from one cycle before, a metastable state can be output. In other words, the metastable state accompanying the change of the input data (for example, D1) can be defined at the language level from the active edge of one clock signal (for example, CLK1) by the above-described functional algorithm.

Further, two clock signals CLK1,
When a phase difference occurs between CLK2s, malfunctions are successively caused within the basic one cycle time in accordance with the algorithm. Through the processing of each of these algorithms, the functions of the asynchronous circuit can be simulated in many aspects and verified in a short time without complicating the description of each test bench and the entire function simulation.

[0033] For example, in the process S2, the variable (d)
Generates a random value that can be taken and stores it in variable (d)
The value (Din) is compared with the
Is stored in a variable (meta)
By setting the state to a predetermined value, the metast
Cable state and verify its malfunction.
You.

FIG. 3 is a timing chart of the operation of the asynchronous circuit shown in FIG. The operation timing according to the present embodiment will be described with reference to FIGS. Hereinafter, in the sequential circuit FF1 shown in FIG. 2, the clock signal CLK1 changes every three cycles, and the sequential circuit FF2
Here, it is assumed that the clock signal CLK2 changes every four cycles.

The value (Din) of the input data D1 to the sequential circuit FF1 is obtained by adding +1 (= 1) to the value (Qout) of the output data Q1 from the sequential circuit FF1 in the initial state by the adder ALU1. It is. At the rising edge of the clock signal CLK1 in the third cycle, the input data D1 is input to the sequential circuit FF1. This value (Din) is equal to the value (Qou) of the output data Q1 in the fourth period, which is one subsequent period.
t) and the value (= 1) is output.

Subsequently, in the third cycle, when the clock signal CLK1 is in the active state, the value (Din) changes from the value one cycle before. Therefore, the flag MF1
Becomes true (= 1), and the value of output data Q1 (Qo
ut) is output as a predetermined value (= 6) in the metastable state. In the fourth cycle, the clock signal CLK1 is in an inactive state, so the value (D
The value input and held as in), that is, the value (= 1) of the input data D1 in the third cycle is output as output data Q1.

Similarly, the ninth, tenth, fifteenth, sixteenth,
In each of the 21st and 22nd cycles, the value of the flag MF1 becomes true (set) within one cycle. Then, after outputting each predetermined value in the metastable state as the value Qout, each value input and held as the value (Din) one cycle earlier is output.

In the sequential circuit FF2, the value (Dout) of the output data Q1 from the sequential circuit FF1 is input as the value (Din) of the input data D2. After the value (= 6) is taken in as the value (Din) of the input data D2 at the rising edge of the clock signal CLK2 in the fourth cycle,
The value (Qout) of the output data Q2 becomes the value (= 6).

At this time, like the sequential circuit FF1, the fourth
When the clock signal CLK2 is active in the cycle, the value (Din) of the input data D2 changes from the value one cycle before, that is, the value when the sequential circuit FF2 is in the initial state. Therefore, the value of the flag MF2 of the sequential circuit FF2 becomes true, and the predetermined value (= 3) in the metastable state is output as the value (Qout) of the output data Q2. Further, since the clock signal CLK2 becomes inactive in the fifth cycle, the value held as the value (Din) one cycle before, that is, the value (= 6) in the fourth cycle is the value Q.
Output as out.

Similarly, the twelfth, thirteenth, and second
0, in each of the 21st cycles, the flag M
The value of F2 becomes true, and each predetermined value in the metastable state is output as the value Qout. Thereafter, each value held as a value (Din) one cycle before that is output.

At this time, the sequential circuit FF in the fourth cycle
The value (= 6) taken as the value (Din) of the input data D2 of No. 2 is a value in the metastable state generated by the sequential circuit FF1. Therefore, a value (Din) of the originally expected input data D2, that is, a value different from the value (= 1) of the output data Q1 of the sequential circuit FF1 in the fourth cycle is input to the sequential circuit FF2. Therefore, the operation of this asynchronous circuit causes a problem from the fifth cycle to the twelfth cycle.

From this, it can be seen that the change in the clock signal CLK1 in the third cycle and the change in the clock signal CLK2 in the fourth cycle are timings that cause problems with the operation of the asynchronous circuit.

In the above embodiment, the active edge of the clock signal is set to a rising change. However, the same applies to a case where the falling edge changes. Also,
The same effect can be obtained by combining a sequential circuit in which the active edge of the clock signal rises and a circuit in which the active edge of the clock signal falls as the configuration of the asynchronous circuit.

[0044]

As described above, the effects of the present invention are as follows.
An algorithm can be realized in which a forced metastable state is generated for each active edge of the clock signal, and this state is maintained in the logic circuit for one cycle. For this reason, it is not necessary to verify the operation check by describing various conditions of the clock signal. In addition, similarly to the conventional function simulation in consideration of the operation timing, it is possible to reproduce the malfunction of the operation in the logic circuit. Therefore, description and verification work of a test bench required for functional simulation at a language level can be simplified, and the verification TA
T can be shortened as a result.

[Brief description of the drawings]

FIG. 1 is a flowchart illustrating a configuration example of a method for verifying an asynchronous circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of an example of an asynchronous circuit to which the verification method shown in FIG. 1 is applied.

FIG. 3 is a timing chart showing an example of an operation in the asynchronous circuit shown in FIG. 2;

FIG. 4 is a flowchart of an asynchronous circuit verification method according to a conventional example.

[Explanation of symbols]

 ALU1 Adders B1 to B3, S1 to S9 Processing CLK1, CLK2 Clock signals D1, D2 Input data FF1, FF2 Sequential circuit Q1, Q2 Output data

Continuation of the front page (72) Inventor Yoji Tachibana 1-403, Kosugi-cho, Nakahara-ku, Kawasaki-shi, Kanagawa 53 F-term in NEC Ic Microcomputer System Co., Ltd. 5B046 JA04

Claims (6)

[Claims] In an asynchronous circuit verification method for verifying operation of an asynchronous logic circuit, when a clock signal of the logic circuit is active, it is determined whether input data of the logic circuit is different from a value held in the logic circuit. Thus, there is a process of defining that the output data is in a metastable state, and a process of generating a predetermined value associated with the metastable state and outputting it for a certain period of time when the metastable state is defined. Verification method for asynchronous circuits. 2. The apparatus of claim 1, wherein said logic circuit comprises one or more sequential circuits. 3. The apparatus according to claim 1, wherein the logic circuit has a flag indicating a metastable state. 4. The apparatus according to claim 3, wherein said outputting step generates a metastable state based on a result of checking a flag. 5. The apparatus according to claim 1, wherein said output processing retains input data when a metastable state occurs. 6. The apparatus according to claim 1, wherein the outputting process causes the input data to be output after a predetermined period has elapsed.