JP2000293553A - Method and system for verifying simultaneous output operation - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the method and device capable of quickly verifying a simultaneous output operation. SOLUTION: A cycle base simulator 22 executes a logical operation in each cycle on the basis of the circuit connection information 1 of a logic circuit in which respective output signals from plural logical elements controlled so as to be simultaneously driven are to be outputted to respective prescribed output terminals at a prescribed time difference and pattern information 21 including the time difference of output signals from a prescribed output terminal of the logic circuit and outputs its logical verification result as error information 23, the error information 23, the circuit connection information 1 and a logic circuit timing restricting condition from a library 31 are inputted to a timing verification tool 32 and a verification result obtained by executing analysis considering the timing by a timing verification tool 32 is outputted as a real verification result 33.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method and a system for verifying simultaneous output operation, and more particularly to a method and system for verifying simultaneous output operation using a cycle-based simulator and timing analysis.

[0002]

2. Description of the Related Art There is an output simultaneous operation verification for verifying a time difference between signal changes of a plurality of output terminals of a logic circuit of a semiconductor integrated circuit. FIG. 7 is a diagram illustrating an example of a conventional simultaneous output operation verification method. In the figure, a logic verification is performed by a cycle-based simulator 6 to obtain a verification result 7, and a timing verification is performed by a timing verification tool 8 to obtain a verification result 9. Here, the cycle-based simulator 6 is a simulator exclusively for logic function verification that evaluates a signal value only at a clock edge, and the verification speed is increased by omitting a timing verification function. This simulator has a feature that it is usually about one or two digits faster.

Conventionally, various operation verification methods have been proposed for verifying whether a logic circuit operates as designed by a designer of a semiconductor integrated circuit. For example, Japanese Patent Laid-Open No. 4-3
Japanese Patent No. 57569 discloses a logic simulator including a simulation execution unit, a simulation control unit, and a timing check execution unit. In this logic simulator, the simulation executing means can trace the influence of the error by giving an error value indicating the presence or absence of a timing error in addition to the logical value as a signal value, and the timing check executing means makes a check result of the hold condition of the flip-flop. After the determination is completed, the check result is sent to the simulation executing means together with the check result of the setup condition.

In Japanese Patent Application Laid-Open No. 6-215060, the definition of the operation of a logic element constituting a logic circuit and information on the connection relationship between the logic elements are received, and the constraint on the operation timing of the logic element is guaranteed. Detection means for detecting whether or not the information is present and adding the detection result to the information to obtain first circuit information; and detecting only the logic element which receives the first circuit information and does not guarantee the operation timing constraints. Timing verification means for verifying the timing,
An operation verification method that reduces the number of logic elements to be subjected to timing verification is disclosed.

In Japanese Patent Application Laid-Open No. Hei 8-222456, a setup time and a hold time of a flip-flop are checked by using an initial check reference value having a large margin. Back trace the activation path to the input terminal and the data input terminal to obtain the typical delay time of the elements on the path and the delay variation time in the target logic circuit, and consider this to obtain a highly accurate check reference value. Set, compare this with the setup time and hold time required for the flip-flop and perform a timing check. If an error occurs in the two-step check, display the path, delay information, and waveform and display the timing. A timing verification method that verifies timing errors at high speed by contributing to analysis has been developed. It is.

Further, Japanese Patent Application Laid-Open No. 10-327047 discloses that a logic simulation is performed based on a logic net based on layout information which is determined by using a first logic cell using a normal flip-flop. The timing information, which is the result of the logic simulation, is compared with the design specification to verify the possibility of malfunction due to timing slip. Further, the first logic cell at the location where malfunction may occur due to timing deviation is input to the flip-flop data input. A design method is disclosed that replaces a second logic cell or a third logic cell having a delay element connected to an end or a data output end and determines a layout of the semiconductor integrated circuit. According to the technology described in each of the above publications, the simultaneous output operation verification of the above-described logic circuit can also be seen at a glance.

[0007]

However, in the conventional simultaneous output operation verification method shown in FIG. 7, the simultaneous output operation verification by the cycle-based simulator 6 is performed in units of cycles, so that the timing cannot be taken into consideration, and a sufficient interval is not provided. Therefore, even operations that satisfy the restrictions may be erroneously detected as errors. In addition, since simultaneous output operation verification by the timing analysis tool 8 is performed without considering logic, a false path (impossible logic) may be erroneously detected as an error.

Further, Japanese Patent Application Laid-Open Nos. Hei 4-357569, Hei 6-215060, Hei 8-22456
In the prior art described in each of the above publications, the simulation apparatus itself has a timing verification function, which is used to assist or enhance the use of the timing verification function. 221456
In the prior arts described in the publications, the timing check verification performed by the event-driven type logic simulator is performed, and in any case, the speed-up of the verification speed is insufficient.
Further, those described in JP-A-10-327047,
This is a layout method that reflects the timing analysis results.
The present invention relates to a technique called a so-called timing driven layout.

[0009] The present invention has been made in view of the above points,
An object of the present invention is to provide an output simultaneous operation verification method and a verification system capable of performing high-speed verification.

Another object of the present invention is to provide an output simultaneous operation verification method and a verification system capable of performing highly accurate verification.

[0011]

In order to achieve the above object, a method according to the present invention comprises a circuit connection information of a logic circuit whose time difference between signal changes at a plurality of output terminals is to be verified, and a predetermined output of the logic circuit. Based on the pattern information including the time difference between the output signals of the terminals, the logic verification result obtained by performing a logic operation in cycle units by a cycle-based simulator is used as error information, and the error information, circuit connection information, and logic circuit timing constraint conditions Is input to a timing verification tool, and a verification result obtained by performing an analysis in consideration of timing by the timing verification tool is output as a true verification result.

In order to achieve the above object, a method of the present invention is based on circuit connection information of a logic circuit whose time difference between signal changes at a plurality of output terminals is to be verified, and timing constraints of the logic circuit. A verification result obtained by performing an analysis in consideration of timing by a timing verification tool is used as error information, and the error information, circuit connection information, and pattern information including a time difference between output signals of predetermined output terminals of a logic circuit are used as a cycle-based simulator. And a logic verification result obtained by performing a logic operation in cycle units by a cycle-based simulator is output as a true verification result.

[0013] To achieve the above object, a simultaneous operation verification system according to the present invention comprises a circuit connection information of a logic circuit whose time difference between signal changes at a plurality of output terminals is to be verified, and a plurality of outputs of the logic circuit. A cycle-based simulator that takes as input pattern information including a time difference between signal changes at terminals and performs a logic operation on a cycle-by-cycle basis based on the input information to output a logic verification result as error information; First storage means for storing, a library in which timing constraint conditions of a logic circuit are stored in advance, circuit connection information, error information from the first storage means, and timing constraint conditions from the library as inputs. And outputs the verification result obtained as a result of the analysis considering the timing based on the input information as a true verification result. And timing verification tool, in which a structure having a second storage means for holding a true verification result output from the timing verification tool.

Further, in order to achieve the above object, the system of the present invention includes a library in which timing constraints of a logic circuit to be verified for a time difference between signal changes of a plurality of output terminals are stored in advance, and a library of the logic circuit. Receives circuit connection information and timing constraints from the library as inputs,
A timing verification tool for performing an analysis in consideration of timing based on the input information, a first storage unit for temporarily storing a verification result by the timing verification tool as error information, an error information from the first storage unit, The circuit connection information and the pattern information including the time difference between the output signals of the predetermined output terminals of the logic circuit are received as inputs, and the logic verification result obtained by performing the logic operation in cycle units of the input information is used as the true verification result. And a second storage means for holding a true verification result output from the cycle-based simulator.

In the cycle-based simulator, logic verification is performed in cycle units, and in timing analysis, a false error is output in the verification result due to the inclusion of a false path (impossible logic). In the simultaneous output operation verification method and verification system according to the present invention, the deterioration of accuracy in units of cycles can be eliminated by timing analysis, and false paths can be eliminated by a cycle-based simulator.

[0016]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a configuration diagram of an embodiment of a simultaneous output operation verification system according to the present invention. The output simultaneous operation verification system shown in FIG. 1 includes a cycle-based simulation environment 2 receiving circuit connection information 1 from a first database as an input, and the circuit connection information 1 and error information from the cycle-based simulation environment 2. It consists of a timing analysis environment 3 that receives as input and obtains a true detection result.

The cycle-based simulation environment 2 receives the circuit connection information 1 and the pattern information 21 from the second database and performs a cycle-based logic operation to output a verification result obtained as error information. It comprises a base simulator 22 and a memory for storing error information 23. As described above, the cycle-based simulator 22 itself is a conventionally-known simulator dedicated to logic function verification, and a detailed description thereof will be omitted.

The timing analysis environment 3 receives the timing constraint library 31, the circuit connection information 1, the error information from the cycle-based simulation environment 2, and the timing constraint information from the timing constraint library 31, and receives the false information based on the error information. A timing analysis tool 32 that eliminates a path and outputs a true detection result under the conditions of timing constraint information, and a memory 33 that holds the true detection result
And The timing analysis tool 32 is conventionally known software dedicated to timing verification.

In this embodiment, the logic verification unit does not have a timing verification function.
2, the timing verification is performed by the static timing analysis tool 32, and information is exchanged between these individually existing verification functions to perform high-speed and high-performance simultaneous output operation verification.

Next, the operation of this embodiment will be described with reference to FIGS.
This will be specifically described with reference to FIG. First, it is assumed that the circuit connection information 1 input from the database is the information of the circuit shown in FIG. In the circuit shown in FIG. 2, of the four D-type flip-flops 204 to 207 to which data DATA is commonly supplied to the data input terminal D, two flip-flops 204 and 205 receive the enable signal EN and the clock CLK. The output signal of the AND circuit 202 is input to a clock terminal in common and operates simultaneously.
The other two flip-flops 206 and 207 are configured to operate at the same time when the output signal of the AND circuit 203 to which the enable signal inverted by the inverter 201 and the clock CLK are input is commonly input to the clock terminal. .

The Q output terminal of the flip-flop 204 is connected to an output terminal 216 via four buffers 208 to 211 in series.
The output terminal is output terminal 2 via one buffer 212.
17 and the Q output terminal of the flip-flop 206 is connected to the output terminal 218 via two buffers 213 and 214 in series.
The output terminal is output terminal 2 via one buffer 215.
19 is connected. That is, the number of buffers on the output side of the flip-flops 204 and 205 that operate simultaneously in a pair differs from each other, and similarly, the number of buffers on the output side of the flip-flops 206 and 207 that operate simultaneously in a pair differs from each other.

Therefore, flip-flops 204 and 205
Are controlled simultaneously, but the output terminals 216 and 21
7 has a propagation time difference of three buffers. This corresponds to cycle 2 in FIG.
And cycle 3 correspond to the time differences d1 and d2. That is, the data DATA shown in FIG. 3A is input to the data input terminals of the flip-flops 204 to 207, and the clock CLK shown in FIG. 3B, the enable signal EN shown in FIG. Reset signal RESE shown in D)
When T is input to the circuit of FIG. 2, the flip-flops 204 and 205 simultaneously operate at the rising edge of CLK in cycle 2 to simultaneously output a high-level signal from the Q output terminal.

The output signal of the flip-flop 205 is output to the output terminal 217 through one buffer 212.
Although output as UT2 in a very short time, the output signal of the flip-flop 204 has four buffers 208 to 21.
1 is output to the output terminal 216 as the output signal OUT1. Therefore, the signal becomes high level with a delay of the propagation time d1 for three buffers. Similarly, flip-flops 204 and 2 at the rising edge of CLK in cycle 3
05 operate at the same time and simultaneously output a low-level signal from the Q output terminal. The output signal OUT1 has a propagation time d equivalent to three buffers compared to the output signal OUT2.
It goes low two times later.

Similarly, flip-flops 206 and 20
7 are controlled simultaneously, but the output terminals 218 and 2
19 has a propagation time difference of one buffer, the output signal OUT3 of the output terminal 218 shown in FIG. 3G is different from the output signal OUT4 of the output terminal 219 shown in FIG. , The level changes with a delay of one buffer propagation time d3, d4. The above output signal O
Information on the propagation time difference between UT1 to OUT4 is stored in the memory as pattern information 21.

The above circuit connection information 1 and pattern information 21
Is input to the cycle-based simulator 22,
Logic verification is performed in cycle units (step A1 in FIG. 4). Thereby, OUT1 and OUT2 in cycle 2 and cycle 3 and cycle 4 and cycle 5 in FIG.
Output simultaneous error information 2 for OUT3 and OUT4
The report No. 3 is output from the cycle-based simulator 22 and stored in the memory (step A2 in FIG. 4).
The error information 23 stored in this memory is indicated by I in FIG.

Subsequently, it is determined whether or not error information has been detected (step A3 in FIG. 4). If no error information has been detected, the processing is terminated. Here, since the error information 23 has been detected, Then, a timing analysis process is performed (step A4 in FIG. 4). In this timing analysis processing, the change time difference between the output signals at the output terminals from the timing constraint library 31 of FIG.
This is performed by inputting a timing constraint condition that a delay time equal to or less than one as an error together with the error information 23 and the circuit connection information 1 by the timing analysis tool 32.

The timing analysis tool 32 reads the error information 23 and outputs the signal OUT1 in cycle 2 and cycle 3.
It verifies whether or not the change time differences d1 and d2 between OUT1 and OUT2 satisfy the above-described timing constraint condition, and outputs a detection result as an error when the constraint condition is not satisfied (step A5 in FIG. 4). Similarly, it is verified whether or not the change time differences d3 and d4 between OUT3 and OUT4 in the cycle 4 and the cycle 5 satisfy the above-described constraint conditions. If the difference conditions do not satisfy the constraint conditions, a detection result is output as an error (FIG. Step A5). The above detection result is stored in the memory 33 as a true detection result.

The true detection result stored in the memory 33 is indicated by II in FIG. That is, in this case, the timing constraint condition is such that the delay time equal to or less than two buffers causes an error, so that the change time differences d3 and d4 between OUT3 and OUT4 in cycle 4 and cycle 5 satisfy the above constraint condition. However, the information is stored in the memory 32 as true simultaneous output operation error information, and it can be seen that there is an error in the circuit configuration on the output side of the flip-flops 206 and 207 in FIG.

As described above, in this embodiment, the detection result of the cycle-based simulation is positioned as an error candidate group, and the timing is verified by the timing analysis tool 32 using the information. Only errors can be detected. Also,
Since the logic verification uses the cycle-based simulator 22 having no timing verification, it is possible to verify the simultaneous output operation as a whole at high speed.

Next, another embodiment of the present invention will be described. FIG. 6 is a block diagram showing another embodiment of the simultaneous output operation verification system according to the present invention. In the figure, a timing analysis environment 4 receives circuit connection information 1 and a timing constraint condition from a timing constraint library 41, performs timing verification with a timing analysis tool 42, and stores the result in a memory as error information 43. . The cycle-based simulation environment 5 receives the circuit connection information 1 and the pattern information 51 from the memory together with the above-mentioned error information 43, performs a logical operation on a cycle-by-cycle basis with a cycle-based simulator 52, eliminates false paths, and detects the detection result. Is output as a true detection result 53,
Store in memory.

Also in this embodiment, the logic verification unit does not have a timing verification function.
2, the timing verification is performed by the static timing analysis tool 42, and information is exchanged between these individually existing verification functions, whereby high-speed and high-performance simultaneous output operation verification can be performed.

[0032]

As described above, according to the present invention,
Since the deterioration of the accuracy due to the cycle unit is eliminated by the timing analysis, and the false path is eliminated by the cycle-based simulator, a true verification result can be obtained with higher accuracy than in the past.

Further, according to the present invention, the logic verification is performed by the cycle-based simulator having no timing verification function, and the time required for the verification work is shortened because the manual verification of the pseudo error is unnecessary. Simultaneous output operation verification can be performed faster than in the past.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an embodiment of the system of the present invention.

FIG. 2 is a circuit diagram of an example of a logic circuit indicated by circuit connection information in FIG.

3 is a timing chart for explaining the operation of FIG. 2 and FIG.
It is explanatory drawing of the pattern information in a middle.

FIG. 4 is a flowchart for explaining the operation of FIG. 1;

FIG. 5 is an explanatory diagram of a verification result in FIG. 1;

FIG. 6 is a configuration diagram of another embodiment of the system of the present invention.

FIG. 7 is an explanatory diagram of an example of a conventional verification method.

[Explanation of symbols]

 1 Circuit connection information 2, 5 Cycle-based simulation environment 3, 4 Timing analysis environment 21, 51 Pattern information 22, 52 Cycle-based simulator 23, 43 Error information 31, 41 Timing constraint library 32, 42 Timing analysis tool 33, 53 True Detection result

Claims (6)

[Claims] 1. A cycle based on circuit connection information of a logic circuit whose time difference between signal changes at a plurality of output terminals is to be verified and pattern information including a time difference between output signals of predetermined output terminals of the logic circuit. A logic verification result obtained by performing a logic operation in a cycle unit by the base simulator is used as error information, and the error information, the circuit connection information, and the timing constraint condition of the logic circuit are input to a timing verification tool, and the timing verification is performed. A simultaneous output operation verification method, characterized in that a verification result obtained by performing an analysis considering a timing by a tool is output as a true verification result. 2. A timing verification tool performs analysis in consideration of timing based on circuit connection information of a logic circuit whose time difference between signal changes at a plurality of output terminals is to be verified and timing constraint conditions of the logic circuit. Inputting the error information, the circuit connection information, and the pattern information including the time difference between the output signals of the predetermined output terminals of the logic circuit into a cycle-based simulator; And outputting a logic verification result obtained by performing a logic operation in cycle units as a true verification result. 3. The timing constraint condition according to claim 1, wherein a time difference between signal changes at a plurality of output terminals of the logic circuit is an error when the time difference between the signal changes is equal to or less than a predetermined value. 2. The output simultaneous operation verification method according to 2. 4. A circuit connection information of a logic circuit for which a time difference between signal changes at a plurality of output terminals is to be verified, and pattern information including a time difference between signal changes at a plurality of output terminals of the logic circuit. A cycle-based simulator that outputs, as error information, a logic verification result obtained by performing a logic operation in cycle units based on the input information of the above, a first storage unit that temporarily stores the error information, and a timing constraint of the logic circuit. A library storing conditions in advance, the circuit connection information, the error information from the first storage means, and the timing constraint condition from the library as inputs, and a timing based on the input information. A timing verification tool that outputs a verification result obtained by performing analysis in consideration of Simultaneous output operation verification system, characterized in that it comprises a second storage means for holding a true verification result output from the timing verification tool. 5. A library preliminarily storing timing constraint conditions of a logic circuit whose time difference between signal changes at a plurality of output terminals is to be verified, circuit connection information of the logic circuit, and the timing constraint from the library. A timing verification tool that receives conditions as inputs and performs analysis in consideration of timing based on the input information; a first storage unit that temporarily stores verification results by the timing verification tool as error information; Receiving as input the error information from the storage means, the circuit connection information, and the pattern information including the time difference between the output signals of the predetermined output terminals of the logic circuit, and performing a logic operation in cycle units of the input information. A cycle-based simulator for outputting the obtained logic verification result as a true verification result; Simultaneous output operation verification system, characterized in that it comprises a second storage means for holding a true verification result output from the simulator. 6. The timing constraint condition is a condition that an error occurs when a time difference between signal changes at a plurality of output terminals of the logic circuit is equal to or less than a certain value. 5. The simultaneous output operation verification system according to 5.