JP2906684B2 - Motion detection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a motion detecting apparatus used for detecting a motion vector in, for example, high-efficiency coding of moving image data.

[0002]

2. Description of the Related Art For example, in highly efficient coding of moving image data,
A motion detection device is used for detecting a motion vector and the like. In such a motion detection device, the operation is performed by a first stage for detecting one pixel (one pel) with accuracy, and a first stage for detecting the accuracy of one pixel.
It is divided into a second stage for detecting 5-pel (half-pel) accuracy. As such a motion detecting device, the present inventor has previously proposed a device for performing one-pel accuracy detection by so-called full search block matching (Japanese Patent Application No. 3-10551). An apparatus for detecting half-pel accuracy after detecting such one-pel accuracy has also been proposed (Japanese Patent Application No. 3-143).
No. 10).

That is, in these devices, 1-pel accuracy detection is performed, for example, for each pixel in the reference data block for each correspondence state of pixels that can be taken by the reference data block of g × p pixels within the search range of e × f pixels. And the sum of absolute differences between the pixel and the corresponding pixel in the search range is calculated, and the position of the block of g × p pixels at which the sum is minimized is detected. On the other hand, when half-pel accuracy is detected, the average value between adjacent pixels is compared with the pixels in the reference data block, and for each corresponding state with the pixels in the reference data block. The sum of absolute differences is obtained.
Here, when the above-described one-pel accuracy detection is performed, the periphery of the block of g × p pixels detected by the half-pel accuracy detection is expanded by one pixel (g + p).
2) The operation may be performed on (p + 2) pixels.

Therefore, when these devices are connected to constitute a device that performs detection up to half-pel accuracy, for example, in the above-described proposed device, detection of one pel accuracy is detected by processing of g × p cycles. And can perform real-time processing. However, in the detection with half-pel accuracy, (g + 2) × (p + 2) cycles are required to perform the processing. Therefore, when this processing is also performed in real time, the processing speed of the device for detecting the half-pel accuracy must be increased to (g + 2) × (p + 2) / g × p times, and a special device is required. In addition, complicated circuit devices have to be provided for transferring image data.

[0005]

The problem to be solved is that, when a device is connected to perform detection up to half-pel accuracy, the processing speed of some devices must be increased as it is. In addition, a special device is required, and a complicated circuit device must be provided for transferring image data.

[0006]

According to the present invention, a pixel within a search range constituted by a predetermined number of pixels and a pixel in a first reference data block constituted by a number of pixels smaller than the predetermined number of pixels are provided. Are compared with each other based on the arrangement state, the first reference data is set for each corresponding state of pixels that can be taken by the first reference data block (input terminal 1) within the search range (input terminal 4). First calculating means (a motion detecting circuit 3 with one-pel accuracy) for calculating the sum of absolute differences between each pixel in the block and a corresponding pixel in the search range, and a motion of one pixel or less in the search range When detecting the state, the average value between adjacent pixels (RAMs 17a and 17b) is compared with the pixels in the second reference data block (delay circuit 22). For each correspondence state with pixels Second arithmetic means for forming as further obtain a sum of absolute difference (half-pel precision motion detection circuit 2
1) the number of pixels of the second reference data block
With the number of processing cycles in the second arithmetic means
Wherein the number of pixels (4 × 4) is smaller than the number of pixels (6 × 6) of the first reference data block so as to be equal to the number of processing cycles in the calculating means. .

[0007]

According to this, the number of pixels of the second reference data block is set to be smaller than the number of pixels of the first reference data block. Can be made equal to the number of processing cycles in the calculating means, and the problems of processing speed and image data transfer can be solved, and half-pel accuracy can be detected with a simple configuration.

[0008]

FIG. 1 shows the structure of the apparatus. Here, a case where the search range is 11 × 11 pixels and the reference data block is 6 × 6 pixels is described as a specific example, but this is of course generalized (search range e × f pixels, reference data block g × p Pixel).

In FIG. 1, an input terminal 1 has, for example, 36 pixels a _I (I) of a reference data block as shown in FIG.
= ₀ to ₃₅ ) are sequentially input from a0. Each of the input pixels a _I is stored in the 36-stage shift register 2 and then supplied to the 1-pel precision motion detection circuit 3.

The input terminal 4 receives pixels in the search range (one frame before) in the order shown in FIG. 3A, for example. Each pixel from the input terminal 4 is supplied to the input D of the motion detection circuit 3 and is also supplied to the input C of the motion detection circuit 3 through the delay circuit 5 for a 36-cycle period. Each pixel from the input terminal 4 is supplied to the input B of the motion detection circuit 3 through the delay circuit 6 for 6 horizontal periods, and further to the input A of the motion detection circuit 3 through the delay circuit 7 for 36 cycle periods. . Accordingly, each pixel is input to the motion detection circuit 3 as shown in FIG. If the search range is 11 × 11 pixels, the shaded B ₅ ... B
_{35, C 30 ~C 35, D} 5 each pixel of the ··· D ₂₉ ~C ₃₅ is searched
The data is out of the range, and is regarded as dummy data .

As a result, the motion detection circuit 3 performs motion detection with one-pel accuracy. That is, the motion detection circuit 3 is provided with, for example, 36 difference absolute value calculation circuits and accumulation circuits, and a comparison circuit for comparing these accumulated values.
Each pixel A _K to D depending on the value of _K sigma supplied to the values and input A~D of each pixel a _I supplied from the shift register 2 above | X _K -a _I | (where, X = A ~ D, K, I = 0 ~ 3
5) is calculated, and a 1-pel precision motion vector (i, j) in which the accumulated value is minimized is detected. The detected 1-pel precision motion vector (i, j) is stored in the latch circuits 8 to
The signal is output to the output terminal 11 of the integer part of the motion vector through 10.

On the other hand, each pixel from the delay circuit 5 is supplied to the contact D of the changeover switch 12 and further supplied to the contact C of the changeover switch 12 through the delay circuit 13 for 36 cycles. Each pixel from the delay circuit 7 is supplied to the contact B of the changeover switch 12, and
Change-over switch 12 through cycle period delay circuit 14
Is supplied to the contact A. Further, the detected motion vector (i, j) with one pel accuracy is supplied to the control circuit 15 through the latch circuit 8, and the switch 12 is switched to the contacts A to D by a signal from the control circuit 15. Thereby, for example, each pixel A _{K to} D _K as shown in FIG. 4A is extracted from the changeover switch 12 in the order of the suffix in accordance with the motion vector (i, j).

Further, the motion vector (i, j) with one pel accuracy from the latch circuit 8 is supplied to the memory control circuit 16, and the write address (WA) formed by the control circuit 16 has a storage capacity of 36 words. RA with
M17a and 17b. This allows RAM1
Each of the addresses 7a and 17b has a pixel A extracted from the changeover switch 12 in the order of the suffix (A in FIG. 4).
_K to D _K is written as shown respectively. Also one
Reference numeral 8 denotes a ring counter that outputs a value from 0 to 35,
The values from the ring counter 18 are stored in the RAMs 17a and 17a.
b is supplied to the read address (RA). This RAM17a, from 17b, the pixels A _K to D _K written is fetched in the order of suffixes as pixel A _'K as shown in B of FIG. The switches 19, 2
0 is for switching the banks of the RAMs 17a and 17b every 36 cycles to alternately perform read / write operations so that continuous processing can be performed.

[0014] Each pixel A _'K retrieved from the switch 20 is supplied to the motion detection circuit 21 of the half-pel precision. Each pixel a _I of the reference data block passed through the shift register 2 is supplied to a delay circuit 22 for a 72-cycle period.
And a motion detection circuit 21 with half-pel accuracy through a delay circuit 23 for a period of 7 cycles. Further, the motion vector (i, i,
The residual S when j) is detected is stored in the latch circuits 24 and 25.
To the motion detection circuit 21 with half-pel accuracy.

[0015] This is shown in Figure 5 in the 36 pixel a _I of the motion detection circuit 21, the reference data block I = 7
Motion detection with half-pel accuracy is performed using 16 pixels of -10, 13-16, 19-22, and 25-28 as new reference data blocks. That is, the motion detection circuit 21 is provided with a subtraction circuit, eight average value calculation circuits, an absolute value calculation circuit and a cumulative addition circuit, and a comparison circuit for comparing the cumulative value and the residual S described above. Σ | (A ′ _K / 2) + (A ′ _{K *} / 2) according to the value of each pixel a _I supplied from the shift register 2 and the value of each pixel A ′ _K extracted from the switch 20. ) −a _I | (where K, I = 7 to 10, 13 to 16, 19 to 22,
25 to 28, K * is a value in eight directions around K), and a half-pel precision motion vector in which the value of the accumulated value and the value of the residual S are minimized is detected. The detected half-pel precision motion vector is output to the output terminal 27 of the decimal part of the motion vector through the latch circuit 26.

FIG. 6 shows an overall time chart.
Here, A is a value input to the input terminal 1, B to E are values supplied to the inputs A to D of the motion detection circuit 3, and F is a 1-pel precision motion vector (i , J), G to J are values supplied to the terminals A to D of the switch 12, K is a value extracted from the delay circuit 22 for a 72-cycle period, and L is extracted from the latch circuit 25.
Residuals S and M when a pel-accurate motion vector (i, j) are detected are values taken out from the switch 20, N is an integer part of the motion vector taken out to the output terminal 11, and O is taken out to the output terminal 27. This is the fractional part of the motion vector.

FIG. 7 shows a time chart between the switches 12 and 20. Here, A to D in the figure are values supplied to the terminals A to D of the switch 12, and when the switch 12 is controlled by a signal from the control circuit 15, for example, It is taken out of the switch 12. E is a write address (WA) supplied to the RAMs 17a and 17b.
AM17a, input 17b is written to each address, the value of such A _'K as shown in G is formed. The value of the A _'K is taken from the switch 20 in the order of the suffix.

According to the above-described apparatus, the number of pixels of the second reference data block (delay circuit 22) is smaller than the number of pixels of the first reference data block (input terminal 1). The number of processing cycles in the second calculating means (the motion detecting circuit 21 with half-pel accuracy) can be made equal to the number of processing cycles in the first calculating means (the motion detecting circuit 3 with one-pel accuracy). It is possible to solve the problem of transfer of image data and perform half-pel accuracy detection with a simple configuration.

That is, according to the above-described apparatus, the number of processing cycles of the first calculating means (the motion detecting circuit 3 with one-pel accuracy) and the second calculating means (the motion detecting circuit 21 with half-pel accuracy) are both 36 cycles. And half-pel accuracy can be detected in real time.

FIG. 8 is a conceptual diagram of the above-described device.
For example, a first reference data block of 6 × 6 pixels supplied to input terminal 1 and 11 × 11 supplied to input terminal 4
The search range of the pixel is supplied to the 1-pel precision motion detection circuit 3, and a 1-pel precision motion vector is detected. Further, 6 × 6 pixels corresponding to the 1-pel precision motion vector detected by the motion detection circuit 3 are included in the search range (shown by hatching in the RAM.
17a and 17b) are supplied to the motion detection circuit 21 with half-pel accuracy. In the motion detection circuit 21 with half-pel accuracy, among the pixels from the delay circuit 22, 4 × 4 pixels indicated by oblique lines are used as second reference data. A motion vector with half-pel accuracy is detected as a block. Then, the detected one-pel precision and half-pel precision motion vectors are taken out to the output terminals 11 and 27.

In the above example, the search range is 11 × 11
The case where the pixels and the first reference data block are 6 × 6 pixels has been described. For example, the search range can be generalized to e × f pixels and the reference data block to g × p pixels. In the above-described apparatus, the 1-pel precision motion detection circuit 3 and the half-pel precision motion detection circuit 21
The present invention is not limited to the device proposed by the inventor of the present application, but can be applied to any device.

[0022]

According to the present invention, the number of pixels in the second reference data block is made smaller than the number of pixels in the first reference data block. Can be made equal to the number of processing cycles in the first arithmetic means, and the processing speed and the transfer of image data can be eliminated, and half-pel accuracy can be detected with a simple configuration. .

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an example of a motion detection device according to the present invention.

FIG. 2 is a diagram showing a first reference data block.

FIG. 3 is a diagram showing a search range.

FIG. 4 is a diagram showing a search range of a second stage detected with one pel accuracy.

FIG. 5 is a diagram showing a second reference data block.

FIG. 6 is an overall time chart of the apparatus.

FIG. 7 is a time chart of a main part of the apparatus.

FIG. 8 is a conceptual diagram of a motion detection device according to the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Input terminal of reference data block 2 Shift register 3 1 Motion detection circuit of 1 pel accuracy 4 Input terminal of search range 5-7, 13, 14, 22, 23 Delay circuit 8-10, 24-26 Latch circuit 11 Motion vector Output terminal of integer part 12, 19, 20 Changeover switch 15 Control circuit 16 Memory control circuit 17a, 17b RAM 18 Ring counter 21 Half-pel precision motion detection circuit 27 Output terminal of decimal part of motion vector

Claims (1)

(57) [Claims] 1. A method according to claim 1, wherein a pixel in a search range composed of a predetermined number of pixels and a pixel in a first reference data block composed of a number of pixels smaller than the predetermined number of pixels are arranged based on their arrangement state. At the time of comparison, the absolute value of the difference between each pixel in the first reference data block and the corresponding pixel in the search range is determined for each corresponding state of the pixels that can be taken by the first reference data block in the search range. A first calculating means for calculating the sum of the above, and when detecting a motion state of one pixel or less in the search range, an average value between adjacent pixels is compared with a pixel in a second reference data block. And a second calculating means for obtaining a sum of absolute difference values for each corresponding state with the pixels in the second reference data block. Number the second
The number of processing cycles in the arithmetic means is
Motion detecting apparatus characterized by small consisting number of pixels than the number of pixels in the first reference data blocks to equal the number of processing cycles and the.