JP2865131B2 - Data transfer method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an apparatus for performing pre-read at the time of DMA read access.

[0002]

2. Description of the Related Art Generally, a peripheral controller which controls a peripheral device and is connected to an I / O bus reads and writes data from and to a main storage device by using a DMA means. It is. Data reading from the peripheral controller is performed using DMA read processing. DMA
In the read processing, an address and a required data amount are sent to the upper bus, and this is transmitted to the main storage device, and as a result, data is returned from the main storage device.

In the DMA read operation, there is a first method in which the bus between the I / O bus and the main storage device is occupied from when a read request is issued until data is returned. Also, after issuing a request, the bus is released once, another request is accepted, and when data is sent from the main storage device, an I / O adapter connecting the I / O bus and the main storage device is connected to the I / O adapter. There is a second method for securing the O bus and returning data to the request source.

[0004] In both of the above methods, the time from issuing a request until the requested data is returned is I
There is a problem that it can be realized only over twice the data transfer time between the / O bus and the main storage device (the round-trip time).

To solve this problem, Japanese Patent Laid-Open Publication No. 2-110
A method such as that described in 646 has been proposed. In this method, the I / O adapter has a look-ahead function,
In this method, when a certain DMA read request is received, data of a subsequent portion of the request is read out (referred to as prefetch).

[0006]

However, even with this method, the read request is issued every time, so that the busy rate (occupancy rate) on the I / O bus decreases, but the main storage device and the I / O bus are not connected. The busy rate between buses higher than the bus cannot be reduced, which is not sufficient as a measure for improving performance.

In order to fully exploit the effect of prefetch, it is necessary to mount a buffer in the I / O adapter in consideration of the access time between the I / O bus and the main storage device. The longer the access time between the storage devices, the more buffers need to be provided.
There is a problem that (hardware) is increased.

In view of the above problems, a main object of the present invention is to reduce the bus busy rate between an I / O bus and a main storage device as compared with the conventional prefetch method, and to improve data performance. To provide a transfer method.

Another object of the present invention is to provide a data transfer system capable of reducing the amount of HW by suppressing the buffer in the I / O adapter.

[0010]

A data transfer system according to the present invention comprises a peripheral controller for controlling peripheral devices such as a CPU, a main storage device and a disk, a data transfer between the CPU and the peripheral controller, and a data transfer between the peripheral controller and the peripheral controller. A data processing device having an I / O adapter for performing data transfer between main storage devices, wherein a subsequent I / O adapter is provided in the I / O adapter based on a read access (hereinafter referred to as a DMA read) generated from the peripheral controller. Predict that there is a DMA read, fetch the predicted data from the main memory before a real DMA read request from the peripheral controller, and fetch if the real request comes from the peripheral controller. Data processing having a pre-reading function of returning the stored data to the peripheral controller. In the apparatus, the I / O adapter includes a buffer for receiving data from the main storage device at the time of preceding reading, and a DMA read / write access to the main storage device generated from the peripheral controller (hereinafter, referred to as a DMA write). Means for returning data to the peripheral controller from the buffer when the data corresponding to the request is stored in the buffer at the time of DMA read, and data corresponding to the request at the time of DMA read. Means for determining whether the read request is likely to perform continuous data transfer when the data is not stored in the buffer, and performing the preceding read when it is determined that there is continuous access. Transfer request for preceding read based on DMA read from peripheral controller Means for issuing a write request to a specific address to which the main storage of the main storage device is not allocated in order to perform the transfer to the main storage device, wherein the main storage device When a write request is received, data transfer is performed from the address requested to the requesting I / O adapter at regular time intervals, and
In the case where a transfer stop instruction from the / O adapter or a break such as a page boundary of data is detected, a data transfer control mechanism having means for stopping data transfer is provided, thereby enabling advance reading.

The data transfer control mechanism has means for instructing a data transfer time interval to the I / O adapter by setting from the I / O adapter, and can perform data transfer at a specified time interval.

[0012] The data transfer control mechanism also includes the DM
When a plurality of data transfer control mechanisms for performing data transfer by the A-write operation are provided, there is provided a means for generating a busy flag indicating that data transfer is being performed, and a request is dynamically allocated to the data transfer control mechanism which is free. Can be controlled.

The data transfer control mechanism may further comprise a plurality of data transfer control mechanisms owned by the main storage controller, wherein all data transfer control mechanisms are processing data transfer, and the request cannot be accepted. And a means for notifying the I / O adapter of an unacceptable state, so that it is possible to suppress the occurrence of a write request for preceding reading.

[0014] The data transfer control mechanism may further include, after the request becomes unacceptable in the main storage control device, an instruction to stop the data transfer that has been executing the process.
O means for detecting the end of data transfer when there is an O-adapter, or when the data transfer which has been processing by detecting a page boundary has been stopped. By notifying the I / O adapter that the request can be accepted, the preceding read operation can be restarted.

The I / O adapter includes a plurality of buffer mechanisms so that a plurality of DMA read requests generated when the plurality of peripheral controllers are connected via an I / O bus can be received in parallel. A means for generating a prefetch flag indicating that the buffer mechanism is performing a preceding read; a means for searching for an empty buffer mechanism when a request from the I / O bus is generated and dynamically allocating to the empty buffer mechanism. However, it is possible to perform data transfer for the preceding reading.

The I / O adapter further includes means for detecting that the data sent from the main memory control device is not discharged to the peripheral controller but is stored in the buffer mechanism and becomes full, A means for notifying the control device of the suspension of the data transfer can be provided to temporarily stop the preceding reading function.

The I / O adapter further includes means for returning data from the buffer to the peripheral controller by a DMA read from the peripheral controller, and detecting that a buffer in the I / O adapter has become empty.
It has means for notifying the main storage device that data reception has become possible, and it is possible to restart interrupted data transfer.

The I / O adapter further comprises means for holding which of the peripheral controllers is performing the pre-read processing of the DMA read, and when the DMA read requests sent from the same peripheral controller are not continuous, Requests other than DMA read request (DMA
Write, etc.) has been issued, and after the detecting means determines that the preceding read process is invalid,
It has means for discarding the data held in the I / O adapter and instructing the main storage control device to stop data transfer, and can stop the preceding reading process without delay.

The I / O adapter further comprises means for instructing the main storage controller to stop data transfer, and thereafter discarding data transmitted until data transfer from the main storage device is completed. However, the next preceding reading process can be performed without delay.

[0020]

According to the present invention, the conventional DMA function can be used under the control of the I / O bus, and the I / O adapter and the main storage device are connected to the I / O bus in the same manner as the prefetch system.
The data transfer time as viewed on the O bus is shortened, while the bus busy rate between the I / O bus and the main storage device is suppressed to improve the performance as compared with the conventional prefetch method. Since the number of buffers can be reduced to half, the HW amount can be reduced.

[0021]

Preferred embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows an overall configuration diagram. The CPU 3, the main storage device 2, and the I / O adapter 1
It is connected via a processor bus 5. The peripheral controller 4 and the I / O adapter 1 are connected via an I / O bus 6. A plurality of I / O adapters 1 can be connected to the processor bus 5, and a plurality of peripheral controllers 4 can be connected to the I / O bus 6. In some cases, the I / O adapter 1 is connected in multiple stages, but here, for simplicity of description, only one stage is used.
In a multistage connection, any function according to the present invention may be provided.

The peripheral controller 4 has a DMA processing function. The DMA processing function in the peripheral controller 4 operates according to an instruction from the CPU 3, issues a data transfer request to the I / O bus 6, and issues a data transfer request. Perform a transfer. I /
The O adapter 1 includes a request receiving unit 10 that receives all requests generated from the I / O bus 6, a buffer mechanism 11 that performs control related to preceding reading, and a processor bus processing unit 15 that performs processing of the processor bus 5. The description of the other parts is omitted.

The buffer mechanism 11 has a request management unit 12 for managing a request relating to the preceding read processing, a buffer unit 14 for storing the preceding read data, and a buffer management unit 13 for managing the state of the buffer.
Referring to FIG. 2, the request management unit 12 issues a continuous transfer check unit 121 that determines whether or not continuous transfer is possible, a request processing unit 122 that controls advance read, and issues a request for advance read to the main storage device 2. It has a request conversion unit 120 for controlling, and a prefetch flag generation unit 123 for generating a prefetch flag indicating that pre-read processing is being performed.

The buffer management unit 13 includes a data discarding unit 131 for controlling data discarding after the end of prefetch. The request processing unit 122 includes an I / O bus 6
A data processing unit 126 that discharges data, a preceding reading holding unit 125 that retains various data associated with preceding reading, detection of temporary suspension of preceding reading, and accompanying a preceding reading to the data transfer control mechanism 23 Request suspension and resumption notification unit 124 for notifying the suspension or resumption of data transfer, transfer end detection unit 127 for detecting the end of preceding reading, and data transfer control mechanism 2 for notifying the transfer end.
3 has a transfer end notifying section 127 for notifying the transfer end.

The main storage control device 20 in the main storage device 2
It has a request receiving unit 21 for receiving a request via the processor bus 5, a data transfer control mechanism 23 for controlling data transfer for preceding read processing, and the like. The request receiving unit 21 has a function of identifying whether the request is an access to the main storage space or a data transfer request, and if the request is for a normal main storage device, sends the request to a normal request processing unit 22 that processes the request. . On the other hand, the data transfer control mechanism 23 includes a request processing unit 230 that processes the received request, a timer unit 231 that counts the timing of data transfer, and a busy flag generation unit 232 that generates a busy flag indicating that the preceding reading process is being performed. Further, the request receiving unit 21 includes a request refusal notifying unit 24 which detects that the preceding read request cannot be received and notifies the request.

Next, a description will be given in order from a place where a DMA read or a DMA write occurs from the peripheral controller 4.

1) All requests from the peripheral controller 4 are received by the request receiving unit 10 of the I / O adapter 1. The request receiving unit 10 is a peripheral controller 4
The request received from the processor bus 5 is checked, and if the request is a DMA write request, the received request is sent to the processor bus processing unit 15 to issue the request to the processor bus 5 as it is.

On the other hand, in the case of a DMA read request,
Information such as the address and transfer length of the received read request, the state of the prefetch flag, and the request processing unit 1
Then, the data information transmitted from the preceding read holding unit 125 and currently held by the preceding read mechanism is checked. If the prefetch flag indicates that the address is being read ahead and the address of the received request corresponds to the address or the like that is being read ahead, the request information is sent to the request processing unit 122 of the buffer mechanism 11.

The data discharge processing unit 126 of the request processing unit 122 confirms whether the corresponding data is stored in the buffer unit 14 based on the received request and information from the buffer management unit 13. When the data corresponding to the DMA read request is stored in the buffer unit 14, the data ejection processing unit 126 of the request processing unit 12 performs a data transmission process. In the data transmission processing, the corresponding data block in the buffer
The data is transmitted to the O bus 6 to update the data information held therein. However, if the data has not yet been stored in the buffer unit 14, it waits for the data to arrive from the main storage device 2. The arrival of data is notified from the buffer management unit 13 to the data ejection processing unit 126 of the request processing unit 122.

However, if the request reception unit 10 is performing the preceding read processing, but the received address or the like does not match the information of the preceding read processing, the preceding read processing cannot be performed. This is sent to the processor bus processing unit 15.

On the other hand, when receiving a request from the peripheral controller 4 and receiving from the prefetch flag that the preceding read process is not operating, the request receiving unit 10 sends the received request to the continuous transfer checking unit 121. . The continuous transfer check unit 121 determines the possibility of performing continuous data transfer from information such as the address and data transfer length of the received request, and
If it is determined that there is a possibility of continuous data transfer, the request conversion unit 120 is instructed to issue a write request to a specific address of the main memory control device 20, and the prefetch flag is set to a state of pre-read processing, and Information related to the prefetch is stored in the preceding read holding unit 125.

If it is determined that there is no possibility of continuous data transfer, the request is sent to the processor bus processing unit 15 because the received request is issued to the processor bus 5 as it is. The request converter 120 generates a write request for data transfer of the preceding read. In the write request, the start address to be transferred, the transfer unit (how many bytes should be sent), and the transfer time interval (how long the transfer unit should be sent) are stored as data. It is sent to a specific address of the main storage control device 20.

The request receiving unit 21 in the main storage control unit 20 identifies whether the received request is an access to the main storage space or a data transfer request. The request is sent to the normal request processing unit 22 that processes the request. On the other hand, if the request is a data transfer request, the received request is sent to the data transfer control mechanism 23. Request processing unit 23 in data transfer control mechanism 23
0 reads data in the main memory from the given address and starts transfer. The amount of data to be sent at one time is I /
It is determined based on the information sent from the O adapter 1. 1
The data divided into transfer units is transmitted to the data transfer control mechanism 2
3 is sent to the I / O adapter 1 at regular intervals by using a timer unit 231 for designating a transfer interval held by the I / O adapter 1. As the timer value, the information sent from the I / O adapter 1 is set in the timer of the timer unit 231 when the request is received.

The data sent from the main storage device 2 to the I / O adapter 1 is registered in the buffer unit 14 of the I / O adapter 1 when the data is identified as data obtained by preceding reading. The buffer management unit 13 detects that data has been registered, and notifies the data ejection processing unit 126 of the request processing unit 122 of data arrival. Request processing unit 1
The data discharge processing unit 126 returns the requested data to the peripheral controller 4.

The end of the preceding read processing is checked by the buffer mechanism 11 of the I / O adapter 1 and the data transfer control mechanism 23 of the main storage controller 20, respectively. I /
Transfer end detection unit 1 of buffer mechanism 11 in O adapter 1
The transfer end detection condition at 27 is when the data position sent from the main storage device 2 has reached the page boundary, when the DMA read request from the peripheral controller 4 that has issued the request is not continuous, This is the time when another operation is performed, and is detected by the transfer end detection unit 127. After the detection, the transfer end detecting unit 127 requests the transfer end notifying unit 127 to transmit the stop to the main storage device 2 to notify the main storage device 2 of the stop of the precedent read in the case of performing the precedent read under the end condition other than the page boundary. Then, the transfer end notification unit 12
7 issues a request to stop the pre-read process.

The data transfer end detection unit 233 of the main memory control device 20 performs data transfer when the data transfer stop instruction is received from the I / O adapter 1 or when the address of the data to be transferred detects a page boundary boundary. The data transfer ends when an end condition is detected.

2) Next, a case where the data transfer control mechanism 23 in the main storage control device 20 and the buffer mechanism 11 in the I / O adapter 1 are not formed by the same number will be described. For example,
This is a case where the number of buffer mechanisms 11 of the I / O adapter 1 is larger than that of the data transfer control mechanism 23 of the main storage control device 20. In this case, the data transfer control mechanism 23 of the main storage control device 20
Is managed by providing a busy flag generating unit 232 for generating a busy flag for notifying the request receiving unit 21 whether or not the device is currently controlling data transfer.

The request receiving unit 21 constantly monitors information being processed from the data transfer control mechanism 23, and when there is a free space in the data transfer control mechanism 23, the data transmitted from the I / O adapter 1 The transfer request is notified to the vacant data transfer control mechanism 23. At this time, if there is a vacancy in the plurality of data transfer control mechanisms 23, control is performed so that the data transfer control mechanisms 23 are allocated from the weakest number.

When the data transfer control mechanism 23 provided in the main storage control unit 20 detects that all data transfer control is being performed, the request refusal notification unit 24 in the request reception unit 21 of the main storage control unit 20 outputs Using the dedicated line, the I / O adapter 1 is notified that data transfer cannot be accepted.

Next, the request receiving unit 21 performs I / O
If the request received from the adapter 1 is to instruct data transfer suspension, the address transmitted from the I / O adapter and the transfer suspension are transmitted to all data transfer control mechanisms. Data transfer control mechanism 2 that received the information
3 is to compare the received address with its own address and, if the transfer area matches, stop the data transfer being performed and cancel the data transfer by releasing the busy flag to the request receiving unit 21 To communicate.

The data transfer control mechanism 23 performs the same processing when the designated data transfer is completed. The request refusal notification unit 24 of the request reception unit 21 that has detected the release of the busy flag notifies the I / O adapter 1 that the exclusive line has been released and data transfer reception is enabled.

A request from the peripheral controller 4 generated during a period in which data transfer accompanying the preceding read cannot be performed is as follows:
The I / O adapter 1 processes the request as a normal request without performing the preceding read processing.

3) The following is a case where a plurality of buffer mechanisms 11 are provided in the I / O adapter 1. In this case, the buffer mechanism 1 is provided to the request receiving unit 10 in the I / O adapter 1.
A signal indicating whether or not the prefetch flag in 1 is performing the preceding read processing is used. Request reception unit 1
When 0 accepts a DMA read, the state of each buffer mechanism is checked as described above. if,
If there is a free instruction from the buffer mechanism 11, the received request is sent to the free buffer mechanism 11. If all the buffer mechanisms 11 are in operation and the received DMA read request does not correspond to any of the preceding read processing, the request receiving unit 10 sends the request to the processor bus processing unit 15 as it is. Send out.

4) The data sent from the main storage controller 20 to the I / O adapter 1
1 is stored in the buffer unit 14. However, when there is a difference in transfer performance between the I / O bus 6 and the main storage device 2, the buffer unit 14 may become full. Therefore, the fact that the buffer unit 14 has become full due to the data sent from the main storage control device 20 is determined by the buffer management unit 1.
If No. 3 is detected, the buffer full is notified to the request suspension / resumption notification unit 124 of the request processing unit 122.

The request suspending / resuming notifying unit 124 of the request processing unit 122 notified of the buffer full
The main storage controller 20 is notified via the processor bus 5 which buffer (transfer) is full. The request receiving unit 21 of the main storage control device 20 that has received the notification instructs the data transfer control mechanism 23 to interrupt the data transfer. The data transfer control mechanism 23 suspends the data transfer when receiving the suspension instruction. Naturally, data may be sent before the request reaches the data transfer control mechanism 23, so the buffer full state takes this into account.

If a DMA read request is issued from the peripheral controller 4 after instructing the above interruption, the request is similarly sent to the buffer mechanism 11 and the corresponding data portion corresponding to the request is sent to the peripheral controller 4.
Send back to Buffer unit 1 in response to sending back
In step 4, the buffer full state is released. The buffer management unit 13 that has detected the release of the buffer full state requests the request suspension / resumption notification unit 124 to send an instruction to resume data transfer from the main storage control device 20 due to the release of the buffer full state.

In response to the request, the request suspending / resuming notifying section 124 of the request managing section 12 instructs the main storage control device 20 to resume data transfer. In the request receiving unit 21 of the main storage control device 20 that has been notified,
It instructs the data transfer control mechanism 23 to restart data transfer. The data transfer control mechanism 23 restarts the data transfer when receiving the restart instruction.

5) The I / O adapter 1 is a buffer mechanism 1
In order to detect the end of the data transfer using No. 1, a function of sequentially monitoring the status of the incoming DMA read request is provided. This is realized by various functions of the request processing unit 122. For example, when the same peripheral controller detects that a DMA write or the like has been transmitted when the received DMA read request does not hold a continuous address as before, the transfer of the data stored in the buffer unit 14 is stopped. And the main memory control device 2
0 is instructed to stop. Accordingly, the request receiving unit 21 of the main storage control device 20 that has received the notification instructs the data transfer control mechanism 23 to stop the data transfer as described above.

Data transmission to the buffer unit 14 of the buffer mechanism 11 may be performed between the execution of the data transfer and the data transfer stop instruction. In order to avoid this, when data that has not been processed is received, the data discarding unit 131 of the buffer management unit 13 checks the data, prevents the data from being registered in the buffer unit 14, and immediately starts the next preceding reading. Can be done.

[0050]

As described above, according to the present invention, even when data is read prior to the DMA transfer in the data processing device, the performance can be improved by lowering the bus busy rate and the HW amount can be reduced. Is possible.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration for realizing the method of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 I / O adapter 2 Main storage device 3 CPU 4 Peripheral controller 5 Processor bus 6 I / O bus 10 Request reception unit 11 Buffer mechanism 13 Buffer management unit 14 Buffer unit 15 Processor bus processing unit 20 Main storage control device 21 Request reception unit Reference Signs List 22 Normal request processing unit 23 Data transfer control mechanism 120 Request conversion unit 121 Continuous transfer check unit 122 Request processing unit 123 Prefetch flag generation unit 210 Timer unit 232 Busy flag generation unit

Claims (10)

(57) [Claims] 1. A CPU (3), a main memory (2), a peripheral controller (4) for controlling a peripheral device such as a disk, data transfer between the CPU and the peripheral controller, and a peripheral controller and the main memory. A data processing device having an I / O adapter (1) for performing data transfer between the I / O adapter and a subsequent I / O adapter based on a read access (hereinafter, referred to as a DMA read) generated from the peripheral controller in the I / O adapter. Predict that there is a DMA read, fetch the predicted data from the main memory before a real DMA read request from the peripheral controller, and fetch if the real request comes from the peripheral controller. A data processing device having a pre-reading function of returning the stored data to the peripheral controller, / O adapter includes a buffer that receives the data from the main storage device at the time of preceding read (14), DM to said main memory generated from the peripheral controller
A read / write access (hereinafter referred to as DMA write) is identified, and when data corresponding to the request is stored in the buffer during DMA read, data is returned from the buffer to the peripheral controller. Means (126), and means (121) for identifying, in the DMA read, whether the read request is likely to perform continuous data transfer when data corresponding to the request is not stored in the buffer. And a main memory of the main storage device for performing a transfer request for the pre-reading based on the DMA read from the peripheral controller to the main storage device for performing the pre-reading when it is determined that there is a continuous access. Means (120) for issuing a write request to a specific address to which no The main storage device, when receiving a write request for a specific address, performs data transfer from the address requested to the requesting I / O adapter at regular time intervals, When a transfer stop instruction from the I / O adapter or a break such as a page boundary of data is detected,
A data transfer method characterized in that a data transfer control mechanism (20) having a means (230) for stopping data transfer enables advance reading. 2. The data transfer control mechanism according to claim 1, wherein:
2. The data transfer method according to claim 1, further comprising means (210) for designating a data transfer time interval to the adapter by setting from the I / O adapter, and performing data transfer at a specified time interval. 3. The data transfer control mechanism according to claim 2, wherein
When a plurality of data transfer control mechanisms for performing data transfer by a write operation are provided, a means (232) for generating a busy flag indicating that data transfer is being performed is provided, and a request is dynamically allocated to the data transfer control mechanism that is free. 3. The data transfer system according to claim 1, wherein the data transfer can be controlled. 4. In the data transfer control mechanism, all of the data transfer control mechanisms in the plurality of data transfer control mechanisms possessed by the main storage control device process data transfer, and the request cannot be accepted. 4. The data according to claim 3, further comprising: means for identifying the status by the busy flag; and notification means (24) for notifying the I / O adapter of an unacceptable state, so that generation of a write request for preceding reading can be suppressed. Transfer method. 5. The data transfer control mechanism according to claim 1, wherein, after the request becomes unacceptable in the main storage control device, an instruction to stop the data transfer being processed is issued to the I / O controller.
Means (233) for detecting the end of data transfer when there is an adapter, or when the data transfer that has been processed by detecting a page boundary has been stopped,
The notifying unit notifies the I / O adapter that the data transfer request can be accepted,
5. The data transfer method according to claim 4, wherein the preceding read operation can be restarted. 6. The I / O adapter includes a plurality of buffers for receiving a plurality of DMA read requests generated when the plurality of peripheral controllers are connected via an I / O bus. A mechanism and a means for generating a prefetch flag indicating that the buffer mechanism is performing a preceding read (123); searching for an empty buffer mechanism when a request from the I / O bus occurs; The data transfer method according to any one of claims 1 to 5, further comprising means (10) for allocating the data to the first memory. 7. The means for detecting that the data sent from the main memory control device is not discharged to the peripheral controller side but is stored in the buffer mechanism and becomes full. 7. The data transfer method according to claim 6, further comprising means (124) for notifying said main storage control device of a temporary stop of data transfer, and capable of temporarily suspending a preceding reading function. 8. The I / O adapter returns data from the buffer to the peripheral controller by a DMA read from the peripheral controller, and detects that a buffer in the I / O adapter has become empty. (1
3) The data transfer method according to claim 6, further comprising means (124) for notifying the main storage device that data reception is enabled, and capable of restarting the interrupted data transfer. 9. The I / O adapter has means (125) for holding which of the peripheral controllers is performing the pre-read processing of the DMA read, and the DMA read requests sent from the same peripheral controller are consecutive. If not, a means (127) for detecting that a request other than the DMA read request (such as a DMA write) has been issued is provided. And means for instructing the main storage control device to stop data transfer, so that the preceding reading process can be stopped without delay.
Data transfer method described. 10. The I / O adapter, after instructing the main storage control device to stop data transfer, discards data transmitted until data transfer from the main storage device is completed. 131. The data transfer method according to claim 9, wherein the data transfer method includes the following: 131), and the next preceding read processing can be performed without delay.