JP4941212B2 - Electronic device, data processing apparatus, and bus control method - Google Patents

Description

  The present invention relates to an electronic device, a data processing apparatus, and a bus control method, and more particularly, to an electronic device that transfers data through a bus, a data processing apparatus that transfers data through a common bus, and a bus control method.

In data transfer in a system in which a plurality of devices are connected to a common bus, anomaly detection due to timeout is generally used as a means for confirming whether or not a device to which data is transferred normally responds.
Generally, the time until a timeout is detected is specific to the system, and if there is no response from the device that is the data transfer partner by the time the timeout occurs, it is determined that the device or bus is abnormal. Then, abnormal termination processing such as system or bus reset is performed.

However, when multiple devices perform data transfer at the same time, the load on the bus increases, so the time until the response of the device that is the data transfer partner temporarily increases and a timeout is detected. There is.
In such a situation, there is a problem that an abnormal termination process such as a bus reset occurs due to the detection of timeout even though there is no abnormality in the device or the bus.

  Although it is possible to avoid the above problem by setting a long time until timeout detection, in this case, when the device does not respond normally due to a device failure, there is a problem that the detection of abnormality is delayed. .

  As a related technique for solving these problems, there is an information processing apparatus disclosed in Patent Document 1. The information processing apparatus includes a shared bus, a plurality of devices that issue a request signal through the shared bus, receive a response signal from the shared bus, perform processing, and a bus monitoring apparatus connected to the shared bus.

  The bus monitoring device monitors the traffic situation on the shared bus, obtains the bus usage rate from the traffic situation of the monitoring result, and changes the timeout detection time in each device accordingly.

JP 2001-22654 A (first page)

  However, the above-described information processing apparatus has a problem in that even when a failure occurs such that the bus is always used due to an abnormal operation of the device or the bus, the timeout time becomes long and the abnormality detection is delayed.

  An object of the present invention is to provide an electronic device, a data processing apparatus, and a bus control method that solve the above problems.

The electronic device of the present invention is
A bus transfer control unit that controls a common bus and performs data transfer with other electronic devices;
A timer for detecting a timeout for receiving a response from the electronic device of the data transfer partner;
A suspend control unit that receives the timeout detection and drives a common suspend signal to interrupt data transfer including other electronic devices;
A diagnostic control unit that transmits a command to the electronic device of the other party and determines whether or not there is a response to the command.

A data processing apparatus of the present invention is a data processing apparatus including a common bus and a plurality of electronic devices that perform data transfer with each other via the bus,
A common suspend signal line connecting the plurality of electronic devices;
The electronic device is
A bus transfer control unit for controlling the bus and performing the data transfer;
A timer for detecting a timeout for receiving a response from the electronic device of the data transfer partner;
A suspend control unit for receiving the timeout detection and driving the suspend signal to interrupt data transfer including other electronic devices;
A diagnostic control unit that transmits a command to the electronic device of the other party and determines whether or not there is a response to the command.

The bus control method of the present invention includes a bus transfer control procedure for controlling a bus and transferring data,
A procedure for detecting a timeout for receiving a response from the electronic device of the data transfer partner;
Upon receiving the timeout detection, a suspend control procedure for driving a common suspend signal and interrupting data transfer including other electronic devices;
A diagnostic control procedure for transmitting a command to the partner electronic device and determining whether or not there is a response to the command.

  According to the present invention, when a timeout is detected in bus data transfer, whether the cause is bus congestion (transfer resource competition on the bus) or an abnormality of the bus or a device connected to the bus. Judgment can be made promptly.

  Therefore, the abnormality of the bus or device is detected promptly, and an abnormal termination process such as abortion of data transfer or bus reset, which is erroneously performed with respect to a timeout due to bus congestion, can be avoided.

Next, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a block diagram showing a first embodiment of a data processing apparatus 10 of the present invention.
The data processing apparatus 10 includes a bus 1 and a bus request arbitration unit 8 that are common to the devices 11 to 61.

The devices 11 to 61 are connected to a common bus 1, and data transfer between the devices is performed via the bus 1.
The bus 1 performs data transfer in synchronization with a clock signal.
The bus request arbitration unit 8 receives a bus request from each of the devices 11 to 61, and if there are requests from a plurality of devices, selects a single request according to the priority order and returns permission to use the bus to that device.
The suspend signal line 7 is a signal line commonly connected to all devices, and a device that detects a timeout in data transfer performs assertion and deassertion of the suspend signal line 7.

  The bus 1 is, for example, a PCI bus including a PCI-X (Peripheral Component Interconnect-X) bus, a SCSI (Small Computer System interface) bus, or the like.

  The devices 11 to 61 are, for example, I / O devices, controllers such as I / O devices and cache memories, file devices, processors, and electronic devices such as bus bridges.

The devices 11 to 61 may be devices of different types or functions, or the same type.
Some of the devices 11 to 61 may be constituted by circuit boards. In this case, the device connection portion of the bus 1 includes a slot connector.

FIG. 2 is a block diagram showing an internal configuration of each device 11 to 61 connected to the bus 1.
The device 11 includes a bus transfer control unit 14, a suspend control unit 15, and a diagnosis control unit 16.
The bus transfer control unit 14 includes a bus control unit 12 that controls the bus 1 and a transfer control unit 13 that requests and performs data transfer. The bus transfer control unit 14 controls the bus 1 and performs data transfer.

  Similarly, the device 61 includes a bus transfer control unit 64, a suspend control unit 65, and a diagnosis control unit 66. The bus transfer control unit 64 includes a bus control unit 62 and a transfer control unit 63. Although not shown, each of the devices 21 to 51 includes each control unit in the same manner.

The bus control unit 12 normally performs normal data transfer via the bus 1 at the request of the transfer control unit 13, but interrupts data transfer in the suspended state in which the suspend signal line 7 is asserted.
In response to a request from the diagnosis control unit 16, the bus control unit 12 transmits a diagnosis command to the data transfer partner device 61 via the bus 1.

The diagnosis control unit 16 transmits a diagnosis command to the partner electronic device and determines whether or not there is a response to the diagnosis command.
That is, the diagnosis control unit 16 requests the bus control unit 12 to transmit a diagnosis command when the suspend signal line 7 is asserted.

When the device 61 receives the diagnostic command, the diagnostic command is notified to the diagnostic control unit 66 via the bus control unit 62, and the diagnostic control unit 66 transmits a diagnostic response (response to the diagnostic command) to the bus control unit 62. Request.
When the diagnosis control unit 16 normally receives a response to the diagnosis command, the diagnosis control unit 16 cancels the timeout and turns off the drive of the suspend signal line 7 via the suspend control unit 15.
The diagnosis control unit 16 instructs abnormal termination of data transfer that has timed out when a response to the diagnosis command cannot be received.

The suspend control unit 15 detects a data transfer timeout and drives the suspend signal line 7 to interrupt data transfer including other electronic devices.
That is, when the bus control unit 12 detects a data transfer timeout, the suspend control unit 15 drives and asserts the suspend signal line 7.
Further, the suspend control unit 15 detects that the suspend signal line 7 is asserted by its own device or another device, notifies the bus control unit 12 or the transfer control unit 13 and interrupts the data transfer.

Assume that the suspend signal line 7 is asserted and deasserted at a timing received by all the devices 11 to 61 within the same clock.
That is, all devices suspend data transfer being executed at the next clock timing when the suspend signal line 7 is asserted, and return to the suspended state at the next clock timing when the suspend signal line 7 is deasserted. The device for which the suspend control unit 15 has not instructed abnormal termination resumes data transfer.

  Although the devices 11 and 61 have been described above, the control units of the other devices 21 to 51 operate in the same manner.

  FIG. 3 is a block diagram showing a detailed configuration of the bus control unit 12 and the suspend control unit 15 of the device 11 and an interface between these control units and the transfer control unit 13 and the diagnosis control unit 16.

The bus control unit 12 includes a timer 121, a control circuit 123, a transmission register 125, a reception register 127, and a save storage unit 124.
The bus control unit 12 also includes a control signal driver 1281 for the bus 1, a control signal receiver 1282, a command signal line / data signal line driver 1283 for the bus 1, a command signal line / data signal line receiver 1284, and a selector 1261. And a selector 1262 and a selector 1271. The bus 1 is, for example, a PCI bus.

The timer 121 detects a timeout for receiving a response from the data transfer partner device.
That is, the timer 121 is set with, for example, a predetermined timer set value in accordance with a timer setting instruction from the control circuit 123, and thereafter counts down with a clock or a long-period timer clock. Keep state. Further, the device ID to be monitored is set in a register (not shown) different from the timer value register in the timer 121 by the timer set instruction.

This device ID is passed to the diagnosis control unit 16 when a timeout occurs.
The timer 121 is again set to a predetermined set value in response to a timeout cancel instruction from the diagnosis control unit 16, and the timeout output is turned off.

  The transmission register 125 is an 8.5-byte transmission register, and holds a command (4 bits), an address (4 bytes), and data (4 bytes) from the top.

  The selector 1261 switches the transfer command and address from the transfer control unit 13, the diagnosis command and address from the diagnosis control unit 16, and the restore data from the save storage unit 124, and inputs them to the command and address portion of the transmission register 125. A selection instruction is received from the control circuit 123.

  The selector 1262 inputs the address 4 bytes and the data 4 bytes of the transmission register 125 to the switching driver 1283.

The reception register 127 is an 8.5-byte reception register that receives a command (4 bits), an address (4 bytes), and data (4 bytes) from the upper level, and receives a request control unit (transfer control requesting read transfer). The received content is passed to the unit 13 and the diagnosis control unit 16) or the control circuit 123 that requested the diagnosis command.
However, if the request source control unit is busy, the contents of the reception register 127 are retained during that time.

  The selector 1271 inputs the received command and address and the restore data from the save storage unit 124 to the switching reception register 127.

When receiving a data transfer request from the transfer control unit 13, the control circuit 123 receives and processes the request if the suspend signal is off.
For example, if the request is a read command to another device 61, the control circuit 123 instructs the selector 1261 to select a transfer command and an address, and sets the selected command and address in the transmission register 125. The address includes a transmission destination device ID indicating the device 61 and a transmission source device ID indicating the device 11.
The control circuit 123 causes the selector 1262 to select an address.

  The control circuit 123 makes a bus request to the bus request arbitration unit 8, and when the bus permission to the device 11 is asserted, a signal line and a command signal line indicating that the command or address / data in the control signal is valid Address / data signal lines (contents are addresses) are driven by a driver 1281 or a driver 1283.

When the control circuit 123 receives an acceptance with a split notification from the device 61 through a control signal line or the like, the control circuit 123 deasserts the signal line indicating the validity and opens the bus.
Then, the control circuit 123 instructs the timer 121 to be set.

  For example, a predetermined timer set value and a device ID of the data transfer partner (device 61 ID) are set in the timer 121.

For example, if the request is a split response to another device 21, the control circuit 123 instructs the selector 1261 to select a transfer command (write) and an address, and sets the command, address, and response data in the transmission register 125. The bus is requested and transmitted in the same manner.
Further, the control circuit 123 selects and transmits response data with the selector 1262 after one cycle of transmission start.

When the suspend signal from the suspend control unit 15 is asserted, the control circuit 123 interrupts the data transfer operation. Acceptance of data transfer requests is suppressed.
If the suspend signal is asserted and the diagnostic transfer flag (not shown, but the control circuit 123 has an internal flag) is off, the bus request to the bus request arbitration unit 8, the control signal to the bus 1, the address / Suppress data signal transmission.

At the rising edge of the suspend signal, the control circuit 123 also suppresses the reception of the bus permission signal and the active control signal from other devices and the progress of processing immediately after the reception. The rise is for one cycle and is suppressed during this period.
At the rising edge, the control circuit 123 saves the command and address of the transmission register 125, the command and address of the reception register 127, and the contents of the transfer sequence counter (not shown) in the save storage unit 124.

When receiving a diagnostic command transmission request from the diagnostic control unit 16, the control circuit 123 accepts and processes this request if the suspend signal line 7 is in the asserted state.
Upon reception of the diagnostic command transmission request, the control circuit 123 clears the transfer sequence counter to the initial value, turns on the diagnostic transfer flag, and temporarily cancels suppression of bus requests and transmission to other devices. To do.

  The lock (inhibition) of the bus request and the gate that drives the control signal driver 1281 to the bus 1 is released, but since the transfer sequence counter is the initial value, the previously suppressed data transfer sequence is resumed. There is no.

Next, the control circuit 123 causes the selector 1261 to select the diagnosis command and address from the diagnosis control unit 16 and sets them in the command and address portion of the transmission register 125.
This address includes a transmission destination device ID (ID of the device 61) and a transmission source device ID (ID of the device 11).

  The control circuit 123 makes a bus request, and when the bus permission is asserted, transmits a diagnostic command to the device 61 of the transfer partner up to that time.

When receiving a diagnostic command from another device, the control circuit 123 checks whether the transmission destination (destination) device ID in the address of the reception register 127 matches its own device ID.
If the check circuit is addressed to the self device, the control circuit 123 passes the received diagnosis command to the diagnosis control unit 16 together with the transmission source device ID.

  When receiving a diagnostic response transmission request from the diagnostic control unit 16, the control circuit 123 performs the same process as the diagnostic command transmission.

  When the suspend signal from the suspend control unit 15 is deasserted, the control circuit 123 causes the contents of the save storage unit 124 to be transferred to the command and address portion of the transmission register 125, the command and address portion of the reception register 127, and transfer at the falling edge. Restore to the sequence counter. Then, the control circuit 123 cancels the suppression of the transmission and reception.

The suspend control unit 15 includes a flip-flop (F / F) 151, a driver 1531, a receiver 1532, and an inverter 1533.
The flip-flop 151 is a flip-flop with a set input and a reset input. When the time-out signal is asserted, the flip-flop 151 is set if the suspend signal line 7 is in a deasserted state, and its output makes the suspend signal line 7 in an asserted state. .
The flip-flop 151 is reset by a suspend reset instruction from the diagnosis control unit 16.
The output of the flip-flop 151 also indicates that it is a drive source device of the suspend signal line 7.

  If the suspend signal is asserted, the diagnosis control unit 16 requests the control circuit 123 to transmit a diagnosis command if it is the drive source device, and waits for a diagnosis response when the request is processed.

  The diagnosis control unit 16 receives a diagnosis response, for example, in the form of a diagnosis response command. If the diagnosis control unit 16 can normally receive the diagnosis response within a predetermined short period, the diagnosis control unit 16 instructs time-out cancellation and then instructs the flip-flop 151 to be reset. As a result, the timeout output of the timer 121 is turned off, and the suspend signal line 7 is also deasserted.

If the diagnosis control unit 16 cannot receive the diagnosis response normally, the diagnosis control unit 16 instructs the suspend control unit 15 to perform a suspend reset, causes the bus control unit 12 to return to the state immediately before the suspend, and then terminates the data transfer that timed out abnormally. The process is instructed to the transfer control unit 13.
The transfer control unit 13 receives an instruction for abnormal termination processing, designates the received device ID, and instructs the device 61 via the bus control unit 12 to terminate the transfer.

Next, the operation of the first exemplary embodiment of the present invention will be described with reference to the drawings.
The operation when the device 11 attempts to read data from the device 61 after the device 21 shown in FIG. 1 starts data transfer with the device 31 and the device 41 starts data transfer with the device 51 will be described as an example. To do.

Assume that each data transfer between devices is performed in a split transaction in which a data transfer request and a response (actual data transfer) are separated. For example, the device 21 requests a bus and obtains a bus permission, designates the device 31 to request reading and requests it, the device 31 responds with a reception with a split notification, and the device 21 immediately turns off the request and turns on the bus. Is released.
Whenever the device 31 can prepare the data, it requests the bus and acquires the bus permission, designates the device ID of the device 21 and transmits the data.

4 and 5 are sequence charts showing the operation of the first embodiment of the data processing apparatus 10 of the present invention.
Referring to FIG. 4, device 21 and device 31 start a transfer operation between devices via bus 1 (step 1). Next, the devices 41 and 51 start a transfer operation between the devices via the bus 1 (step 2).

  Next, the device 11 acquires the bus, designates the device 61 and transmits a reading instruction (step 3-1), and the device 61 responds with reception with split notification (step 3-2). The device 11 releases the bus, enters a response data waiting state, and sets the timer 121 (step 3-3).

When device 61 is ready for data, it requests a bus for a response, but the bus request is rejected. That is, a state in which the bus request of the device 51 enters in synchronism with the bus request by the device 31 or a cycle in which the bus is not used occurs, and the bus request reception priority of the device 61 is the lowest. Permission is not asserted for a long time (step 4).
For this reason, the device 61 cannot transfer the response data, and the device 11 detects a read transfer timeout (step 5).

The device 11 that has detected the timeout sets the flip-flop 151 to drive the suspend signal line 7 to be asserted (step 6).
Further, the devices 11 to 61 detect that the suspend signal line 7 is asserted, immediately stop the data transfer being executed, suppress the bus request and transmission, and release the bus 1. The devices 11 to 61 also save, in the save storage unit 124, information on registers overwritten by the transfer for diagnosis, among the state information at the time of data transfer interruption (step 7).

At the start of the diagnostic transfer operation, the device 11 initializes the sequence state of the data transfer and then temporarily cancels the bus request and transmission suppression.
The device 11 transmits a diagnostic command to the device 61 via the bus 1 (step 8), and the device 61 receives the diagnostic command (step 9).

The device 61 that has received the diagnostic command initializes the sequence state of the data transfer at the start of the diagnostic transfer operation, and then temporarily cancels the bus request and transmission suppression.
The device 61 transmits a diagnostic response to the device 11 (step 10), and the device 11 receives the diagnostic response from the device 61 (step 11).

When the device 11 receives the diagnostic response normally, it is determined that the timeout has occurred due to congestion of the bus 1 (transfer resource contention on the bus 1), cancels the timeout (step 12), and drives the suspend signal line 7. Turn off (step 13).
The devices 11 to 61 detect the deassertion of the suspend signal line 7, restore the state saved in step 7, and resume the interrupted data transfer (step 14).

  Eventually, the data transfer between the device 21 and the device 31 is completed (step 15), the device 61 acquires the bus and transmits the read data (step 16), and the device 11 receives the read data (step 17) and ends the operation. To do.

  Further, if the device 11 fails to normally receive the diagnostic response from the device 61 in step 11 within a predetermined short period after issuing the diagnostic command in step 8, it means that an abnormality has occurred in the bus 1 or device 61. Considering abnormal termination processing such as aborting data transfer.

In the above description, the configuration of the timer 121 is assumed to hold the timer value and the device ID corresponding to the timer 121 for convenience of explanation and illustration, but actually, a plurality of sets of timer values and device IDs corresponding thereto are held. .
Accordingly, even when the device 11 sequentially transmits a data transfer command to a plurality of devices as counterparts and performs parallel processing, the time monitoring can be performed.

  Further, although the example in which the bus control unit 12 includes the timer 121 has been described, there is also an example in which the transfer control unit 13 includes.

  In the first embodiment of the present invention, when time-out is detected without increasing the time monitoring time from the beginning, data transfer is interrupted, a diagnostic command is transmitted to the partner device, and a response can be received normally. Whether the bus is congested or abnormal is determined. If the bus is congested, transfer is resumed.

  Therefore, according to the first embodiment of the present invention, the abnormality of the bus 1 or the devices 11 to 61 is quickly detected, and the transfer abortion that is erroneously performed with respect to the timeout due to the congestion of the bus 1 is detected. Abnormal termination processing such as bus reset can be avoided.

  In addition, when sending and receiving diagnostic commands and responses to the partner device that has timed out, the transmission registers 125, reception registers 127, and control circuit 123 around the drivers 1281 and 1283 and receivers 1282 and 1284 connected to the bus 1 The same means as for data transfer is used, and the cause of timeout can be determined with high accuracy.

Next, a second embodiment of the present invention will be described in detail with reference to the drawings. FIG. 6 is a block diagram showing a detailed configuration of the second embodiment of the devices 11 to 61 of the present invention.
In the second embodiment, the functions and configurations of the bus control unit 12 and the diagnosis control unit 16 of the devices 11 to 61 are partially different from those in the first embodiment.

  In other words, in the first embodiment, the bus control unit 12 also performs transmission / reception of diagnostic commands and transmission / reception of diagnostic responses. In the second embodiment, the bus control unit 12A performs transmission / reception of these commands. Absent. Instead, the diagnosis control unit 16A performs these transmissions and receptions.

The diagnostic control unit 16A shares the drivers 1281 and 1283 and the receivers 1282 and 1284 connected to the bus 1 with the bus control unit 12A, but performs a diagnostic transfer operation without affecting the interrupted data transfer state. .
Therefore, 2-way selectors 1263, 1287, and 1289 (selection circuits) are inserted on the input side of the driver for the transmission signal to the bus 1 and the bus request signal to the bus request arbitration unit 8.
A data transfer signal from the inside of the bus control unit 12A and a diagnostic transfer signal from the diagnosis control unit 16A are switched and input to these.

  In addition, two-output selective repeater circuits 1285, 1286, and 1288 are inserted into the outputs of the receivers 1284 and 1282 of the received signal from the bus 1 and the receiver (not shown) of the bus permission signal from the bus request arbitration unit 8, respectively. The output is distributed to the inside of the bus control unit 12A and the diagnosis control unit 16A.

The bus control unit 12 </ b> A does not include the save storage unit 124, the selector 1261, and the selector 1271 provided in the bus control unit 12.
The request source of the control circuit 123A is only the transfer control unit 13.

However, a selector 1289, a selector 1287, and a selector 1263 are inserted into the bus request signal input, the control signal driver 1281 input side, and the driver 1283 input side, respectively.
In addition, a suspend reception signal received by a flip-flop is input to these selectors as a selection signal. The selectors 1289, 1287, and 1263 select the bus request D, the control signal D, and the command and address D that are inputs from the diagnosis control unit 16A if the selection signal is on, and the bus control unit if the selection signal is off. Select input from within 12A.

  Also, a repeater circuit 1288, a repeater circuit 1286, and a repeater circuit 1285 are inserted on the output side of the receiver 1282 for the bus permission signal and the control signal and on the output side of the receiver 1284 for the command and address / data signals, respectively.

These repeater circuits 1285, 1286, and 1288 are selective repeaters, and only a part thereof is shown, but a suspend signal is input as a selection signal.
If the selection signal is ON, the input signal is transmitted to the output to the diagnosis control unit 16A, and the output to the bus control unit 12A is not driven.

  On the contrary, if the selection signal is OFF, the input signal is transmitted to the output to the inside of the bus control unit 12A, and the output to the diagnosis control unit 16A is not driven.

  When the suspend signal is asserted, the diagnosis control unit 16A requests the bus after one or two cycles if the driving source signal is on, acquires the bus, and transfers the diagnostic command via the bus 1.

When a diagnostic command whose destination device ID in the address information is its own device ID is received via the bus 1, a diagnostic response is transmitted to the source device of this command.
The diagnosis control unit 16 </ b> A that has transferred the diagnosis command waits for a diagnosis response and receives it through the bus 1. Other operations of the diagnosis control unit 16A are the same as those in the first embodiment.

Next, the operation as the data processing apparatus 10 of the second embodiment will be described.
In the process of step 7 in the sequence chart of FIG. 5, the data transfer state is not saved.
In step 8, the device 11 transmits a diagnostic command to the device 61 via the bus 1 without initializing the data transfer sequence state and temporarily canceling the bus request and transmission suppression.

In step 10, the device 61 transmits a diagnostic response to the device 11 via the bus 1 without initializing the data transfer sequence state and temporarily canceling the bus request and transmission suppression. In step 14, when the devices 11 to 61 detect the deassertion of the suspend signal, the data transfer is resumed without performing the state restoration.
Operations other than those described above are the same as those in the first embodiment.

  According to the second embodiment of the present invention, as in the first embodiment, an abnormality is detected quickly, and an abnormal termination process that is erroneously performed with respect to a timeout due to the congestion is avoided. it can.

  Further, since the save storage unit 124 and the circuit for saving and restoring the state are not required, the second embodiment is more suitable for the device in which the state information to be overwritten by the transfer for diagnosis becomes larger. Less additional hardware.

The present invention can also be applied to a data processing apparatus in which any of the devices 11 to 61 includes a bus bridge, and the bus bridge is also connected to the second bus.
That is, if the bus bridge relays the suspend signal line 7 in addition to the existing relay function to the suspend signal line of the second bus, the device 11 detects the timeout of the response from the device on the second bus. In this case, similarly, the data transfer is interrupted, and it can be determined whether it is abnormal or the bus is congested by the response to the diagnostic command, and the data transfer is resumed when it can be regarded as the bus congestion.
The device ID is a device ID including the bus ID in the upper bits, and the bus bridge has a first port connected to the bus 1 and a second port connected to the second bus.
Then, if the destination ID indicates the second bus, the first port takes in the command and transmits it to the device corresponding to the device ID of the destination ID through the second port.

It is a block diagram which shows the structure of 1st Embodiment of the data processor 10 of this invention. It is a block diagram which shows the internal structure of each device 11-61 in 1st Embodiment of the data processor 10 of this invention. 2 is a block diagram illustrating a detailed configuration of a bus control unit 12 and a suspend control unit 15 of the device 11 and an interface between the control unit, the transfer control unit 13 and the diagnosis control unit 16 in the first embodiment of the present invention. FIG. It is a sequence chart which shows the whole operation | movement in the 1st Embodiment of this invention. It is a sequence chart which shows the whole operation | movement in the 1st Embodiment of this invention. It is a block diagram which shows the structure of each control part of the device 11 in the 2nd Embodiment of this invention.

Explanation of symbols

1 Bus 7 Suspend signal line 8 Bus request arbitration unit 10 Data processing device 11, 21, 31, 41, 51, 61 Device 12, 12A, 62 Bus control unit 13, 63 Transfer control unit 14, 64 Bus transfer control unit 15, 65 Suspend control unit 16, 16A, 66 Diagnosis control unit 121 Timer 123, 123A Control circuit 124 Save storage unit 125 Transmission register 127 Reception register 151 Flip-flop 1261, 1262, 1263, 1271 Selector 1281, 1283, 1531 Driver 1282, 1284, 1532 Receiver 1285, 1286, 1288 Repeater circuit 1287, 1289 Selector 1533 Inverter

Claims (14)

A bus transfer control unit that controls a common bus and performs data transfer with other electronic devices;
A timer for detecting a timeout for receiving a response from the electronic device of the data transfer partner;
A suspend control unit that receives the timeout detection and drives a common suspend signal to interrupt data transfer including other electronic devices;
An electronic device comprising: a diagnosis control unit that transmits a command to the electronic device of the other party and determines whether or not there is a response to the command. The diagnostic control unit cancels the timeout when receiving a response to the command and stops driving the suspend signal, and instructs the abnormal end of the timed-out data transfer when the response to the command cannot be received. The electronic device according to claim 1. With an evacuation storage,
The bus transfer control unit saves the state at the time of interrupting the data transfer from a register to the save storage unit, receives driving stop of the suspend signal, and restores the information of the save storage unit to the register. The electronic device according to claim 2. A part of the data transfer state at the time of the interruption, the register information to be overwritten for the designation of the command, the partner electronic device or the transmission of a diagnostic response, is saved in the save storage unit The electronic device according to claim 3. A selection circuit that selects a bus control signal from each of the bus transfer control unit and the diagnosis control unit according to a state of the suspend signal, and drives a driver of the bus by its output;
A diagnostic control unit that generates the command and controls and transmits the bus;
3. The electronic device according to claim 2, wherein bus transfer of the command and a response to the command is performed using the diagnosis control unit and the selection circuit. A data processing apparatus including a common bus and a plurality of electronic devices that transfer data to each other via the bus,
A common suspend signal line connecting the plurality of electronic devices;
The electronic device is
A bus transfer control unit for controlling the bus and performing the data transfer;
A timer for detecting a timeout for receiving a response from the electronic device of the data transfer partner;
A suspend control unit for receiving the timeout detection and driving the suspend signal to interrupt data transfer including other electronic devices;
A data processing apparatus comprising: a diagnostic control unit that transmits a command to the electronic device of the other party and determines whether or not there is a response to the command. The diagnostic control unit cancels the timeout when receiving a response to the command and stops driving the suspend signal, and instructs the abnormal end of the timed-out data transfer when the response to the command cannot be received. The data processing apparatus according to claim 6. The electronic device includes an evacuation storage unit;
The bus transfer control unit saves the state at the time of the data transfer interruption from the register to the save storage unit, receives driving stop of the suspend signal, and restores the information of the save storage unit to the register The data processing apparatus according to claim 7. The save storage unit saves information of a register that is a part of the data transfer state at the time of interruption and is overwritten for designating the command, the partner electronic device, or transmitting a diagnostic response. The data processing apparatus according to claim 8. The electronic device is
A selection circuit that selects a bus control signal from each of the bus transfer control unit and the diagnosis control unit according to a state of the suspend signal, and drives a driver of the bus by its output;
A diagnostic control unit that generates the command and controls and transmits the bus;
8. The data processing apparatus according to claim 7, wherein bus transfer of the command and a response to the command is performed using the diagnosis control unit and the selection circuit. A bus transfer control procedure for controlling the bus and transferring data;
A procedure for detecting a timeout for receiving a response from the electronic device of the data transfer partner;
Upon receiving the timeout detection, a suspend control procedure for driving a common suspend signal and interrupting data transfer including other electronic devices;
A bus control method comprising: a diagnostic control procedure for transmitting a command to the electronic device of the other party and determining whether or not there is a response to the command. When the diagnostic control procedure receives a response to the command, it cancels the timeout and stops driving the suspend signal, and when the response to the command cannot be received, instructs the abnormal termination of the timed-out data transfer The bus control method according to claim 11, wherein: 13. The bus transfer control procedure saves a state at the time of interruption of the data transfer from a register, receives a suspension of driving of the suspend signal, and restores information in the save storage unit to the register. The bus control method described. Saving the data transfer state is a part of the data transfer state at the time of the interruption, and saves the information in the register that is overwritten for the designation of the command or the partner electronic device or the transmission of a diagnostic response. The bus control method according to claim 13, wherein:

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