JP2719226B2 - Information processing system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a means for supplying a clock to each circuit in an information processing system having a plurality of semiconductor integrated circuits operated by clocks, And a method of controlling an operation clock.

[Prior Art] In an information processing system including a plurality of semiconductor integrated circuits according to the related art, as shown in FIG. 6, a method of supplying a clock to each of the semiconductor integrated circuits 16, 36, and 46 is different from each other. A clock having a frequency required in the semiconductor integrated circuits 16, 36, 46
63, and supplied via clock lines 110 to 112 on a printed circuit board on which the semiconductor integrated circuits 16, 36, and 46 are mounted.

As another prior art, as shown in FIG.
In a semiconductor integrated circuit having a U (Central Processing Unit), a phase locked loop circuit 66 (hereinafter, also referred to as a PLL) is provided in a semiconductor integrated circuit 76 as described in Japanese Patent Application Laid-Open No. 64-62023. Some of them generate a stable clock.

[Problems to be Solved by the Invention] The above-described prior art shown in FIG.
In order to use the clock supplied from the outside as it is as the internal operation clock as the clock used in the semiconductor integrated circuits 16, 36, 46 such as 6, 46, the speed of the semiconductor integrated circuits 16, 36, 46 At least one clock generation circuit 61, 62, 63 corresponding to the performance is required, and there is a problem that the system cost is increased.

Also, since the clock sources of the CPU 16 and the I / O controllers 36 and 46 are different, when the CPU 16 accesses the I / O controllers 36 and 46, the I / O controllers 36 and 46 are asynchronously accessed and the timing loss for synchronization is lost. This causes a problem that the performance of the system is deteriorated.

Further, since the clocks input to the I / O controllers 36 and 46 are supplied from the external clock generation circuits 62 and 63 via the wiring patterns (clock lines 111 to 114) on the printed circuit board, the clocks are high. In the case of the frequency, there is a problem that a large amount of radio interference noise is generated from the wiring pattern to which the clock is transmitted.

In the prior art shown in FIG. 7, one PLL is provided in one semiconductor integrated circuit, and each functional block (CPU
17, the same clock is sent to the memory 27 and the I / O controllers 37 and 47), so the above-mentioned problem does not occur. However, when there are a plurality of such semiconductor integrated circuits,
The above-mentioned problem occurs. However, no consideration has been given to this problem.

An object of the present invention is to provide an information processing system having a plurality of semiconductor integrated circuits, in which timing loss for synchronization is reduced and the performance of the system is improved.

Means for Solving the Problems To achieve the above object, the present invention provides, in an information processing system, a semiconductor integrated circuit having a plurality of PLLs (phase locked loops) and a clock signal supplied to the PLL. A clock generation circuit, and each of the semiconductor integrated circuits operates by a clock signal output from a PLL included in the semiconductor integrated circuit, and synchronizes a signal from another circuit with a clock signal output from the PLL. It has a circuit.

[Operation] The clock signal from the clock generation circuit is input to the PLL provided in each semiconductor integrated circuit, and the PLL receives the clock signal according to the frequency division ratio of the frequency divider inside the PLL based on the clock signal. A clock signal having a frequency multiplied by the clock signal is output.

Accordingly, since each circuit is synchronized with the clock signal of another circuit, the optimal timing setting can be performed in each circuit with respect to the access control signal from the other circuit, and the circuit scale of the synchronous circuit can be reduced.

Further, since the built-in phase locked loop circuit can generate a clock signal of a multiplied frequency, a multiplied clock signal can be selected as a clock signal of each semiconductor integrated circuit.

Also, even if the frequency of the external clock signal is set to a low frequency so that a large amount of electromagnetic noise does not occur from the wiring pattern existing on the printed circuit board, the clock signal of the required frequency is required inside each semiconductor integrated circuit. Can be generated.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a configuration diagram of an information processing system described in the present invention. In this system, a CPU 1, a memory 2, and I / O controllers 3 and 4, each of which has a different target I / O device, include: Independent semiconductor integrated circuits 7 to 10
Mounted on

Each of the semiconductor integrated circuits 7 to 10 is connected to a clock line 11 for transmitting a clock signal generated by an external clock generation circuit 6 and a control bus 12 for transmitting control information and the like between the semiconductor integrated circuits. Is done.

The control bus 12 selects a circuit for the CPU 1 to change the frequency,
This is a means for outputting a control signal for controlling the output frequency to the selected circuit.

Each of the semiconductor integrated circuits 7 to 10 incorporates, for example, a phase locked loop circuit (PLL) 5 in addition to a functional block circuit such as a CPU.

A clock signal input to the circuit 5 from the external clock line 11 is converted to a predetermined frequency by the phase locked loop circuit 5 according to control information transmitted from the CPU 1 through the control bus 12.

Then, the obtained clock signal is supplied to the functional block circuits requiring the clock signal in each semiconductor integrated circuit via the internal clock lines 131 to 134.

Note that in the case where a circuit that does not require a clock signal is included, supply of the clock signal to the circuit is unnecessary. For example, regarding the memory 2, depending on the type of the memory,
Some clock signals are unnecessary, and therefore, the supply of the clock signal by the phase locked loop circuit need not be performed.

FIG. 2 is a configuration diagram of a phase locked loop circuit mounted in each semiconductor integrated circuit.

This figure shows the case of the PLL 5 mounted on the semiconductor integrated circuit 7, but the PLL 5 mounted on the other semiconductor integrated circuits 8 to 10
PLL5 has a similar configuration.

The clock signal supplied via the clock line 11 is input to the phase comparator 16, where the input signal and the frequency dividing circuit
Compare the output with the 15 outputs and filter the output signal with a low-pass filter.
The output signal of the low-pass filter 17 is input to a voltage-controlled oscillator (VCO) 18.

The clock signal 131 output from the VCO 18 is
The frequency is divided by the frequency division ratio set by the control information from the CPU 1 and input to the phase comparator 16.

As described above, the phase-locked loop circuit mounted in each semiconductor integrated circuit has a frequency dividing circuit inside, and the frequency dividing ratio can be freely controlled, so that the frequency of the output clock signal is generated by the clock generation. It is possible to set a frequency that is a multiple of the clock signal generated by the circuit 6.

 Next, the frequency dividing circuit will be described.

FIG. 5 is a configuration diagram of a programmable frequency divider that can perform 1/2, 1/3,... 1/8 frequency division using a flip-flop that changes at the rising edge of an input clock signal.

Here, 20, 21, and 22 are for 1/2 frequency division, and 23 is used for signal latch.

Only the circuit selected by the CPU as the frequency change target is at the “H” level, and the control bus input terminal 26 receives a signal corresponding to the frequency to be set to the control bus input terminals 205, 215, and 225 at that time.

The control bus input terminal 26 is a signal obtained by decoding an address signal output from the CPU by a decoder. In this way, a circuit for changing the frequency is arbitrarily selected.

The input clock signal to this circuit is input as the clock signal of the first-stage flip-flop 20, and the flip-flops 21 and 22 thereafter use the inverted output Q of the previous stage as the clock input. The D input terminals of the flip-flops 20 to 22 each have their own inverted output or the control bus input terminals 205, 215, 225
, Or one of them is selected according to the level of the signal from the control bus input terminal 26.

The outputs of all the frequency-dividing flip-flops 20 to 22 are output from this frequency-dividing circuit after their logical product (AND) is obtained, and are output from the clock output terminal 25.

In this circuit, the normal dividing operation is performed when the signal from the control bus input terminal 26 is at the “L” level, but by setting this signal to “H”, writing for setting the dividing ratio is performed. It becomes possible, and frequency division from 1/2 to 1/8 is performed according to the level of the signal from the control bus input terminals 205, 215, and 225.

As described above, when the frequency is changed by the control signal from the CPU, for example, a plurality of CPs are stored in one information processing system.
If there is a U and the frequency of the clock signal of the CPU differs depending on the CPU, the frequency of the clock signal of a circuit other than the CPU can be changed according to the CPU.

 Next, the timing gloss will be described.

FIG. 3A shows a conventional control signal synchronization circuit for performing access between blocks operating asynchronously,
FIG. 3 (B) shows a timing chart thereof.

In the master / slave type flip-flops 19a and 19b shown in FIG. 3A, the control signal flowing through the control bus 120, which is a part of the control bus 12, is the rising edge of the clock signal 110 (flowing through the clock line 11). To enter the master flip-flop 19a. The slave flip-flop 19b receives the output (flows through the signal line 121) from the master flip-flop 19a at the rise of the clock signal flowing through the clock line 111, and outputs a synchronized control signal (flows through the signal line 122).

The slave flip-flop 19b is for avoiding the meta-stable state of the output of the master flip-flop 19a. In the synchronous circuit used in the conventional system, the clock signal 110 is used as shown in FIG. Since the phase difference Δφ exists between the control signal flowing through the signal line 120 and the control signal flowing through the signal line 120, the control signal flowing through the synchronized signal line 122 lags the original signal flowing through the signal line 120 by a maximum of 1.5 clocks. there is a possibility.

On the other hand, FIG. 4A shows a control signal synchronizing circuit according to the present invention, and FIG. 4B shows a timing chart thereof.

FIG. 4 shows a synchronization circuit provided inside the I / O controller A3. The same applies to the synchronization circuit provided inside the memory 2 and the I / O controller B4.

As shown in FIG. 4B, since the control signal flowing through the signal line 120 is synchronized with the clock signal input through the clock line 133, there is almost no phase difference.
What is necessary is to use the NOT gate 13 to take in at the edge delayed by half a clock.

The synchronized control signal obtained on the signal line 123 thus obtained is uniformly 0.5 times the original signal flowing on the signal line 120.
Just by delaying by the clock, the timing loss can be reduced as compared with the case where the master / slave flip-flop is used.

In addition, the synchronization circuit itself is a master as shown in FIG. Since there is no need to use a slave flip-flop, the circuit can be simplified.

The present invention is configured as described above, and has the following effects.

A phase-locked loop circuit is embedded in a semiconductor integrated circuit such as multiple I / O controllers, and a low-speed clock from the only clock generation circuit in the system or a low-speed clock signal from the CPU is provided in each semiconductor integrated circuit. Based on this, the PLL outputs a clock signal of any frequency as well as the same frequency with respect to the input clock signal by changing the division ratio of the frequency divider inside the PLL based on this. I do.

Therefore, even if the frequency of the external clock signal is set to a low frequency so that a large amount of electromagnetic noise is not generated from the wiring pattern existing on the printed circuit board, the clock signal of the required frequency is required inside each semiconductor integrated circuit. Can be generated.

Therefore, radio interference noise due to the clock signal can be prevented.

Further, since a clock signal of a multiplied frequency can be generated by the built-in phase locked loop circuit, a multiplied clock signal can be selected as a clock signal in each semiconductor integrated circuit.

Also, since it is synchronized with the clock signal of other circuits,
Optimal timing can be set in each circuit for access control signals from other circuits, and at the same time, the circuit scale of the synchronous circuit can be reduced.

Further, since a clock signal synchronized with each functional block is used, timing loss at the time of access between circuits is reduced, and a circuit for synchronization is simplified.

Further, since a clock signal corresponding to the speed performance can be supplied to each semiconductor integrated circuit based on a reference clock signal from a single clock generation circuit, only one clock generation circuit is required, and the system cost can be reduced.

[Effects of the Invention] According to the present invention, in an information processing system having a plurality of semiconductor integrated circuits, a timing loss for synchronization can be reduced, and an information processing system with improved system performance can be provided.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an information processing system showing an embodiment of the present invention, FIG. 2 is a configuration diagram of a phase locked loop shown in FIG. 1, and FIG. 3 is a conventional control signal synchronization circuit and its related circuit. FIG. 4 is an explanatory diagram of a timing chart, FIG. 4 is an explanatory diagram of a synchronous circuit and a timing chart thereof in the present invention, and FIG.
The figure shows the configuration of the two frequency dividers shown in FIG.
FIG. 7 is a configuration diagram of a conventional information processing system. DESCRIPTION OF SYMBOLS 1 ... CPU, 2 ... Memory, 3/4 ... I / O controller, 5 ... Phase locked loop circuit, 7-10 ... Semiconductor integrated circuit, 15 ... Division circuit, 16 ... Phase comparator , 17 ... low-pass filter, 18 ... voltage-controlled oscillator.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Ryutaro Hotta 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside Microelectronics Device Development Laboratory, Hitachi, Ltd. (72) Kenichi Hase Inventor Kenichi Haseda 292, Hitachi, Ltd. Microelectronics Equipment Development Laboratory (56) References JP-A-60-262232 (JP, A) JP-A-63-268020 (JP, A) JP-A-58-184626 (JP, A) JP-A-59-110227 (JP, A)

Claims (2)

(57) [Claims] A functional block circuit for performing information processing;
A plurality of semiconductor integrated circuits each having a PLL (Phase Locked Loop) circuit for generating an operation clock signal for the function block circuit; and a clock generation circuit for supplying an original clock signal to each of the PLL circuits. A control bus connecting the functional block circuits of the semiconductor integrated circuits, and a clock line connecting the PLL circuits and the clock generation circuit and supplying an original clock signal from the clock generation circuit to each PLL circuit. Wherein each of the semiconductor integrated circuits has a synchronization circuit for synchronizing a signal from another circuit with a clock signal output from a PLL circuit, and a functional block circuit in at least one of the semiconductor integrated circuits. Is a CPU (Central Processing Unit), and the CPU arbitrarily selects a semiconductor integrated circuit from other semiconductor integrated circuits and selects the selected semiconductor Included in the product circuit
The PLL circuit has means for outputting a control signal for controlling the output frequency of the PLL circuit. The PLL circuit transmits the frequency of the clock signal to be output via the control bus to the control signal from the CPU. An information processing system characterized by having means for setting according to the condition. 2. The information processing system according to claim 1, wherein the synchronization circuit transmits a control signal from the control bus to the control circuit.
An information processing system comprising means for inverting a clock signal supplied from the PLL circuit and capturing the inverted clock signal at an edge of a clock signal uniformly delayed by 0.5 clock.