JPH0693216B2 - Information processing equipment - Google Patents

Description

The present invention relates to an information processing device and an information processing system controlled by a clock signal, and is particularly suitable for shortening the clock cycle for speeding up. The present invention relates to an information processing device and an information processing system.

[Conventional technology]

A first conventional example of information processing controlled by a clock signal is shown in FIG. Reference numeral 201 is a clock oscillator that sends out the original clock signal 211, and 202 is a clock generator that receives the original clock signal 211 and generates the clock signal 212 necessary to control the logic units 203-206. Also, 213 is clock 2
It is an interface means between the logic devices whose timing is controlled by 12.

The clock 212 for controlling the logic device is usually a multi-phase clock of 2 to 4 phases each having a different phase. Examples of this clock are shown in FIGS. 4, 5, and 6. What is shown in FIG. 4 is called a non-overlap two-phase clock, and it is a clock having sections t ₁ and t ₂ both of which are at a low level. In addition, FIG.
It is an overlap clock with a duty of 50%, which is 90 degrees out of phase. Further, FIG. 6 is a four-phase clock with a short width, which is out of phase with each other by approximately 90 degrees. These clocks are selected according to the circuit format of the logic circuit that constitutes the logic device or the design method of the logic device.

These polyphase clock signals are generated by the clock generator 202 based on the clock 211 and distributed to each logic device. No clock signal processing is performed within the logic unit. Data exchange between the logic devices is performed in synchronization with the clock signal 211.

FIG. 3 shows a second conventional example of an information processing apparatus using a clock signal. 301 and 302 are clock oscillators, 3
11,312 are original clock signals, 303 and 304 are clock signals 311,3
The information processing unit 313 controlled by 12 is the information processing unit 303.
And an interface signal between the information processing unit 304 and the information processing unit 304. This information processing apparatus is composed of two information processing units, and each information processing apparatus has a separate clock oscillator 301, 30.
Have two. Processing the original clock signal,
As shown in FIGS. 5 and 6, a clock generator for generating a multiphase clock signal is provided in each information processing unit. Data exchange between the information processing units 303 and 304 is performed asynchronously through the interface 313.

7 to 9 show a third conventional example of an information processing apparatus controlled by a clock signal. For this method, see IEE, Journal of Solid State Circuit, SC 17, (1
982) pp. 51-56 (IEEE Jaurnal of Solid-State
Circuits vol SC-17, PP51-56).

FIG. 7 is an overall view. Reference numeral 701 is an oscillator for transmitting the clock signal 711, and 702 is a frequency divider for dividing the clock signal 711 by N. The information processing units 703 and 704 receive both the clock signal 711 and the clock signal 712. The interface between both processing units is 713.

FIG. 8 shows the internal configuration of the information processing unit 703. Reference numeral 801 denotes a PLL (Phase lock lo) that delays the clock signal 711 so as to have a specific phase relationship with the clock signal 712.
op) circuit. The PLL circuit 801 sends out a clock signal 811 which controls the logic device 802. On the other hand, the clock signal 712 is
As described above, it is a clock divided by 1 / N of the clock 711, and controls the interface circuit 803. That is, the logic unit inside the information processing unit
The low-speed clock 712 controls the communication between the information processing units, which are controlled by 711 and require time for signal propagation.

When two types of clock signals are used as shown in FIG. 8, a problem called metastability occurs with respect to data exchange between the interface circuit 803 and the logic device 802. This will be described with reference to FIG.
Consider the case where data is sent from the interface circuit 803 to the logic device 802. It is assumed that an edge trigger type flip flop is used for the interface. In the interface circuit 803, when the clock signal 712 rises from the first potential level Low to the second potential level High, data is taken in from the interface 713 and the data is sent to the logic circuit 802 through the signal 812. To be done. On the other hand, the logic device 802 takes in the transmitted data when the clock signal 811 rises from low to high. If the phase relationship between the clock signal 712 and the clock signal 811 is skewed and the rising edge of the clock 712 overlaps with the rising edge of the clock 811 (the portion indicated by t _{c in} FIG. 9), the flip-flop in the logic unit is When the clock signal is hit with the clock signal 811, it becomes unstable, and the output of the flip-flop is not fixed for a long time. This is metastability.

In order to avoid the above-mentioned metastability, in this conventional example, as shown in FIG.
The phase relationship between 1 and the clock signal 712 is fixed to the relationship shown in FIG.

[Problems to be solved by the invention]

First, the first conventional example shown in FIG. 2 will be described. The first problem of this conventional example is that the polyphase clock signal 212 must be distributed to the entire information processing apparatus. Therefore, the clock skew usually becomes large, and the duty of each clock signal also deviates from the desired value. This problem is particularly remarkable when the machine cycle is increased due to the increase in speed and the polyphase clock signal 212 has a high frequency. That is, a large part of the machine cycle is taken for blackout. On the other hand, the advantage of this conventional example is that the same polyphase clock signal 21
Since the two are distributed, data can be exchanged between the logical units in a synchronous manner.

Next, the second conventional example shown in FIG. 3 will be described. This configuration is found in microprocessor systems and the like. The information processing unit corresponds to the LSI chip. The first problem of this conventional example is that each information processing unit is controlled by a separate clock signal, and therefore the interfaces between the information processing units must be performed asynchronously. Asynchronous interfaces require synchronization of asynchronous signals and are slower than synchronous interfaces. This becomes a problem especially when it is desired to create a high-speed system in which data is frequently exchanged between information processing units. However, the advantage of the conventional example is that the clock signal is generated in each information processing unit and the clock signal is distributed in one information processing unit, so that the clock skew can be reduced. is there.

The second problem of this conventional example is that a high-frequency original clock signal must be supplied from outside the information processing unit. Normally, the original clock signal is frequency-divided inside the information processing unit in order to generate a clock signal with a correct duty. Therefore, for example, divide by 2 and machine cycle 40
Considering the case of MHz, the original clock signal of 80 MHz must be supplied from the outside. This is difficult when considering the LSI chip stored in the package as the information processing unit hardware. This problem becomes even more pronounced when the machine cycle becomes high.

Next, problems with the third embodiment shown in FIGS. 7 to 9 will be described. The first problem of this conventional example is that
That is, the high-speed clock signal 711 must be supplied from the outside of the information processing unit. The second problem is that no consideration is given to the clock duty used inside the information processing unit.

A first object of the present invention is to synchronize clock signals between a plurality of information processing units in an information device.

A second object of the present invention is to supply a clock signal with a small clock skew and an accurate clock signal to each information processing unit.

A third object of the present invention is to avoid supplying a high-speed clock signal from the inside of the information processing section.

[Means for solving problems]

The above-mentioned object is an information processing system comprising an original clock oscillator for transmitting at least one original clock signal K serving as a first clock signal and a plurality of information processing units connected to the original clock signal K. Clock generating means for synchronizing each of the processing sections with the at least one original clock signal K and generating at least one second clock signal K ₁ having a predetermined duty; and the second clock generating means. constituted by logical unit and which is timing controlled by clock signals K _1, the in-tough ace in between at least one pair of said logic device, by the clock signal K _1, it is accomplished by timing control in synchronization.

[Action]

The at least one-phase clock signal K ₁ generated inside the information processing section is in phase synchronization with the original clock signal K. As a result, a clock signal inside a certain information processing unit
K _1, through an original clock signal K, may be clock signals K ₁ and phasing of the internal other information.

In addition, each information processing unit has a built-in clock generation means that is phase-synchronized with at least one original clock signal K and generates at least one second clock signal K ₁ having a predetermined duty. Therefore, it is possible to supply a clock signal with a small clock skew and a precise clock signal to each information processing unit.

Further, the clock generation means outputs the original clock signal K,
The internal clock signal K ₁ is phase-locked, but the frequency of the original clock K need not be equal to or higher than the frequency of the internal clock signal K ₁ . Therefore, in an information processing device including a plurality of information processing units in which the frequency of the internal clock signal K ₁ is increased for speeding up, it is possible to avoid supplying a high-speed clock signal from the outside of each information processing unit. .

〔Example〕

 An embodiment of the present invention will be described below.

FIG. 10 is an overall view of an information processing apparatus which is an embodiment of the present invention. Reference numeral 1001 is an original clock oscillator, 1011 is an original clock, 1002 and 1003 are information processing units, and 1012 is an interface signal for exchanging data between the both information processing units.

There may be various information processing apparatuses to which the present invention is applied, but in the present embodiment, a computer CPU configured by an ultra-high speed VLSI will be described as an example. Further, an information processing apparatus generally comprises a plurality of information processing units, but in this embodiment, it is assumed that it comprises two information processing units for simplicity.

Further, the information processing section is a part of the information processing apparatus, and is a unit that is logically functional and hardware. As hardware, one information processing unit is a board on which a plurality of LSI packages are mounted, or one that is formed on a single semiconductor substrate, that is, one information processing unit.
It may be an LSI or a part of one LSI. Further, the wafer scale integration can be one block on a single semiconductor substrate wafer. In the present embodiment, the information processing unit is one VLSI mounted in a package.

The description of the embodiment of the present invention will be made in terms of the information processing unit 1002
It suffices to mention only the interface between 1003, and what kind of processing is shared by both information processing units is not directly related to the present invention. Therefore, although not described in detail, the following two cases will be illustrated.

1) The information processing unit 1002 is a BPU (Basic Processing Unit) that performs instruction decoding and basic instruction processing, and
1003 is an FPU (Floating Processing) that performs floating point arithmetic.
34) shows an example of the configuration of the unit). 101,3401 is
These are the clock generators of the information processing units 1002 and 1003, respectively. 102 and 3406 are logic devices that perform a desired logical operation on an input signal and output an output signal. 3402 and 3404 are bus controllers that form an interface means. 3403 is a register MAR (Memory Address Register) that holds a memory address.
r) and 3405 are register MDR (Me
mory Data Register), 3407 is a memory. Signal 3410
Is an address bus, 3411 is a data bus, and 3412 is a control signal. A reference numeral 3419 is a signal indicating the type of floating point arithmetic instruction to be processed.

In this configuration example, the logical device of FPU1003 does not have the address calculation function. It functions as a so-called coprocessor. The operation will be described by taking as an example the loading of floating point data from memory into the FPU. Logical unit 102 in BPU1002
When the floating point arithmetic instruction is decoded, the instruction type is sent to the FPU 1003 via the signal 3419. On the other hand, the memory address is calculated and set in the MAR3403 through the signal 3418. Also, the memory read activation is sent to the bus controller 3402 through the signal 3415. The bus controller 3402 synchronizes with the clock 3420, and by the signal 3413,
The contents of MAR are controlled to be sent to the address bus 3410. It also sends out a control signal 3412 for controlling the memory.

On the other hand, the bus controller on the FPU side receives the control signal 3412, and sends the data fetch signal 3414 to the MDR 3405 at the timing when the memory 3407 sends the data to the data bus 3411. After fetching the operand in the MDR, the operand read end signal 3416 is sent to the logic unit 3406. Also, the loaded operand data is sent out through the signal 3417.

2) The information processing unit 1 is a master BPU and the information processing unit 2 is a slave BPU. In other words, it is a computer in which the BPU is duplicated to improve reliability. The slave BPU has the same function as the master BPU and operates in synchronization with the master BPU. Then, when the master BPU writes to the memory, the slave BPU fetches the data in its own chip and compares it with its own data. If not, master it
Notify BPU.

FIG. 29 shows the configuration described above. 29
00 is memory. 2901 to 2905 are interface signals,
2901 is address, 2902 is address strobe, 2903 is data, 2904 is read / write signal, 2905 is slave BP
U is a signal that notifies the master BPU of an error. Again 2906
Is high, the information processing unit is the master and low
If so, it is a signal indicating that the information processing unit is a slave.

FIG. 30 is a timing chart showing the operation of the above embodiment. Since both information processing units are operating in synchronization, when the master BPU writes, the slave BPU also has a write address and write data. The memory cycle will be extended by the amount of clock skew between chips.

Next, the oscillator 1001 will be described. The oscillator 1001 is an oscillator that sends out the original clock signal 1011. Hara Clock 10
11 may be polyphase, but in the present example, 1
It is a phase. The duty of the original black does not necessarily have to be 50%. This is the feature of the present invention.

Further, the oscillator may be built in the information processing unit 1 for convenience. The configuration in this case is the 11th
It is a figure. Reference numeral 1100 is a VLSI chip in which the information processing unit 1002 and the oscillator 1001 are built in the same semiconductor substrate. 1011 is a crystal oscillator. Since the chip 1002 itself also takes in the oscillator output 1011 output outside the chip once, the relationship between the original clock signal, the information processing section 1 and the information processing section 2 is the same as in FIG. In the configuration of FIG. 11, since the chip 1100 has an oscillator built therein, there is an advantage that the oscillator does not need to be externally attached and the hardware becomes small.

FIG. 1 shows the internal configuration of the information processing unit 1002 shown in FIG. 101 is a clock generator, 111 is a polyphase clock signal, 102 is a logic device, 103 is an interface circuit, 11
2 is a signal line between the logic device 102 and the interface circuit 103. A clock generator 101 generates a multi-phase clock 111 including at least second and third clock signals from an original clock signal 1011 from the outside and sends it to a logic device 102 and an interface circuit 103. There are various types of polyphase clocks as shown in FIGS. 4, 5, and 6, but here, the non-overlap two-phase clocks K ₁ and K ₂ shown in FIG. 4 are used. .

Next, the logic device 102 of FIG. 1 will be described. The logic device 102 is controlled by the two-phase clock signals K ₁ and K ₂ . The logic elements that make up the logic device 102 include inverters, basic gates such as 2NAND, flip-flops, PL
There are various kinds such as A, ROM, RAM, but here, taking PLA as an example, how the clock signal K ₁ and the clock signal K ₂ are used, and when the machine cycle is shortened,
Describe what is required of the clock signals K ₁ and K ₂ .

FIG. 12 is a circuit diagram of the PLA controlled by the two-phase clocks K ₁ and K ₂ . FIG. 13 is a timing chart showing the operation of this PLA.

In FIG. 12, 1201 to 1207 are PMOSs for precharging the wirings 1229 to 1235, 1209 to 1212 and 1219 to 1221 are clocked inverters, 1213 to 1218 and 1240 and 1241 are inverters, and 1222 to 1228 are 2 inputs. It is NOR. Further, X, Y, Z are inputs, and L, M, N are outputs. This PLA implements the following logic.

L = X + Y * Z M = X * Z + X * Y N = Y * Z + X * Z.

As shown in FIG. 13, the wiring 1229 is recharged when K ₂ is (high), and when K ₁ is (high) and X = 0,
The charge is extracted by the NMOS. On the other hand, when X = 1, it is not pulled out. When X = 0, it must be pulled out during the high period of K ₁ , that is, during t ₃ shown in FIG. Regarding the design of the clock system, considering that t ₃ is squeezed during clock distribution, even in the worst case,
It is set so that the charge withdrawal of the wiring is completed.

On the other hand, the wiring 1235 is precharged when K ₁ is high,
When K ₂ is high, that is, during the period t ₄ , charge extraction is performed. t ₃ Similar t ₄ also consideration that some, become narrower in clock distribution, in the worst case, the charge withdrawal of the wiring is set to end during t ₄ period.

t ₃ , t ₄ are used symmetrically as described above, so t ₃
It is designed as = t ₄ . Further, as is apparent, in order to shorten the machine cycle, the fluctuation of t ₃ and t ₄ is small, that is, the duty of K ₁ and K ₂ is accurate in the logic unit 102 of FIG. It is important to have something.

Next, the black skew will be described. In Fig. 12, when the wiring 1229 is pulled out, the output of the inverter 1213 is
It changes from gh to Low, but this change must be completed before the output of the inverter 1218 becomes low,
The wiring 1233 may be accidentally pulled out. Therefore, the period t ₁ in FIG. 13 needs to be a certain value or more. In designing the clock, the fact that t ₁ becomes short during clock distribution is taken into consideration, and the clock is set so as to prevent the malfunction even in the worst case. The same applies to t ₂ . As is clear here, in order to shorten the machine cycle, it is important that there are few fluctuations in t ₁ and t ₂ , that is, the clock skew of K ₁ and K ₂ is small.

To summarize the logic device 102 controlled by the clocks K ₁ and K ₂ , in order to shorten the machine cycle, it is required to minimize the deviation of the duty of the clock signal and the clock skew.

Next, the clock generator 101 will be described. The operation of the clock generator is shown in FIG. The clock generator 101 receives the original clock signal K, the two-phase clock signal K ₁ ,
Output K ₂ . The duty of the original clock signal K does not have to be 50%. K ₁ and K ₂ are in phase synchronization with K, and K ₁ and K ₂ are set to t ₁ = t ₂ and t ₃ = t ₄ as described above. The phase synchronization mentioned here means that the phase relationship between K and K ₁ is constant, and more specifically, the difference between the rise of K and the rise of K ₁ is constant. In Fig. 14, K and K ₁ , K
The frequencies of ₂ are equal. However, they do not necessarily have to be equal. FIG. 15 shows another operation example of the clock generator 101. Although K and K ₁ or K and K ₂ are in phase synchronization, the frequency of K ₁ and K ₂ is twice that of K. This is preferable because the machine cycle is increased inside the chip, the clock supplied from the outside of the chip is kept at a low frequency, and there is no restriction on its duty.

In addition, "lo" of the original clock signal K which becomes the first clock signal
w "is first potentiator dial levels," high "is the second potentiator dial level, and the second, third of K _1, K ₂ which is a clock signal" low "the third potentiator dial level," H
igh "is the fourth potential level.

Here, preferably, the first potential level and the third
Is substantially equal to and the second and fourth potential levels are substantially equal.

Next, the detailed configuration of the clock generator 101 will be described.

FIG. 16 shows a clock which receives 1011 (thick clock signal K) and is phase-locked at the same frequency as K to generate non-overlap two-phase clocks K ₁ and K ₂ (corresponding to FIG. 14) of a predetermined duty. 3 shows an exemplary configuration of a generator 101.

Phase comparator 1301, low-pass filter (hereinafter abbreviated as LPF) 13
02, Voltage controlled oscillator (VOC: Voltage Control Oscilla)
1303, 1 / N (for example, 1/2) frequency divider 130
A PLL is composed of 4 closed loops. Ie 1011 and 13
The phase difference and frequency difference of 09 are detected by 1301, and a pulse signal according to the difference is output to 1306. 1302 integrates 1306 into a DC signal (voltage value) 1307, and 1303 oscillates at a frequency according to 1307 and outputs it to 1308. The 1304 outputs a clock signal with a duty of 50% to the 1309 by dividing the 1308 by half. Therefore, 1309 becomes a clock signal with a duty of 50% by synchronizing the phase with 1011 by the PLL, making the frequencies equal, and dividing by 1304.

The two-phase clock generator 1305 receives the clock signal 1309 with a duty of 50% and receives the non-overlapped two-phase clock signal.
Outputs K ₁ and K ₂ . FIG. 17 shows a configuration example of the gate level 1305.

The outputs K ₁ and K ₂ of the 2-input NOR circuits 1311 and 1312 are cross-connected to one of the inputs, and the other is connected to the complementary signals of the inverted signals 1313 and 1309 of 1309 by the inverter circuit 1310.

Figure 18 shows the operating waveforms at each point in Figures 16 and 17. 1301 ~ 130
With 4 PLLs, 1011 and 1309 are in phase and equal in frequency. Therefore, the oscillation output 1308 of 1303 before being divided by half in 1304 is shifted from 1011 by the delay Δt _{0 of} 1304,
It is twice the frequency. The 1309 divides the 1308 by 1304, so the duty is 50%. 1313 is 1309 to 1310
Is delayed by Δt ₁ . Since K ₁ and K ₂ are 2-input NOR circuit outputs, they become high when both inputs are low. That is, when _one of K ₁ and K ₂ is high, the other is always low, and there is no overlap. 13 for K ₁ to rise
09 rises, 1312 delays Δt _{1 and} then K ₂ falls, and 1311 delays Δt _{2 and} then rises. Conversely, for K ₂ to rise, 1309 falls, 1313 rises after a delay Δt _{1 of} 1310, K ₁ falls after a delay Δt _{2 of} 1311, and rises after a delay Δt _{1 of} 1312. Therefore, the time when both K ₁ and K ₂ are low is the delay t ₂ , t ₁ of 1311, 1312, and the circuit configuration of 1311 and 1312 should be the same, and the loads of K ₁ and K ₂ should be equal. Therefore, it is possible to set t ₁ = t ₂ . The K ₁ and K ₂ of the pulse width (the High state time) t _3, t ₄ the following equation holds.

(However, the period is T.) From equations (1) and (2), t ₁ + t ₃ −Δt ₁ = t ₂ + t ₄ + Δt ₁ (3)

By the way, the delay Δt ₁ of 1310 is 1311
However, the load of 1313 is very small and can be ignored compared to the delays t ₂ and t ₁ of 1311 and 1312. Therefore,
The equation (3) is t ₁ + t ₃ = t ₂ + t ₄ . As described above, if t ₁ = t ₂ is set, then t ₃ = t ₄ , and an ideal non-overlap two-phase clock signal can be obtained. Also, the two-phase clocks K ₁ and K ₂ are 1011
It is generated from 1309 in synchronism with and has a constant phase relationship with 1011.

From the above, it is possible to generate a clock signal with a predetermined duty in phase synchronization with 1011 (original clock K).

In order to reduce the clock skew between the information processing units, it is preferable that the clock generators among the plurality of information processing units have the same configuration.

FIG. 19 shows another configuration example of the gate level 1305. First
In FIG. 19, the same symbols as in FIG. 17 indicate the same parts and the same functions.

2-input NAND circuit 1314, 1315 output 1320, 1321 to delay circuit
Via inputs 1316 and 1317, one of inputs 1322 and 1323 is crossed and connected, and the other is connected with complementary signals 1309 and 1313, respectively. 1320 and 1321 are output as two-phase clocks K ₁ and K ₂ via inverters 1318 and 1319. In this configuration, 2-input NAND
Since it is returning from the output of the circuit through the delay circuit,
In order for K ₁ to rise, 1309 will fall and then 13
It rises through 10,1315,1317,1314,1318. On the other hand, the fall of K ₂ is followed by 1310, 1315, and 1319 after 1309 rises. Therefore, if the delay of 1316,1317 is made larger than the others, the time when both K ₁ and K ₂ are low is 1316,131.
Can be set with 7.

20 shows the operation waveforms of FIGS. 20 to 19. Delay circuit 1316, 1317
The solid line shows the case where the delay time is small, and the broken line shows the case where the delay time is large. That is, the duty of the two-phase clocks K ₁ and K ₂ is 131
Since it can be changed by the delay time of 6,1317, a non-overlap two-phase clock signal having an arbitrary duty can be obtained. Therefore, by using the circuit of the present configuration, it is possible to set the non-overlap two-phase clock water drain (the time when both clock signals are low) only for the clock skew generated in the logic device.

FIG. 21 shows 1011 (original clock K), which is phase-locked at a frequency higher than K (twice the frequency) and has a predetermined duty non-overlap two-phase clock signal K ₁ , K ₂ (15th clock).
2 shows an example of the configuration of the clock generator 101 for generating (corresponding to the figure). 21, the same reference numerals as those in FIG. 16 indicate the same parts and the same functions.

The difference between FIG. 21 and FIG. 16 is that by adding a ½ divider 1304 to the feedback loop of the PLL, the number of stages becomes two and the input of the two-phase clock generator 1305 becomes the output 1323 of the previous 1304. It is that.

FIG. 22 shows the operation waveform of FIG. Since the PLL feeds back through two stages of the 1/2 frequency divider, the output 1322 of 1303 has a frequency four times that of 1011. Also, the output 1323 of the previous stage 1304 is 2
Since the frequency is divided by one, the duty is 50% and 10
With respect to 11, the clock signal is doubled in frequency and is out of phase with the delay Δt ₀ of the subsequent 1304. In response to this 1323,
1305 outputs non-overlap two-phase clock signals K ₁ and K ₂ . As described above, the 1305 can generate an ideal non-overlap two-phase clock signal from a duty 50% clock signal. Therefore, even in this configuration, the ideal non-overlap two-phase clock K ₁ , K ₂ Can be obtained.
Further, since the phase relationship between 1323 and 1011 is constant (difference of Δt ₀ ), the phase relationship between K ₁ , K ₂ and 1011 is also constant.

From the above, it is possible to generate a high-frequency clock signal with a predetermined duty by performing phase synchronization from an external low-frequency clock signal.

FIG. 23 shows a clock which receives 1011 (original clock signal K), is phase-locked at the same frequency as K, and generates an overlapped four-phase clock signal K ₄₁ , K ₄₂ , K ₄₃ , K ₄₄ of a predetermined duty. 3 shows an exemplary configuration of a generator 101. 23, the same reference numerals as those in FIG. 16 indicate the same parts and the same functions.

1301,1302,1303 by the closed loop of 1/4 divider 1324
Configures the PLL. Therefore, the phases of 1011 and 1309 are synchronized and the frequencies are equal. 1/4 in closed loop of PLL
Since the frequency is divided, 1303 oscillates at a frequency four times that of 1011 and outputs a clock having a phase shift of 1309, that is, the delay Δt ₂ of 1011 and 1324 to 1322. 1309 divides 1322, so the duty is 50%.

The 4-phase clock generator 1325 is a clock with 50% duty.
Overlap four-phase clock signals K ₄₁ , K ₄₂ , K ₄₃ , which are obtained by shifting the phase of 1309 by 90 ° by a clock 1322 having a frequency four times that of 1309.
And it outputs the K _44. FIG. 24 shows a configuration example of the gate level of 1325.

Clocked Inverter 1327 and inverter 1328 are connected in series to the dynamic clutch, and every other dynamic clutch is inverted by inverter 1326.
And 1322 are controlled by complementary signals to form a shift register.

Figure 25 shows the operation waveforms in Figures 23 and 24. As described above, 1322 has a frequency four times that of 1011 and has a phase difference of 1011 and Δt ₂ . 1309 has the same frequency and phase as 1011 and has a duty
50%. The 1st stage dynamics clutch output 1330 by 1327 and 1328 rises in synchronization with the rise of 1309 after the rise of 1309 and the rise of 1329 in synchronization with the fall of 1309 and the rise of 1329 for the first time. Get down. Next, the second-stage dynamics clutch output K ₄₁ by 1327 and 1328 rises synchronously when 1322 starts and rises after 1330 rises, and synchronizes when 1322 starts and rises after 1330 falls. And go down. Therefore, K ₄₁ is delayed in phase by one cycle from 1309 to 1322. This relationship is K ₄₁ and K ₄₂ , K ₄₂ and K ₄₃ , K ₄₃ and K ₄₄
Similarly, K ₄₁ , K ₄₂ , K ₄₃ , and K ₄₄ are delayed in phase by one cycle of 1322. Since 1322 has a period four times as long as 1011, it is 90 ° out of phase. That is, K ₄₁
~ K ₄₄ is an ideal overlapping 4-phase clock signal. Also, since the phase relationship between 1322 and 1011 is constant, the phase relationship between K _{41 to} K ₄₄ and 1011 synchronized with 1322 is constant.

From the above, it is possible to generate a clock signal with a predetermined duty in phase synchronization with 1011 (original clock K). In this configuration, 1309, which is a clock signal having the same frequency as 1011, is used as the signal whose phase shifts,
Since the clock signal 1322 having a frequency four times that of 1011 is used as the phase to be shifted, it is a non-overlap four-phase clock signal having the same frequency as 1011, but the same applies to the frequency multiplied by 1309 and 1322. Also, by making the number of stages of the shift register of 1325 equal to the multiplication number of the frequency of 1322 from 1309, it is possible to obtain a polyphase clock signal of an arbitrary number of phases.

FIG. 26 shows that in response to 1011 (original clock signal K), phase synchronization is performed at the same frequency as K to generate non-overlap two-phase clock signals K ₁ and K ₂ with a predetermined duty. 10 shows an example of the configuration of a clock generator 101 that can directly generate a non-overlapping two-phase clock signal from 1011. 26, the same reference numerals as those in FIG. 16 indicate the same parts and the same functions.

The difference between FIG. 26 and FIG. 16 is that the input of 1305 is an external signal 13
Signal 1338 which is the signal of 37 and its signal inverted by the inverter circuit 1325
1337 by a clocked inverter 1334 controlled by
When is high, it is 1309, and when it is low, it is 1011. However, since a clocked inverter is used, the phases of K ₁ and K ₂ are 90 ° out of phase with 1011.

That is, when a two-phase clock signal of a fixed duty is required by operating at high speed, the clock signal is generated from the clock 1309 having a duty of 50%. On the other hand, when diagnosing the function of the logic device at a low frequency as in the case of testing, the two-phase clock signal can be generated directly from 1011.

As described above, in this configuration, when operating the inside at a low frequency, a two-phase clock is directly generated from the external clock signal, and conversely, when operating the inside at a high frequency, a clock with a duty of 50% is synchronized with the external clock signal. Can generate a two-phase clock part signal. Therefore, there is an effect that the range of the oscillation frequency with respect to the oscillator in the clock generator can be limited. It is also possible to stop the clock signal and perform a DC functional test when diagnosing the internal logic device. Note that this configuration uses a non-overlap 2 with the same frequency as the original clock signal.
Although the case of the phase clock generation has been described, as shown in FIGS. 27 and 28, when the non-overlap two-phase clock signal of a higher frequency than the original clock signal is generated, or when the external clock signal is different from the original clock signal, The same applies to the case of the overclocking four-phase clock signal generation. The logic device is controlled with respect to the clock generator which receives the original clock signal, synchronizes the phase with the original clock signal, and generates at least one clock signal of a predetermined duty. By switching between the signal generated in the clock generator and the signal input from the outside as the signal input to the circuit for transmitting the clock signal, the above-described effect can be obtained.

FIG. 33 shows a configuration example of the phase comparator 1301 of FIG. 3301 is an inverter, 3302 is a 2-input NAND, 3303 is a 4-input NAND, and 3304 is a 4-input NAND.

35 (a) and 35 (b) are a state diagram and a state transition diagram showing the operation of the phase comparator 1301. 1301 has 8 states a,
It consists of b, c, d, e, f, g and h. The value written in the eight circles indicating the state is the output “P, D” of the phase comparator 1301. The value written next to the arrow indicating the state transition is the input “1011,1309” of the phase comparator 1301 that causes the state transition.
As can be seen from this figure, the output P of the phase comparator becomes High in states c and g, and the output D of the phase comparator becomes High in state e,
At h. That is, in the phase relationship of the inputs 1011 and 1309 of 1301, when 1309 is delayed from 1011, the output P becomes High from the rise of 1011 to the rise of 1039, and conversely, when 1309 is advanced from 1011, 1309 The output D becomes High from the rising edge of 1011 to the rising edge of 1011.

FIG. 36 is a time chart showing the operation of the phase comparator 1301. As can be seen from the description of FIGS. 35 (a) and 35 (b), the output P is high during the period in which the input 1011 leads the input 1309 in phase. On the other hand, the output D has the input 1101
It goes high during the phase delay with respect to input 1309. The above is the operation of the phase comparator 1301.

FIG. 37 is a diagram showing a configuration example of the low-pass filter 1302 of FIG. This is a circuit called a charge pump. 1301, 1302 are NMOS transistors, 1303 are resistors, 1304
Is the capacitance.

FIG. 38 is a timing chart showing the operation of the low pass filter shown in FIG. When the input P is high, NM
OS1301 is turned on, the pulse current i _p flows, the potential of the node 1305 rises. On the other hand, when input D is high, NMOS
1302 is turned on, a pulse current i _D flows, and the potential of the node 1305 drops. At 1307, the potential of 1305 is smoothed by the low-pass filter composed of the resistor 1303 and the capacitor 1304. As described above, the circuit 1302 is a circuit that changes the potential of the output 1307 in proportion to the pulse width of the input P and the pulse width of the input D.

FIG. 39 shows an example of the structure of the VCO 1303 shown in FIG. In FIG. 39, 3901 is a multivibrator circuit, 3902 is a level shift circuit, and 3903 is a level conversion circuit.

In 3901, NPN transistors 3906 and 3907 whose collectors and bases are cross-connected perform a switching operation in which one is in an ON state and the other is in an OFF state to form an astable multivibrator. Resistors 3904 and 3905 that supply current from the power supply Vcc are connected to the collector sides of the 3906 and 3907. Also,
The emitter side is mutually connected by a capacitor 3908 and is grounded via NMOS transistors 3909 and 3910. The gates of 3909 and 3910 are the outputs of the LPF 1302 and are connected to the control voltage input 1307 of the 1303, which is a bias current source for flowing a current according to the voltage value of 1307.

The 3901 works as follows. First, 3906 is ON, 3907
Consider the case where is in the OFF state. Assuming that the current value of 3909, 3910 is I, the current 2I of both 3909, 3910 flows through the resistor 3904, and the current I of 3910 flows through 3908 from 3922 to 3933. Therefore, 3920 drops from Vcc by the amount of voltage drop of 3904, and conversely, 3921 is pulled up to Vcc by 3905. Since 3906 is in the ON state in 3922, the potential dropped from 3921 by V _{BE of the} bipolar transistor (the voltage between the base and the emitter required to turn on the bipolar transistor, which is generally about 0.8 V for Si transistors). Becomes 3908
Since I flows through the capacitor, if the capacitance of 3908 is C, the potentials of 3922 and 3923 at both ends of 3908 change with I / C with time. Then, when the potential of 3923 becomes V _BE lower than 3920, 3907 is turned on and the current I flowing in 3908 is 3905.
Through to 3907. Then, the voltage of 3921 drops by the voltage drop of 3905, and the voltage between 3921 and 3922 becomes V _BE or less, so that 3906 is turned off.

That is, in 3901, two transistors are switched alternately. FIG. 40 shows operation waveforms of the 3901. The 3901 can obtain 3920 and 3921 differential signals. Also, this oscillation frequency is the current value I flowing through 3909, 3910.
, The frequency can be changed by changing I. However, since the output amplitude of the multivibrator is small, it is necessary to amplify the output of the multivibrator to the logic amplitude of CMOS when using CMOS as an internal circuit.

Reference numeral 3903 is a level conversion circuit thereof, and reference numeral 3902 is a level shift circuit which connects 3901 and 3903.

In 3902, NPN transistors 3911 and 3912 and resistors 3913 and 3
Series circuit of 914 is 3901 input to the base of 3911,3912
The differential output of 3920, 3921 is lowered by V _{BE and} output to 3925, 3924.

The 3903 has a PMO with the 3902 outputs 3924 and 3925 connected to the gate.
S-transistors 3916 and 3918 are replaced with NMOS transistors 3917 and 3919
In the series circuit of 3917, 3919 gates 3916 and 3917
Are commonly connected to the connection point. That is, when the current of 3916 is large, the voltage drop of 3917 is also large and the impedance of 3919 is small. In this case, since the current of 3918 is small, 1322 becomes Low. Conversely, if the current of 3916 is small, then 3
The voltage drop of 917 becomes small and the impedance of 3919 becomes large. In this case, the current of 3918 is high and 1322 is high.
Becomes That is, the 3903 operates as Push-Pull,
The amplitude of the output 1322 becomes large.

As described above, in this configuration example, a VCO having a CMOS level output can be realized.

FIG. 31 shows another configuration example of the logic device 102 shown in FIG. Reference numerals 3100 to 3103 are four sub-logical units that form a logical unit. 3104 to 3106 are interfaces between sub-logical units. Each sub-logic unit operates in synchronization with the clock 111.

FIG. 32 is a diagram showing the configuration of the sub logic device 3100.
3201 is a clock generator, 3202 is a logic device, 3203 is
It is an interface circuit. 3211 is a clock for controlling the logic device 3202. That is, the sub-logical unit 3100
Has the same configuration as the information processing unit 1002. With such a hierarchical structure, for example, 1 MHz is used as the original clock signal 1011 for synchronizing the information processing unit, for example, 10 MHz is used as the clock signal 111 for synchronizing the sub logic device, and the logic device 3202 in the sub clock is used. The clock frequency can be gradually increased, for example, 100 MHz is used as the clock signal to be controlled. With this hierarchical structure, even in a large-scale information processing apparatus, it is possible to shorten the machine cycle while keeping the clock distributed to the entire information processing apparatus at a low frequency.

〔The invention's effect〕

According to the present invention, since the inner surface of each information processing unit constituting the information processing apparatus has the clock generation means for generating at least one clock signal K ₁ phase-synchronized with the original clock signal K, The departments can be synchronized.

Further, according to the present invention, since the clock generating means generates the clock signal K ₁ of a predetermined duty, it is possible to generate an accurate clock signal of the duty. Further, since the generated clocks may be distributed only within the respective information processing units, the clock signal K ₁ with a small clock skew and a small duty deviation can be distributed within the logic device.

Further, according to the present invention, the low frequency original clock signal from the outside of the information processing unit and the high frequency clock signal inside the information processing unit can be synchronized, so that the machine cycle of the information processing apparatus can be increased while the information processing unit is being increased. The original clock signal from the outside can be kept at a low frequency.

[Brief description of drawings]

FIG. 1 is a block diagram of an information processing unit according to one embodiment of the present invention,
2 and 3 are block diagrams showing a conventional example, and FIGS. 4 to 6 are timing charts and 7 for explaining a conventional example.
FIG. 8 is a block diagram showing a conventional example, FIG. 9 is a timing chart explaining a conventional example, FIGS. 10 and 11 are overall block diagrams of one embodiment of the present invention, and FIG. 12 is the present invention. FIG. 13 is a timing chart for explaining the operation of FIG. 12, FIG. 13 is a timing chart for explaining the operation of FIG. 12, and FIGS. 14 and 15 are for explaining the operation of the clock generator of one embodiment of the present invention. Timing charts, FIGS. 16 to 28 are block diagrams for explaining the clock generator of one embodiment of the present invention, and timing charts, FIGS. 29 and 30 are information processing units of one embodiment of the present invention. Figure explaining the interface between, Figure 31 to 40
FIG. 1 is a diagram showing a configuration example of an embodiment of the present invention. 1001 …… Original clock oscillator, 1011 …… Original clock signal,
1002, 1003 ... Information processing unit, 1012 ... Interface signal, 101 ... Clock generator, 102 ... Logic device, 103 ...
... interface circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hideo Maejima 4026 Kuji Town, Hitachi City, Hitachi, Ibaraki Prefecture Hitachi Research Institute, Ltd. (72) Inventor Shigeya Tanaka 4026 Kuji Town, Hitachi City, Ibaraki Prefecture Hitachi, Ltd. Inside Hitachi Research Laboratory (72) Inventor Tadaaki Bando 4026 Kuji Town, Hitachi City, Hitachi, Ibaraki Prefecture Hitachi Research Laboratory, Inc. (72) Inventor Yasuhiro Nakatsuka 4026 Kuji Town, Hitachi City, Ibaraki Prefecture Hitachi Research Laboratory (72) Inventor Kazuo Kato 4026, Kuji-cho, Hitachi City, Ibaraki Prefecture Hitachi Research Laboratory, Hitachi Co., Ltd. (56) References JP-A-52-66346 (JP, A) JP-A-59-3676 (JP, A) JP-A-62-27813 (JP, A) JP-A-58-151622 (JP, A) JP-A-61-109236 (JP, U) JP-A-62-70924 (JP, A) Open Akira 49-29042 (JP, A) JP Akira 55-52653 (JP, A) JP Akira 54-35666 (JP, A) JP Akira 60-211666 (JP, A)

Claims (18)

[Claims] 1. The information processing apparatus operates in synchronization with at least one other information processing apparatus based on a first clock signal having a first clock frequency, and exchanges information with the at least one other information processing apparatus. At least one clock generator that performs input and output in synchronization and generates a second clock signal from the first clock signal, and at least one information processor that processes information based on the second clock signal And an information processing device formed on one semiconductor substrate, wherein the clock generation unit receives (1) the first clock signal and the second clock signal, and outputs the first and second clock signals. A phase comparator that generates a signal representing the phase difference between the two clock signals, and (2) a low-pass filter that generates a voltage signal determined by the signal generated by the phase comparator. (3) A voltage-controlled oscillator that is controlled by the voltage signal generated by the low-pass filter and that generates a third clock signal having a frequency that is an integral multiple of the first frequency, and (4) the voltage-controlled oscillator. The frequency of the third clock signal is divided so that the duty is determined by the frequency of the third clock signal, and the information processing is performed at substantially the same frequency as the first clock signal. A frequency divider section for generating the second clock signal necessary for the operation of the section, and (5) being connected between the frequency divider section and the phase comparator, and applying the second clock signal to the phase And a feedback path for supplying to a comparator, wherein the information processing unit has a timing from a rising edge to a falling edge or a rising edge from a falling edge of the second clock signal output from the frequency divider section. The information processing apparatus characterized by having at least one circuit operating in response to the timing of Rimade. 2. The information processing unit according to claim 1, wherein the information processing unit outputs an output signal from the information processing unit based on a second clock signal output from the frequency divider unit of the clock generation unit. An information processing apparatus, comprising: an interface section for inputting / outputting an input signal to the information processing section to / from the other at least one information processing apparatus. 3. The information processing device according to claim 1 or 2, wherein the information processing device has a clock oscillating section for transmitting the first clock signal. 4. The frequency divider unit according to claim 1, 2, or 3, wherein the second clock signal is a rising edge or a falling edge of the second clock signal. An information processing apparatus, characterized in that frequency division is performed so as to have a predetermined duty in which the phase of each and the main edge of the third clock signal are synchronized. 5. The frequency divider unit according to claim 1, 2, 3, or 4, wherein said frequency divider unit comprises at least two frequency dividers, said frequency divider unit being connected to said voltage controlled oscillator. A first frequency divider that divides the frequency of the third clock signal to generate a fourth clock signal so that the duty is determined by the frequency of the third clock signal; and the first frequency divider. A frequency of the fourth clock signal from the frequency divider or another clock signal from another frequency divider connected in series to the first frequency divider, and substantially dividing the frequency with the first clock signal. An information processing device, comprising: a second frequency divider that generates the second clock signal having the same frequency. 6. Claims 1, 2, 3,
In the fourth or fifth term, the third clock signal multiplied by a predetermined integer value by the voltage control oscillator is adjusted to the predetermined frequency by all the frequency dividers included in the frequency divider section. An information processing apparatus, wherein the second clock signal divided into a numerical value is input to the phase comparator. 7. Claims 1, 2, 3,
In item 4, item 5, or item 6, the information processing unit includes a gate circuit that performs processing by the second clock signal, the fourth clock signal, or the other clock signal. Information processing equipment. 8. Claims 1, 2, 3,
The information processing device according to any one of items 4, 5, 6, or 7, wherein the information processing device is a microcomputer. 9. Claims 1, 2, 3 and
The information processing device according to any one of items 4, 5, 6, or 7, wherein the information processing device is a processor. 10. Claims 1, 2 and 3
Section, Section 4, Section 5, Section 6, Section 7, Section 8, or Section 9.
In the paragraph, there is provided a multi-phase clock generator which receives the second clock signal, the fourth clock signal, or the other clock signal and generates a plurality of clock signals having different phases,
An information processing apparatus comprising: at least one information processing unit that processes data based on the plurality of clock signals. 11. The information processing apparatus according to claim 10, wherein the information processing unit processes data based on rising edges of the plurality of clock signals. 12. The information processing apparatus according to claim 10, wherein the information processing unit processes data based on falling edges of the plurality of clock signals. 13. Claims 10, 11 or 12
The information processing apparatus according to claim 1, wherein the multi-phase clock generator is provided in the clock generation unit, between the clock generation unit and the information processing unit, or in the information processing unit. 14. The method according to claim 10, 11, 12, or 13 wherein the multi-phase clock generator synchronizes a phase with the first clock signal and has a predetermined frequency. An information processing apparatus, which generates a plurality of clock signals having different duty. 15. Claims 10, 11, and 12
In the paragraph [13], [13] or [14], the multi-phase clock generator generates a plurality of clock signals that are synchronized in phase with the first clock signal and that have different duties with different frequencies. Information processing device. 16. Claims 10, 11 and 12
In the paragraph [13], [14] or [15], the multi-phase clock generator performs timing control with the third clock signal, and the second clock signal or the fourth clock signal or the other clock signal. An information processing apparatus, wherein a plurality of clock signals having different phases are generated by using the clock signal. 17. Claims 10, 11, and 12
In the paragraph (13), (13), (14), (15), or (16), the plurality of clock signals are two clock signals, and they are clock signals that do not overlap each other. apparatus. 18. Claims 10, 11, and 12
An information processing device according to any one of items (1), (13), (14), (15), and (16), wherein the plurality of clock signals are clock signals that overlap each other by a predetermined time difference.