JP2717577B2 - Sector mark detection device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for detecting a sector mark which is a mark for identifying a position of a sector (sector area) of a disk-shaped recording medium such as an optical disk, and more particularly to an apparatus for detecting a sector mark. Even when the recording surface of the recording medium is scratched or dusty, the sector mark can be effectively detected and the detection accuracy can be improved, and the number of registers can be reduced compared to the conventional circuit. The present invention relates to a sector mark detection device capable of reducing the size.

[Conventional technology]

On a disc-shaped recording medium such as an optical disk, a sector mark for identifying each sector that divides a track is recorded. In this sector mark, for example, first, 1 data is continuously recorded for a predetermined number of bits a (“1111...”), And subsequently, 0 data is continuously recorded for a predetermined number of bits b. (“0000...”), And subsequently, data of consecutive 1s and consecutive 0s are alternately recorded by a predetermined number of bits c, d.

FIG. 3 and FIG. 4 are circuit diagrams showing a conventional sector mark detecting device for detecting such a sector mark.

3 uses a shift register 1 to which data is input and gates 2, 3, 4,... To which an output from the shift register 1 is input, and outputs from the gates 2, 3, 4,. A sector mark detection signal is output from the AND gate 5 when all become High level.

FIG. 4 shows a counter 6 to which data is input, D flip-flops 7, 8, 9, and 10 for directly outputting a signal given from the counter 6 in synchronization with a clock, and each D flip-flop 7 And a combination circuit 11 that outputs a high-level signal when the output from .about.10 has a predetermined pattern, and receives the output from the combination circuit 11 and the output from the shift register 12 to which the clock is input, and outputs the sector mark. And an AND gate 13 for outputting a detection signal.

[Problems to be solved by the invention]

However, in the detection device shown in FIG. 3, it is necessary to take in all the patterns of the sector mark into the shift register 1, and the number of storage elements required for the number of bits of the sector mark increases the circuit scale. Further, if the recording medium disk is scratched or dusty, the detected pattern does not completely match the pattern of the sector mark, and the detection becomes impossible.
The detection device of FIG. 4 is also similar to that of FIG. 3 in that it is susceptible to scratches and dust on the recording medium. In the apparatus shown in FIG. 4, for example, when a pattern "1111" and a pattern "0000" are input, the mutual order of the patterns cannot be determined, so that the sector mark detection signal is output in any order. There is a risk of false detection.

The present invention has been made to solve the above problems, and can effectively detect a sector mark and improve detection accuracy even when a recording surface of a recording medium is scratched or dusty. It is another object of the present invention to provide a sector mark detecting device capable of reducing the number of registers and reducing the circuit scale as compared with the conventional one.

[Means for solving the problem]

The present invention relates to a sector mark detection device for detecting, in a read signal from a recording medium, a sector mark in which a pattern in which a signal (1) is continuous and a pattern in which a signal (0) is continuous are repeated. A detection counter for counting (1) and a detection counter for counting the signal (0) of each pattern are provided. Each detection counter counts the signal (1) or the signal (0), and the count value is normal. When a predetermined number of bits is reached in relation to the number of bits in the pattern,
An enable signal for disabling reset is provided to a detection counter that counts a subsequent pattern, and a reset generation counter that starts counting clocks and measures time in association with the detection counter starting counting is provided. A reset signal is provided from a reset generation counter to the detection counter to which the enable signal is to be provided after the time at which the enable signal is provided when the pattern counted by the detection counter is a normal signal. When none of the detection counters is reset and the counting of the signal (1) and the signal (0) is completed in all of the sector mark patterns, a sector mark detection signal is output. An apparatus for detecting a sector mark, comprising:

In the above description, the continuation of the signal (1) and the continuation of the signal (0) at the sector mark are defined as pattern a, pattern b, and pattern.
.., and a plurality of detection counters A, B, C,... respectively corresponding to the respective patterns a, b, c,. In connection with the start of counting, each pattern a, b, c,
A plurality of reset occurrence counters A ', B', C ',... Which are selected each time counting is performed, and when any of the detection counters A, B, C,. The enable signal is applied only to the next detection counter, and when any of the reset occurrence counters A ′, B ′, C ′,... Has counted a predetermined time, the detection counters A, B , C,... Can be provided with a reset signal.

[Action]

According to the above means, the sector marks in which the data of 1 and 0 are continuously and alternately recorded for each of the predetermined patterns a, b, c... The sector mark detection signal is output only when the pattern (1) is detected.

That is, when data indicating a legitimate sector mark is input, for example, detection counters A and
B, C ... count input 1 or 0 data by a predetermined number of bits a ', b', c '... and sequentially output enable signals to the next stage counter. Therefore, even if the reset signal is input from the reset generation counter section, the counter receiving the enable signal continues the counting operation, and the last stage counter outputs the sector mark detection signal.

When data that is not a legitimate sector mark is input, an enable signal is not output from each of the counters A, B, C,... Of the detection counter unit. No mark detection signal is output.

Each of the counters A, B, C,... Has the number of times of inputting data of 1 or 0 among the input data.
A ′, b ′, c ′... Determined in relation to the number of bits of
, An enable signal or a sector mark detection signal is output. Therefore, even if the input data does not completely match each of the sector mark patterns a, b, c, etc., a sector mark detection signal is output if the input data matches to some extent. It is possible to effectively detect a sector mark even when a part of the data is missing.

〔Example〕

 Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a configuration of a sector mark detection device according to one embodiment of the present invention, and FIG. 2 is a time chart for explaining the operation of the sector mark detection device of FIG.

In FIG. 1, reference numeral 21 denotes a 01 detection counter, which comprises a plurality of 1 or 0 detection counters A, B, C, D. These detection counters A to N are connected in parallel with respect to the input of the read data and the system clock, and keep the counters in operation regardless of the enable signal output from the EN terminal of each counter (regardless of the input of the reset signal). Are connected in cascade. This enable signal is transmitted to each detection counter A, B, C, D ...
(Except for N), data of 1 or 0 is detected from the read data in synchronization with the clock, and when the number of times of detection reaches a predetermined number predetermined for each counter, all the data from the next stage onward are detected. This is output to the detection counter. However, since the enable signal is input to the detection counters after C through the AND gates 22c, 22d... 22n, the enable signal is input to the detection counters C, D. Is limited to the case where the enable signal is output from all the detection counters at the preceding stage. The detection counter N at the last stage outputs a sector mark detection signal when 1 data from the read data is input a predetermined number of times.

Reference numeral 23 denotes a reset generation counter, which is a plurality of reset signal output counters A ', B', C ', D', E '(hereinafter, abbreviated as "counters A', B ', C'..."). Are connected in parallel. That is, each counter A ', B', C '
.. Are supplied with a clock and a selection signal from the multiplexer 24. The multiplexer 24 includes detection counters A, B, C, D
Receive a mode signal output from the M terminal of... And output a control signal (selection signal) for operating any of the counters A ′, B ′, C ′. The output side of each of the counters A ', B', C ',... Is connected to the input side of the OR gate 25. Thereby, each counter A ',
When a reset signal is output from one of the counters B ', C',..., A reset signal is input from the OR gate 25 to each of the detection counters A to N.

Next, the operation of the present embodiment will be described with reference to the time chart of FIG.

FIG. 3C shows a waveform indicating read data input to each of the detection counters A to N, and FIG.
It is a waveform showing a clock input to N and each counter A ', B', C '... For reset output. In addition, FIG.
Is a period corresponding to the number of bits (the number of clock pulses) of each pattern a, c, e in which one data of each pattern of the sector mark is continuous, and the bit of each pattern b, d in which 0 data is continuous. A period corresponding to the number (the number of clock pulses) is shown.

In FIG. 1, when data indicating a sector mark is input to each of the detection counters A to N in the 01 detection counter 21,
Each of the detection counters A to N is 1 in synchronization with the clock.
Alternatively, the counting of the number of times data of 0 is input is started. Then, the detection counter A counts up to a predetermined bit number a '(in this embodiment, a bit number slightly smaller than the bit number corresponding to the period a) in relation to the bit number corresponding to the period a. When the enable signal
E1 (FIG. 2 (e)) is output. The enable signal E1 is not input to the detection counters after the detection counter C by the AND gates 22c to 22n, but is only input to the detection counter B.

When data "1" is input to the detection counter A (the sector mark is set to start with data 1), a mode signal (for example, "1") is output from the detection counter A.
0 "). The multiplexer 24 receives the mode signal and sends a selection signal to the reset output counter A 'to start the operation of the counter A'. And a period α slightly shorter than the period of the pattern a in FIG.
(See FIG. 2 (j)) when counting up to the number of clock pulses corresponding to (see FIG. 2 (a))
Is output. When the α reset signal is output, the other detection counters except the detection counter B to which the enable signal E1 from the detection counter A is input are reset, and the enable signals E3 and E4 and the sector mark detection signal are output. Is prevented.

Next, when the data of the pattern b in FIG. 2B is input, the detection counter B starts counting the number of times of detection of the “0” signal. Then, when "0" is counted only for data having a bit number b 'shorter than the bit number of the pattern b data, the enable signal E2 is output. This enable signal E2 is
It is output only to the detection counter C via the AND gate 22c. Further, the detection counter B outputs a mode signal (for example, “00”) to the multiplexer 24 simultaneously with the start of the counting. The multiplexer 24 receives this mode signal and outputs a selection signal to the β counter B ′ to start the operation of the β counter B ′. The β counter B 'counts the number of clock pulses, and when counting up to the number of clock pulses corresponding to a period β slightly shorter than the number of bits in the period of the pattern b (see FIG. 2A), a β reset signal (See FIG. 2 (k)). By this β reset signal,
The detection counters D,... Other than the detection counters B and C to which the enable signals E1 and E2 have been input earlier.
N is reset to prevent output of the enable signal E4 and the sector mark detection signal from these detection counters D and N.

Thereafter, similarly, the detection counters C and D respectively count the number of times of inputting "1" data and the number of times of inputting "0" data, and determine the predetermined number of times (bits corresponding to the periods d and e in FIG. 2B). When counting up to the number of bits slightly smaller than the number, the enable signals E3 and E4 (FIG. 2 (g))
And (f)). Similarly, the reset output γ counter C ′, δ counter D ′, and ε counter E ′ are respectively γ and C in FIG.
When counting the number of clock pulses corresponding to δ and ε,
It outputs a γ reset signal, a δ reset signal, and an ε reset signal (see FIGS. 2 (l), (m) and (n)).

By the above operation, each detection counter A, B, C, D
Operate sequentially, and enable signals E1, E2, E3 are output. After the enable signals are output, α, β, γ... Reset signals are output, that is, by the combination of these signals, a normal signal is output. When input, the detection counters A, B, C, D... Operate sequentially without being reset. When the number of times of inputting "1" data is counted to a bit number slightly smaller than the bit number corresponding to the period e shown in FIG. 2B by the last detection counter N, the sector mark detection signal ( (See FIG. 2 (i)).

On the other hand, when data other than the legitimate sector mark is input, the reset signal counter A '() is output before the enable signal E1 (E2, E3...) Is output from the detection counter A (B, C. B ′, C ′...) Output the α (β, γ...) Reset signal and reset the detection counters B, C, D.

As described above, according to the present embodiment, the reset signals are output when the predetermined periods α to ε have elapsed by the reset output counters A ′ to E ′. Therefore, each detection counter A, B, C...
Unlimited "1" beyond each period (see Fig. 2 (b))
Alternatively, there is no danger that the number of times of inputting "0" is counted and a sector mark detection signal is erroneously output. Further, by using the reset occurrence counter 23, the subsequent detection counter cannot perform the counting operation unless the enable signal is output from the previous detection counter, so that "111 ..." detected from the input data is used. And the order between the patterns of “000...” Is determined to be the same as the order of the patterns of regular sector marks, and the accuracy of sector mark detection is improved.

In this embodiment, the detection counters A, B, C.
Outputs the enable signal and the sector mark detection signal because the number of times of input of data "1" or "0" is determined by the data of each pattern a, b, c... Of the sector mark (FIG. 2 (b)
), The number of times is slightly smaller than the number of times a ′, b ′, c ′...
For example, even when a part of data is missing due to a scratch or dust attached to a recording medium, a sector mark can be effectively detected.

Further, in this embodiment, it is possible to count 2 ⁿ bits of data in the counter using the n memory elements, e.g., FIG. 3 the 2 ⁿ memory devices to count the 2 ⁿ bits of data as It is possible to greatly reduce the circuit scale as compared with a conventional device that requires the above.

〔effect〕

In the present invention, when the enable signal is not supplied from the preceding stage counter, the count operation is prevented by the reset signal from the reset generation counter section. Therefore, the sector mark detection signal is output only when the order between the patterns obtained from the input data matches the order between the patterns a, b, c... Of the sector mark, and the accuracy of the sector mark detection is improved. Will be improved.

Further in accordance with the present invention, 2 ⁿ using n storage elements
It is also possible to count bit data, so that the number of storage elements can be reduced and the circuit scale can be reduced as compared with a conventional sector mark detection device.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a sector mark detection device according to one embodiment of the present invention, FIG. 2 is a time chart for explaining the operation of the sector mark detection device of FIG. 1, FIG. FIG. 4 is a circuit diagram showing a conventional sector mark detection device. 21 ... 01 detection counter, 23 ... reset occurrence counter,
A, B, C, D, N ... detection counter, A ', B', C ', D', E '...
…counter.

Claims (2)

(57) [Claims] 1. A sector mark detecting apparatus for detecting, in a read signal from a recording medium, a sector mark in which a pattern in which a signal (1) is continuous and a pattern in which a signal (0) is continuous are repeated. A detection counter for counting the signal (1) and a detection counter for counting the signal (0) of each pattern are provided. Each detection counter counts the signal (1) or the signal (0), and the count value is normal. When a predetermined number of bits is reached in relation to the number of bits of the pattern,
An enable signal for disabling reset is provided to a detection counter that counts a subsequent pattern, and a reset generation counter that starts counting clocks and measures time in association with the detection counter starting counting is provided. A reset signal is provided from a reset generation counter to the detection counter to which the enable signal is to be provided after the time at which the enable signal is provided when the pattern counted by the detection counter is a normal signal. When none of the detection counters is reset and the counting of the signal (1) and the signal (0) is completed in all of the sector mark patterns, a sector mark detection signal is output. An apparatus for detecting a sector mark, comprising: 2. A continuation of the signal (1) at a sector mark,
The continuation of the signal (0) is defined as pattern a, pattern b, pattern c, ...
, And a plurality of the detection counters A, B, C,... Respectively corresponding to the respective patterns a, b, c,.
In connection with the start of counting of A, B, C, ..., each pattern a, b, c, ...
A plurality of reset occurrence counters A ', B', C ',... Which are selected for each of the counts are provided, and when any of the detection counters A, B, C,. , The enable signal is given only to the next detection counter, and when any of the reset occurrence counters A ′, B ′, C ′,.
2. The sector mark detecting device according to claim 1, wherein a reset signal is supplied to all of A, B, C,.