JP2703902B2 - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JP2703902B2
JP2703902B2 JP62171253A JP17125387A JP2703902B2 JP 2703902 B2 JP2703902 B2 JP 2703902B2 JP 62171253 A JP62171253 A JP 62171253A JP 17125387 A JP17125387 A JP 17125387A JP 2703902 B2 JP2703902 B2 JP 2703902B2
Authority
JP
Japan
Prior art keywords
circuit
output
input
bit
semiconductor integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP62171253A
Other languages
Japanese (ja)
Other versions
JPS6415942A (en
Inventor
清一 森神
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62171253A priority Critical patent/JP2703902B2/en
Publication of JPS6415942A publication Critical patent/JPS6415942A/en
Application granted granted Critical
Publication of JP2703902B2 publication Critical patent/JP2703902B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Description

【発明の詳細な説明】 ［産業上の利用分野］ 本発明は半導体集積回路に関し、特に半導体集積回路
の出力ビット数をボンディングにより変更することがで
きるようにした半導体集積回路に関する。 ［従来の技術］ Ｎビットのデータを入出力する従来の半導体集積回路
は、第５図に示すように、トライステートバッファから
なる出力回路C11と入力初段NOR回路C12とをI/O手段とし
て備え、これらを制御信号S11、S12で制御して適宜動作
可能状態にさせ、I/OピンD1を介してデータの入出力を
行うようにしている。 第６図はこのような半導体集積回路の平面図を示す。
Ｎ型半導体の場合、VCCレベルのリードフレーム１とア
イランド２とが接続され、チップ３上の各ビットの入出
力用又は電源用のパッドＰは、I/OピンD1及びGNDピンD2
等に、例えば、ワイヤボンディングＷによって接続され
ている。 ［発明が解決しようとする問題点］ 上述した従来の半導体集積回路においては、入出力で
きるデータのビット数がチップ毎に固定的に定められて
いる。しかしながら、近年、この種の半導体集積回路の
ビット数として多種多様な長さが要求されるようになっ
てくると、ビット数が固定的に定められた従来の半導体
集積回路では汎用性に欠け、コストも上昇する等の問題
点があった。 本発明はかかる問題点に鑑みてなされたものであっ
て、１つのチップで入出力ビット数を適宜変更すること
ができ、汎用性が優れ、これによりコスト低減を図るこ
とができる半導体集積回路を提供することを目的とす
る。 ［問題点を解決するための手段］ 本発明に係る半導体集積回路は、各ビット毎に設けら
れた入出力回路及び入出力パッドと、少なくとも一部の
前記入出力回路に設けられ、電源電圧及び接地電圧のい
ずれか一方の電圧印加で前記入出力回路を動作可能状態
にし、他方の電圧印加で動作停止状態にする入出力制御
回路と、この入出力制御回路に前記電圧を印加するため
のボンディングの専用パッドとを備えている。 ［作用］ 本発明においては、専用パッドを電源電圧のピン又は
接地電圧のピンにボンディングすることにより、特定の
入出力回路を動作停止状態にしたり、動作可能状態にす
ることができるので、上記入出力回路を所望の数だけ動
作可能状態にさせることにより、チップ自体は何ら変え
ずに入出力可能なビット数を変更することができる。こ
のため、チップの汎用性が高まり、コストの低減を図る
ことができる。 ［実施例］ 次に、本発明の実施例について添付の図面を参照して
説明する。第１図及び第２図は夫々本発明の実施例に係
る半導体集積回路の平面図及び９ビット目の入出力制御
回路の構成図である。この実施例では入出力データ数と
して８ビット又は９ビットの２通りの選択が可能な例を
示している。D9は９ビット目の入出力ピン、D2はGNDピ
ン、P1は９ビット目の入出力回路制御用の専用パッド、
P2は９ビット目の入出力パッドである。なお、チップ３
の基板としてＮ型半導体基板を使用しているため、アイ
ランド２はVCCレベルとなっている。 専用パッドP1は、第２図に示すように、NAND回路C16
の一方の入力及びNOT回路C13を介してNOR回路C17の一方
の入力に夫々接続されている。NAND回路C16の他方の入
力には制御信号S11が入力され、NOR回路C17の他方の入
力には制御信号S12が入力されている。そして、NAND回
路C16の出力はNOT回路C14を介して９ビット目の出力回
路C11の制御端子に与えられている。また、NOR回路C17
の出力はNOT回路C15を介して入力初段NOR回路C12の一方
の入力に与えられている。NOR回路C12の他方の入力に
は、出力回路C11の出力が与えられている。 この場合には、第１図に実線で示すように、専用パッ
ドP1はGNDピンD2とワイヤボンディングによって接続さ
れる。このような接続を行うと、専用パッドP1がGNDレ
ベルD2、即ちロウレベルとなるのでNAND回路C16の出力
はハイレベルとなり、更にNOT回路C14により節点N11は
ロウレベルとなり、９ビット目の出力回路C11に入力さ
れる。また、NOT回路C13の出力がハイレベル、NOR回路C
17の出力がロウレベル、NOT回路C15の出力がハイレベル
であるから、節点N12はハイレベルとなる。 第３図は、第２図の出力回路C11、入力初段NOR回路C1
2の更に詳細を示す回路図である第３図において、節点N
11がロウレベルであるから、NOT回路C21を介した節点N1
3はハイレベル、NOR回路C22を介した節点N14はロウレベ
ル、NOT回路C23を介した節点N15はハイレベルとなり、
Ｐチャネル型MOSFETQ11はオフする。同様に、節点N11が
ロウレベルであるから、NAND回路C24を介した節点N16は
ハイレベル、NOT回路C25を介した節点N17はロウレベル
となり、Ｎチャネル型MOSFETQ12はオフする。これによ
り、D9の９ビット目の入出力節点はハイインピーダンス
状態となり、９ビット目の出力回路C11は不活性化され
る。従って、８ビット出力の半導体集積回路として使用
するときは、９ビット目の出力回路C11は不活性化され
る。 次に、９ビット出力の半導体集積回路として使用する
場合について説明する。まず、第１図に破線で示すよう
に９ビット目の入出力回路制御用専用パッドP1をVCCピ
ンにワイヤボンディングし、９ビット目の入出力パッド
P2は９ビット目の入出力ピンD9にワイヤボンディングす
る。そうすると、第２図において入出力回路制御用の専
用パッドP1はVCCレベル、即ちハイレベルとなる。専用
パッドP1がハイレベルとなるとNAND回路C16はNOT回路と
して機能するようになる。そうすると、節点N11のレベ
ルはNOT回路の機能を有する回路C16,C14を通して制御信
号S11のレベルと同レベルとなり、９ビット目の出力回
路C11は通常の出力回路と同様に、制御信号S11によって
動作する。また、節点N10のレベルはNOT回路C13により
ロウレベルとなり、C17のNOR回路はNOT回路として機能
するようになる。従って、節点N12のレベルはNOT回路の
機能を有する回路C17,C15を通して制御信号S12のレベル
と同レベルとなり、９ビット目の入力初段回路C12は通
常の入力回路として動作するようになる。 第４図は本発明の第２の実施例の出力回路C30を示
す。この実施例が前述の実施例と異なる点は、Ｐチャネ
ル型MOSFET及びＮチャネル型MOSFETの素子数が減少した
ことにある。 これにより、節点N11のレベルがロウレベルになる
と、NAND回路C31を介した節点N12はハイレベルとなり、
Ｐチャネル型MOSFETQ11はオフとなる。 また、NOT回路C32、NOR回路C34を介したN14の節点N14
はロウレベルとなり、Ｎチャネル型MOSFETQ12はオフと
なり、出力回路C30の出力はハイインピーダンス状態と
なり、出力回路C30を不活性化することができる。 なお、前述の各実施例は８ビット出力と９ビット出力
とを切換える半導体集積回路を例として説明したが、８
ビット出力及び９ビット出力に限らず、任意のビットに
適用可能であることはいうまでもない。 また、前述の各実施例はＮ型の半導体基板を使用して
いるため、アイランドはVCCレベルとなっていたが、Ｐ
型の半導体基板を用いた場合は、アイランドはGNDレベ
ルとなり、この場合も本発明を同様に適用することがで
きる。その他、本発明の要旨の範囲内で種々の変形が可
能であることはいうまでもない。 ［発明の効果］ 以上説明したように、本発明によれば、１つのチップ
における専用パッドのボンディングの仕方によって、任
意のビットを取扱うことができるので、チップの汎用性
を高めることができ、コスト低減に寄与することができ
る。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit in which the number of output bits of a semiconductor integrated circuit can be changed by bonding. [Prior Art] A conventional semiconductor integrated circuit that inputs and outputs N-bit data includes an output circuit C11 composed of a tristate buffer and an input first-stage NOR circuit C12 as I / O means, as shown in FIG. These are controlled by control signals S11 and S12 so as to be appropriately operable, and data is input / output via I / O pin D1. FIG. 6 shows a plan view of such a semiconductor integrated circuit.
In the case of an N-type semiconductor, the lead frame 1 at the VCC level and the island 2 are connected, and the input / output or power supply pad P of each bit on the chip 3 is connected to the I / O pin D1 and the GND pin D2.
For example, they are connected by wire bonding W. [Problems to be Solved by the Invention] In the conventional semiconductor integrated circuit described above, the number of data bits that can be input and output is fixedly determined for each chip. However, in recent years, when a variety of lengths are required as the number of bits of this type of semiconductor integrated circuit, conventional semiconductor integrated circuits in which the number of bits is fixed are lacking in versatility, There were problems such as an increase in cost. The present invention has been made in view of such a problem, and a semiconductor integrated circuit that can appropriately change the number of input / output bits in one chip, has excellent versatility, and can achieve cost reduction. The purpose is to provide. [Means for Solving the Problem] A semiconductor integrated circuit according to the present invention includes an input / output circuit and an input / output pad provided for each bit, and a power supply voltage and An input / output control circuit for activating the input / output circuit by applying one of the ground voltages and halting the operation by applying the other voltage, and bonding for applying the voltage to the input / output control circuit With dedicated pads. [Operation] In the present invention, a specific input / output circuit can be put into an operation stop state or an operable state by bonding a dedicated pad to a power supply voltage pin or a ground voltage pin. By allowing the desired number of output circuits to operate, the number of bits that can be input and output can be changed without changing the chip itself. Therefore, the versatility of the chip is enhanced, and the cost can be reduced. Example Next, an example of the present invention will be described with reference to the accompanying drawings. FIG. 1 and FIG. 2 are a plan view of a semiconductor integrated circuit and a configuration diagram of a ninth bit input / output control circuit, respectively, according to an embodiment of the present invention. This embodiment shows an example in which the number of input / output data can be selected from two types of 8 bits or 9 bits. D9 is a 9th bit input / output pin, D2 is a GND pin, P1 is a 9th bit dedicated pad for input / output circuit control,
P2 is a 9th bit input / output pad. Note that chip 3
Since the N-type semiconductor substrate is used as the substrate, the island 2 is at the V CC level. The dedicated pad P1 is connected to the NAND circuit C16 as shown in FIG.
And one input of a NOR circuit C17 via a NOT circuit C13. The control signal S11 is input to the other input of the NAND circuit C16, and the control signal S12 is input to the other input of the NOR circuit C17. The output of the NAND circuit C16 is given to the control terminal of the ninth bit output circuit C11 via the NOT circuit C14. Also, NOR circuit C17
Is provided to one input of an input first-stage NOR circuit C12 via a NOT circuit C15. The output of the output circuit C11 is given to the other input of the NOR circuit C12. In this case, as shown by a solid line in FIG. 1, the dedicated pad P1 is connected to the GND pin D2 by wire bonding. When such a connection is made, the output of the NAND circuit C16 becomes high level because the dedicated pad P1 becomes the GND level D2, that is, the low level, and the node N11 becomes low level by the NOT circuit C14, and the ninth bit output circuit C11 Is entered. Also, the output of the NOT circuit C13 is high level, and the NOR circuit C
Since the output of 17 is low and the output of NOT circuit C15 is high, node N12 is high. FIG. 3 shows the output circuit C11 and the input first-stage NOR circuit C1 shown in FIG.
In FIG. 3 which is a circuit diagram showing further details of FIG.
Since 11 is at the low level, the node N1 via the NOT circuit C21
3 is high level, node N14 via NOR circuit C22 is low level, node N15 via NOT circuit C23 is high level,
P-channel type MOSFET Q11 turns off. Similarly, since the node N11 is at the low level, the node N16 via the NAND circuit C24 is at the high level, the node N17 via the NOT circuit C25 is at the low level, and the N-channel MOSFET Q12 is turned off. As a result, the input / output node at the ninth bit of D9 enters a high impedance state, and the ninth bit output circuit C11 is inactivated. Therefore, when used as an 8-bit output semiconductor integrated circuit, the ninth bit output circuit C11 is inactivated. Next, a case where the semiconductor integrated circuit is used as a 9-bit output semiconductor integrated circuit will be described. First, as shown by the broken line in FIG. 1, the ninth bit input / output circuit control dedicated pad P1 is wire-bonded to the VCC pin, and the ninth bit input / output pad
P2 is wire-bonded to the ninth bit input / output pin D9. Then, in FIG. 2, the dedicated pad P1 for controlling the input / output circuit is at the V CC level, that is, the high level. When the dedicated pad P1 becomes high level, the NAND circuit C16 functions as a NOT circuit. Then, the level of the node N11 becomes the same level as the level of the control signal S11 through the circuits C16 and C14 having the function of the NOT circuit, and the ninth bit output circuit C11 is operated by the control signal S11 similarly to the normal output circuit. . Further, the level of the node N10 becomes low level by the NOT circuit C13, and the NOR circuit of C17 functions as a NOT circuit. Therefore, the level of the node N12 becomes the same level as the level of the control signal S12 through the circuits C17 and C15 having the function of the NOT circuit, and the ninth-bit input initial stage circuit C12 operates as a normal input circuit. FIG. 4 shows an output circuit C30 according to a second embodiment of the present invention. This embodiment differs from the above-described embodiment in that the number of elements of the P-channel MOSFET and the N-channel MOSFET is reduced. Thereby, when the level of the node N11 becomes low level, the node N12 via the NAND circuit C31 becomes high level,
The P-channel MOSFET Q11 is turned off. A node N14 of N14 via a NOT circuit C32 and a NOR circuit C34.
Becomes low level, the N-channel type MOSFET Q12 turns off, the output of the output circuit C30 enters a high impedance state, and the output circuit C30 can be inactivated. In each of the embodiments described above, a semiconductor integrated circuit that switches between 8-bit output and 9-bit output has been described as an example.
It goes without saying that the present invention is not limited to the bit output and the 9-bit output, but can be applied to any bit. In each of the above-described embodiments, the N-type semiconductor substrate was used, so that the island was at the V CC level.
When a semiconductor substrate of the mold type is used, the island is at the GND level, and in this case, the present invention can be similarly applied. It goes without saying that various modifications are possible within the scope of the present invention. [Effects of the Invention] As described above, according to the present invention, an arbitrary bit can be handled depending on the bonding method of the dedicated pad in one chip, so that the versatility of the chip can be improved and the cost can be increased. It can contribute to reduction.

【図面の簡単な説明】 第１図は本発明の実施例を示す平面図、第２図は同じく
その入出力制御回路のブロック図、第３図は同入出力制
御回路の更に詳細な回路図、第４図は本発明の他の実施
例を示す出力回路の詳細な回路図、第５図は従来の入出
力回路のブロック図、第６図は従来のチップの平面図で
ある。 1;リードフレーム、2;アイランド、3;チップ、D9;9ビッ
ト目の入出力ピン、D2;GNDピン、P1;9ビット目の入出力
回路制御用専用パッド、P2;9ビット目の入出力パッド、
C11;9ビット目の出力回路、C12;9ビット目の入力初段NO
R回路BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a plan view showing an embodiment of the present invention, FIG. 2 is a block diagram of the input / output control circuit, and FIG. 3 is a more detailed circuit diagram of the input / output control circuit. FIG. 4 is a detailed circuit diagram of an output circuit showing another embodiment of the present invention, FIG. 5 is a block diagram of a conventional input / output circuit, and FIG. 6 is a plan view of a conventional chip. 1; Lead frame, 2; Island, 3; Chip, D9: 9th bit input / output pin, D2: GND pin, P1: 9th bit input / output circuit control dedicated pad, P2: 9th bit input / output pad,
C11: 9th bit output circuit, C12: 9th bit input first stage NO
R circuit

Claims (1)

(57)【特許請求の範囲】 １．各ビット毎に設けられた入出力回路と、前記各ビッ
ト毎に設けられた入出力パッドと、少なくとも一部の前
記入出力回路に設けられ電源電圧及び接地電圧のいずれ
か一方の電圧が印加されると前記入出力回路を動作可能
状態にし、同他方の電圧が印加されると前記入出力回路
を動作停止状態にする入出力制御回路と、この入出力制
御回路に前記電圧を印加するための専用パッドとを備
え、前記専用パッドを電源電圧及び接地電圧のいずれと
ボンディングするかによって使用するビット数を変更し
得るようにしたことを特徴とする半導体集積回路。(57) [Claims] An input / output circuit provided for each bit, an input / output pad provided for each bit, and one of a power supply voltage and a ground voltage provided to at least some of the input / output circuits is applied. An input / output control circuit that puts the input / output circuit into an operable state, and puts the input / output circuit into an operation stop state when the other voltage is applied; and A dedicated pad, wherein the number of bits used can be changed depending on whether the dedicated pad is bonded to a power supply voltage or a ground voltage.
JP62171253A 1987-07-10 1987-07-10 Semiconductor integrated circuit Expired - Lifetime JP2703902B2 (en)

Priority Applications (1)

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JP62171253A JP2703902B2 (en) 1987-07-10 1987-07-10 Semiconductor integrated circuit

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Application Number Priority Date Filing Date Title
JP62171253A JP2703902B2 (en) 1987-07-10 1987-07-10 Semiconductor integrated circuit

Publications (2)

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JPS6415942A JPS6415942A (en) 1989-01-19
JP2703902B2 true JP2703902B2 (en) 1998-01-26

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JP62171253A Expired - Lifetime JP2703902B2 (en) 1987-07-10 1987-07-10 Semiconductor integrated circuit

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Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6825698B2 (en) * 2001-08-29 2004-11-30 Altera Corporation Programmable high speed I/O interface

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58127366A (en) * 1982-01-25 1983-07-29 Hitachi Ltd Ic memory

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Publication number Publication date
JPS6415942A (en) 1989-01-19

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