JPS6415942A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPS6415942A
JPS6415942A JP62171253A JP17125387A JPS6415942A JP S6415942 A JPS6415942 A JP S6415942A JP 62171253 A JP62171253 A JP 62171253A JP 17125387 A JP17125387 A JP 17125387A JP S6415942 A JPS6415942 A JP S6415942A
Authority
JP
Japan
Prior art keywords
output
circuit
reaches
high level
low level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62171253A
Other languages
Japanese (ja)
Other versions
JP2703902B2 (en
Inventor
Seiichi Morigami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62171253A priority Critical patent/JP2703902B2/en
Publication of JPS6415942A publication Critical patent/JPS6415942A/en
Application granted granted Critical
Publication of JP2703902B2 publication Critical patent/JP2703902B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

PURPOSE:To change the number of bits capable of being input and output without altering chip itself at all, to improve the general-purpose properties of the chip and to reduce cost by bonding an exclusive pad to a pin for supply voltage and a pin for ground voltage. CONSTITUTION:In an example in which two kinds of selection of eight bits or nine bits is enabled as the number of input/output data, an output from a NAND circuit C16 reaches a high level because an exclusive pad P1 reaches a GND level D2, a low level, when the exclusive pad P1 is connected to the GND pin D2 by wire bonding, and a node N11 reaches the low level by a NOT circuit C14, and an output circuit C11 for ninth bit is input. Since an output from a NOT circuit 13 reaches the high level, an output from a NOR circuit 17 the low level and an output from the NOT circuit C15 the high level, a node N12 reaches the high level. Since the node N11 reaches the low level, a P channel type MOSFETQ11 is turned OFF. Likewise, an N channel type MOSFETQ12 is turned OFF Accordingly, the output circuit C11 for ninth bit is inactivated.
JP62171253A 1987-07-10 1987-07-10 Semiconductor integrated circuit Expired - Lifetime JP2703902B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62171253A JP2703902B2 (en) 1987-07-10 1987-07-10 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62171253A JP2703902B2 (en) 1987-07-10 1987-07-10 Semiconductor integrated circuit

Publications (2)

Publication Number Publication Date
JPS6415942A true JPS6415942A (en) 1989-01-19
JP2703902B2 JP2703902B2 (en) 1998-01-26

Family

ID=15919893

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62171253A Expired - Lifetime JP2703902B2 (en) 1987-07-10 1987-07-10 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JP2703902B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011165214A (en) * 2001-08-29 2011-08-25 Altera Corp Programmable high-speed input/output interface

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58127366A (en) * 1982-01-25 1983-07-29 Hitachi Ltd Ic memory

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58127366A (en) * 1982-01-25 1983-07-29 Hitachi Ltd Ic memory

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011165214A (en) * 2001-08-29 2011-08-25 Altera Corp Programmable high-speed input/output interface
US8487665B2 (en) 2001-08-29 2013-07-16 Altera Corporation Programmable high-speed interface
US8829948B2 (en) 2001-08-29 2014-09-09 Altera Corporation Programmable high-speed I/O interface
JP2015043229A (en) * 2001-08-29 2015-03-05 アルテラ コーポレイションＡｌｔｅｒａ Ｃｏｒｐｏｒａｔｉｏｎ Programmable high-speed input/output interface
JP2015043230A (en) * 2001-08-29 2015-03-05 アルテラ コーポレイションＡｌｔｅｒａ Ｃｏｒｐｏｒａｔｉｏｎ Programmable high-speed input/output interface
JP2016173866A (en) * 2001-08-29 2016-09-29 アルテラ コーポレイションＡｌｔｅｒａ Ｃｏｒｐｏｒａｔｉｏｎ Programmable high-speed input and output interface
US9473145B2 (en) 2001-08-29 2016-10-18 Altera Corporation Programmable high-speed I/O interface

Also Published As

Publication number Publication date
JP2703902B2 (en) 1998-01-26

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