JP2915319B2 - Semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device capable of reducing input capacitance as viewed from an external signal input pin. 2. Description of the Related Art Conventionally, ceramic packages and plastic molded packages have been used as packages for large-scale integrated circuits (LSI) and the like. Whichever package is used, there is only one bonding pad for the same external signal on the semiconductor chip, and a plurality of bonding pads for each signal are provided, for example, on the peripheral portion in the short direction of the semiconductor chip. Was usually there. FIG. 2 is a partial plan view showing a structure in which a conventional semiconductor chip on which bonding pads are arranged is sealed in a ceramic package. Explaining the configuration of this device, the semiconductor chip 1 is an integrated circuit element incorporating an integrated circuit for a 256 kbit dynamic RAM, and the semiconductor chip 1 is sealed in a ceramic package 2. [0006] A peripheral portion of the semiconductor chip 1 in the lateral direction is A
A 0 signal bonding pad 3a, an A2 signal bonding pad 3b, and an A1 signal bonding pad 3c are arranged at an interval from each other, and a peripheral portion of the ceramic package 2 in the short direction is provided with an A0 signal bonding pad. The A0 signal terminal 4a, the A2 signal terminal 4b, and the A1 signal terminal 4c are spaced apart from each other so as to correspond to the bonding pad 3a, the A2 signal bonding pad 3b, and the A1 signal bonding pad 3c. A0 signal bonding pads 3a and A0
The signal terminal 4a is connected to the signal terminal 4a by a bonding wire 6a.
2 signal bonding pad 3b and A2 signal terminal 4b
Is bonded by the bonding wire 6b, and the A1 signal bonding pad 3c and the A1 signal terminal 4c are bonded by the bonding wire 6c. The A0 signal terminal 4a, the A2 signal terminal 4b, and the A1 signal terminal 4c are the fifth, sixth, and seventh pins for external signal input exposed on the outer surface of the package, respectively. (Not shown). here,
In the figure, indicates a pin number. Fifth pin,
An A0 signal, an A2 signal, and an A1 signal, which are external signals, are input to the sixth pin and the seventh pin, respectively. The A0 signal, A2 signal, and A1 signal are, for example, an address signal, a data signal, a control signal, and the like. FIG. 3 is a partial plan view showing a structure in which a conventional semiconductor chip having bonding pads is sealed in a plastic mold package. The configuration of this device will be described. A semiconductor chip 1 in which an integrated circuit for a 256 kbit dynamic RAM is incorporated
Are enclosed in a plastic mold package 3. A0 signal terminals 5a and 5A are provided on a plastic mold package 3 so as to surround the semiconductor chip 1.
The two-signal terminal 5b and the A1 signal terminal 5c are provided at an interval from each other. A0 signal bonding pad 3a and A0 signal terminal 5a are connected to bonding wire 6a.
Accordingly, the A2 signal bonding pad 3b and the A2 signal terminal 5b are bonded by the bonding wire 6b, and the A1 signal bonding pad 3c and the A1 signal terminal 5c are bonded by the bonding wire 6c. The A0 signal terminal 5a, A2 signal terminal 5b, and A1 signal terminal 5c are the fifth, sixth, and seventh pins for external signal input, respectively, which are exposed on the outer surface of the package. (Not shown). here,
In the figure, indicates a pin number. Here, it should be noted that the arrangement of the signal terminals is different between the ceramic package and the plastic mold package due to structural restrictions. Since only one bonding pad for the same external signal is provided on the conventional semiconductor chip 1, when the semiconductor chip 1 is sealed in the ceramic package 2 as shown in FIG. Bonding pad 3a and A0 signal terminal 4a can be bonded without the bonding wire 6a coming into contact with the semiconductor chip 1, but when the semiconductor chip 1 is sealed in the plastic mold package 3 as shown in FIG. Are the A0 signal bonding pads 3a and A0
When bonding to the signal terminal 5a with the bonding wire 6a, the bonding wire 6a crosses the edge of the semiconductor chip 1 over a long range,
During molding, the bonding wire 6a is connected to the semiconductor chip 1
There is a problem of contact with the edge portion . FIG. 4 is a plan view showing the structure of a semiconductor device which has solved the above-mentioned problems. The feature of this semiconductor device is that a semiconductor chip 1 in which a 256 kbit dynamic RAM integrated circuit is incorporated has an A0
This is different from the bonding pad arrangement on the semiconductor chip 1 in FIGS. 2 and 3 in that another A0 signal bonding pad 3d is arranged in addition to the signal bonding pad 3a . Also, they are connected by internal wiring 7 on the semiconductor chip 1 and the bonding A0 signal pads 3a and A0 signal bonding pads 3d. FIG. 5 is a partial plan view showing the structure when the semiconductor device of FIG. 4 is sealed in a ceramic package. In the figure, the bonding pad 3a for A0 signal and the terminal 4a for A0 signal are bonded at the shortest distance by a bonding wire 6a.
The signal bonding pad 3d is an empty pad. FIG. 6 is a partial plan view showing a structure when the semiconductor device of FIG. 4 is sealed in a plastic mold package. In the figure, an A0 signal bonding pad 3d and an A0 signal terminal 5a are
a, the A0 signal bonding pad 3d is used instead of the A0 signal bonding pad 3a. In this case, A0
The signal bonding pad 3a becomes an empty pad. As described above, since two identical external signal bonding pads are arranged on one semiconductor chip 1, even if the form of the package is changed, the same bonding pads are selected to select the same bonding pad. The external signal bonding pad and the terminal can be easily bonded at the shortest distance, and a short circuit between the bonding wire and the edge of the semiconductor chip can be avoided, so that highly reliable wire bonding can be performed. Such a bonding method is called a multiple bonding pad method. [0015] SUMMARY OF THE INVENTION] Figure 7 is a partial plan view showing further detail the structure of a semiconductor device several ball <br/> down loading pad method of FIG. 4 has been applied. In the figure, the input buffer circuit 20 and the A for A0 signal on the semiconductor chip 1
0 clock buffer circuit 40 is provided for signal input buffer circuit 20 is p-channel MOSFET
21, n-channel MOSFET 23 and p-channel M
OSFET 22 and power supply line 24 to which power supply voltage VDD is applied
It is composed of The bonding pad 3d for A0 signal is connected to the bonding pads 3a for A0 signal by the internal wiring 7, the connection point between the bonding pad 3a and the internal wiring 7 for A0 signal on the input side of the input buffer circuit 20 are connected, the output side of the input buffer circuit 20 is connected to the clock buffer circuit 40. [0018] In the conventional semiconductor device multiple Bonn loading pad method is applied, normally two are bonding pads for one external signal input pins as this, internal wiring extending in the longitudinal direction of the semiconductor chip 1 but one, since the further input buffer circuit is provided one, the input capacitance seen from the external signal input pins (internal volume), the capacitance of the capacitor of the two bonding pads and one internal wiring and 1 is composed of a gate capacitance of the inputs buffer circuit, there is a problem that the input capacitance seen from the external signal input pins is significantly increased impair the high speed of the element. In some cases, an input protection circuit is provided for each bonding pad. In this case, however, there is a problem that the input capacitance as viewed from the external signal input pin further increases. The present invention has been made in view of the above points, and is one of a plurality of external signal bonding pads provided at a peripheral portion on a semiconductor chip and spaced apart from each other. The present invention aims to obtain a semiconductor device in which the input capacitance as viewed from each of a plurality of external signal bonding pads is reduced, in which a signal inputted to the internal buffer circuit is supplied to the internal buffer circuit by a selection circuit. A semiconductor device according to the present invention comprises a plurality of external signal bonding pads provided on a semiconductor chip at an interval from each other, and a plurality of external signal bonding pads provided on the semiconductor chip. a plurality of input buffer circuits corresponding to and connected to the one-to-one for use bonding pads, respectively, and the internal buffer circuit provided on the semiconductor chip, <br/> Outputs of the plurality of input buffers circuits on a semiconductor chip provided to be connected in common to a node, the internal buffer a signal corresponding to the signal appearing on one of the output nodes of the input buffer circuit connected to bonding pads for external signals of a plurality of bonding pads for external signal And a selection circuit for outputting to the circuit. In the present invention, since an input buffer circuit is interposed between each of the plurality of external signal bonding pads and the selection circuit, the input buffer circuit is viewed from the external input signal pin corresponding to the external signal bonding pad. The input capacitance has only a capacitance component from the external signal bonding pad to the input buffer circuit connected thereto. An embodiment of the present invention will be described below with reference to the drawings. In the description of this embodiment, a description of a part that overlaps with the description of the related art will be appropriately omitted. FIG. 1 is a partial plan view showing the structure of a semiconductor device according to one embodiment of the present invention. The structure of this embodiment is shown in FIG.
The following points are different from the configuration of the semiconductor device of the first embodiment. That is, A is newly added on the semiconductor chip 1.
Input buffer corresponding to the 0 signal bonding pad 3d
A NAND circuit 30 is provided.
Is provided. Input buffer circuit 10 is composed of p-channel MOSFET11 and n-channel MOSFET13 and p-channel MOSFET12 and the power supply voltage supply line 14 for VDD is supplied. NAND circuit 3
0 is p-channel MOSFET 31 and n-channel MO
SFET 33, p-channel MOSFET 32 and n-channel
Channel MOSFET 34 and a power supply voltage VDD.
And a source line 35. [0023] The input buffer circuit 20 NAND circuit 30
Is connected to one input of which, the bonding pad 3d for A0 signal is connected to the input buffer circuit 10, NAN by the input buffer circuit 10 is the internal wiring 70
It is connected to the other input side of the D circuit 30. NAND
The output side of the circuit 30 is connected to the clock buffer circuit 40. In such a configuration, for example, in order to input an external signal, when bonding to the A0 signal bonding pad 3d, the A0 signal bonding pad 3d is used.
a is in an open state (floating “L”), the gate potentials of the p-channel MOSFET 31 and the n-channel MOSFET 33 become “H” level, and the NAND circuit 30 outputs the A0 signal input to the A0 signal bonding pad 3 d. Clock buff
The key circuit 40 operates. [0025] At this time, the input capacitance seen from the external signal input pins corresponding to the bonding A0 signal pad 3d, 3a is composed of only the gate capacitance of the input buffer circuit 10 and the capacitance of the A0 signal bonding pad 3d Is done. Therefore, the input capacitance viewed from the external signal input pin is reduced to 以下 or less as compared with the conventional semiconductor device, and high-speed operation of the semiconductor device is realized. [0026] In the above embodiment, the bonding pad 3d for A0 signals, but shows the case of connecting the input buffer circuits 10, 20 to the respective 3a, the input buffer circuit 10 and the bonding pad 3d for A0 signal And the A0 signal bonding pad 3a and the input buffer
An input protection circuit may be provided between the input protection circuit 20 and the input / output circuit 20, respectively. In this case, the same effects as those of the above embodiment can be obtained. Further, in the above embodiment, the input buffer circuit shown case is a NOT circuit, may be using the input buffer circuit of another type, instead of the circuit. In the above embodiment, the semiconductor chip is 2
The case of a semiconductor integrated circuit device incorporating an integrated circuit for a 56 kbit dynamic RAM has been described.
The element structure incorporated on the semiconductor chip may be of various types such as a MOS type and a bipolar type. In these cases, the same effects as those of the above-described embodiment can be obtained. In the above embodiment, the case where two identical external signal bonding pads are arranged on one semiconductor chip has been described.
A plurality of the same external signal bonding pads may be arranged. In this case, the same effects as those of the above embodiment can be obtained. As described above, the present invention provides a plurality of external signal bonding pads provided on a semiconductor chip at intervals from each other and a plurality of external signal bonding pads provided on the semiconductor chip. 1 for each bonding pad
A plurality of input buffer circuits corresponding to and connected to the pair 1, the internal buffer circuit provided on the semiconductor chip, the semiconductor chip provided commonly connected to the output node of the plurality of input buffers circuits, a plurality of external since there is provided a selection circuit for outputting a signal corresponding to the signal appearing on one of the output nodes of the input buffer circuit connected to bonding pads for external signal among the signal bonding pad to the internal buffer circuit, external The input capacitance seen from the external input signal pin corresponding to the signal bonding pad has only a capacitance component from the external signal bonding pad to the input buffer circuit connected thereto, and this input capacitance
This has the effect of reducing the amount . As a result, the speed and economy of the semiconductor device can be improved.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a partial plan view showing a structure of a semiconductor device according to one embodiment of the present invention. FIG. 2 is a partial plan view showing a structure in which a conventional semiconductor chip having bonding pads arranged therein is sealed in a ceramic package. FIG. 3 is a partial plan view showing a structure when a conventional semiconductor chip on which bonding pads are arranged is sealed in a plastic mold package. FIG. 4 is a plan view showing a structure of a semiconductor device to which a multiple bonding pad method is applied. 5 is a partial plan view showing a structure when the semiconductor device to which the multiple bonding pad method of FIG. 4 is applied is sealed in a ceramic package. 6 is a partial plan view showing a structure when the semiconductor device to which the multiple bonding pad method of FIG. 4 is applied is sealed in a plastic mold package. FIG. 7 is a partial plan view showing the structure of the semiconductor device to which the multiple bonding pad method of FIG. 4 is applied in more detail; [Description of Signs] 1 semiconductor chip, 3a-3d bonding pad, 4a-4c / 5a-5c signal terminal, 6a-
6c bonding wire, 10, 20 input buffer
§ circuit, 30 NAND circuit (selection circuit) 40
The clock buffer circuit (internal circuit).

Claims (1)

(57) [Claims] A semiconductor chip, a plurality of external signal bonding pads provided on the semiconductor chip at intervals, a plurality of input buffer circuits provided on the semiconductor chip, an internal buffer circuit provided on the semiconductor chip, An output node of the input buffer circuit, which is provided on the semiconductor chip so as to be commonly connected to output nodes of the plurality of input buffer circuits, and is connected to one of the plurality of external signal bonding pads. A selection circuit for outputting a signal corresponding to the signal appearing in the internal buffer circuit to the plurality of external signal bonding pads and the plurality of input buffer circuits in a one-to-one correspondence. an input node of the bonding pads and the input buffer circuit is connected, the input buffer Wherein the road-internal buffer
The semiconductor device corresponds to a plurality of circuits .