JP2615836B2 - Image signal processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image signal processing device such as a facsimile or a photographic transmission / reception device.

2. Description of the Related Art Image signal data to be recorded by a facsimile or a plotter usually handles binarized data in many cases. Recently, however, a photographic recording device for directly recording multi-valued data for recording with gradation has been developed. Have been coming. For example, a photographic transmission / reception device corresponds to this. In this case, laser light is used as a light source for recording, and data with gradation is recorded by the magnitude of the analog voltage applied to the optical modulator.

In such a device, when the multi-position data and the binary data are mixed and used, the multi-value data is used for recording image data having gradation such as photographic information, and the binary data is used for character information. It is used for recording of image data having no gradation as described above.

For example, binary data is used for adding a date, time, a transmission destination, etc., before recording image information in a facsimile or the like.

Conventionally, a configuration shown in FIG. 8 has been known as these methods. The configuration will be briefly described below.

In FIG. 8, reference numeral 1 denotes input image signal data of image information;
Represents output image signal data such as 8 bits per pixel used for recording photographic information processed by the image memory controller 9;
The image signal is converted into an analog signal by the A converter 10. Reference numeral 4 denotes a bus for the CPU unit 11, which is an image memory control unit 9,
The character memory control unit 12 and the switching control unit 14 are connected.
The image memory control unit 9 has an image memory, and one pixel 8
It stores bit multi-level image signal data. 5 is output 2
With the value data, the output image signal 6 adjusted to the maximum and minimum levels of the D / A converter 10 via the level converter 13 is generated.
Reference numeral 7 denotes an input image signal to the recording control unit 15, which is inputted via the switching control unit 14 between a multi-value output image signal 3 of photograph information and a binary output image signal 6 of character data.

In the above configuration, the image signal data 1 input from an external device or a computer (not shown) is temporarily stored in the image memory in the image memory control unit 9.

For example, a photographic transmission / reception device or the like stores image signal data (for one document) of a document to be received in an image memory in the image memory control unit 9 and stores information such as an ID, date, and comment attached to the document. The data is stored in the character memory in the character memory control unit 12 from the CPU 11 via the CPU bus 4. The recording of the image information is performed by first converting the binary image signal data of the character data into a recording control unit.
At the time of recording via 15, the changeover control unit 14 connects the changeover switch to a and records. Next, when recording multi-valued image signal data of photograph information, the changeover switch is set to b.
The multi-level image signal data in the image memory control unit 9 is extracted, converted into an analog signal by the D / A converter 10, and recorded by the recording control unit 15.

However, in this case, the character data is usually obtained by expanding a font pattern obtained by a character generator in a binary memory and reading the binary data in this memory each time recording is performed. The recording of such character data is at most about one line, and it is not possible to record long data such as comments and outlines attached to photographic information.

As described above, in the conventional image signal processing apparatus, the multi-value data forming the photographic information and the binary data forming the character data are stored in separate memories and are switched and extracted by a switch or the like. The control for recording the image data of any length from an arbitrary recording position to an arbitrary length is complicated. In particular, for the recording of binary data such as characters, conversion to a multi-valued data level is required. This has the disadvantage that the processing system cannot be shared. It is also difficult to arbitrarily designate the character data pitch and line spacing of character data and record them.

SUMMARY OF THE INVENTION In view of the above problems, the present invention provides an image signal processing apparatus having a recording control unit for recording multi-valued data such as photographic information when recording image information in which multi-valued data and binary data are mixed. By converting the binary data into multi-valued data, a common image signal processing system is provided. In particular, by interpolating these image data to match the recording density of the recording control unit, The purpose is to obtain high-density image data.

Means for Solving the Problems The present invention relates to a storage means for dividing and storing multi-valued image data and binary image data with respect to input image data according to an address of the memory space, and the storage means. Addressing means for designating a reading start address of the image data stored in the memory space, and a first means for counting the recording length of each of the multi-valued image data and the two image data of the image data read from the storage means. Counter means, first switching means for instructing the storage means to select between the multi-valued image data and the binary image data in accordance with the recording length of the image data, and switching between the multi-valued image data and the binary image data Second counter means for reading and counting the number of pixels in the line direction in byte units and outputting a control signal; and binary image data stored in the storage means in byte units Address reading means for generating a bit-specified address by a control signal from the second counter means, and the address generating means instructing the binary image data read from the storage means in byte units. Data conversion means for converting the pixel data into pixel data for each bit, and further outputting the pixel data as multi-valued pixel data by bit expansion; and a second for switching the read start address by a control signal from the second counter means. Switching means, by switching the read start address of the storage means, to connect the multi-valued image data read from the storage means and the multi-valued pixel data from the data conversion means as continuous multi-valued image data, Further, interpolation processing means for performing density conversion of the multivalued image data by interpolation, and reading from the interpolation processing means. A digital / analog converter means for converting the digital image data issued to the analog image signals, is provided with a recording means for performing gradation recording based on the analog image signal the digital / analog conversion means has output.

Function The present invention is to store multi-valued data (for example, 1-bit data) when storing an image signal input through an external device or a digital line in a designated address space in a memory and recording it in a recording device capable of gradation recording. Gradation data such as pixel 8 bits) and 2
A counter that controls reading of value data (for example, data of one bit per pixel) according to each recording length, and generates a bit-by-bit address for a binary data signal stored in byte units. After decoding into bit-by-bit pixel data by the address specified by the counter and converting it into byte data of 8 bits per pixel,
Further, by controlling the reading by updating the reading address in the line direction in accordance with the reading end signal in units of bytes of the binary pixel data, it is possible to easily manage the recording length of each of the image data. Can be
As a result, the recording of the multi-valued data and the binary data can be made common, and furthermore, high-density image data can be easily generated by interpolating or duplicating these image data. It is.

Embodiment Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1A shows a block configuration of an image signal processing apparatus according to an embodiment of the present invention.

In FIG. 1 (a), reference numeral 20 denotes a CPU, a line control unit 21, an image memory control unit 23, a multi-value data counter control unit 25, a binary data counter control unit 24, a timing control via a CPU bus 22. It is connected to the unit 26. The line control unit 21 is for taking in image data processed by an external computer, a scanner, or the like and transmitted through a communication line or the like. This image data is stored in a memory in the image memory control unit 23.
The character / data counter control unit 24 is a counter arranged in the image memory control unit 23 for determining a line for reading character data. The read end signal 28 is connected to the image memory control unit 23. Similarly, the multi-valued data counter control unit 25 is a counter arranged in the image memory control unit 23 for determining a read line of multi-valued data, and the reading end signal 37 is connected to the image memory control unit 23. I have. Reference numeral 26 denotes a timing control unit, which includes an image memory control unit 23, a character data counter control unit 24, and a multi-value data counter control unit.
Controlling the read timing of 25, connecting an enable signal 31 for reading multi-valued data, an enable signal 32 for reading binary data, a read clock 33 for reading these image data, and a synchronization signal 35 I have. Reference numeral 29 denotes an input synchronization signal, which is a basic timing signal for operating the timing control unit 26, and is a main synchronization signal generated by rotation of a main scanning motor or the like. Reference numeral 34 denotes an interpolation processing unit which performs interpolation processing or overlap processing on image data read by the image memory control unit 23. Reference numeral 27 denotes a digital-to-analog converter that converts the image data 36 interpolated by the interpolation unit 34 into an analog image signal. 28
A recording control unit records an analog image signal on recording paper such as photographic paper.

 The operation of the above configuration will be described below.

Image data sent via a digital line or the like is controlled by the CPU 20 via the line control unit 21 so as to be stored in a memory in the image memory control unit 23. This memory is a memory that shares multi-valued data and binary data, and divides and stores each area by an address in this memory space.
That is, gradation data such as photographic information and binary data such as character data are stored by separating the address space of the memory.

Prior to recording, first, the CPU 20 executes the processing via the CPU bus 22.
The number of recording lines for gradation data (multi-value data) such as photographic information is set in the multi-value data counter control unit 25, and the number of recording lines for character data (binary data) is set in the binary data counter control unit 24. . These parameters can be specified as a format determined in the photograph information sent from the line control unit 21.

Next, when the start of operation is designated by the CPU 20 to the timing control unit 26, an enable signal 31 for reading multi-valued data is output in synchronization with the input synchronization signal 29. First, the multi-valued data in the image memory control unit 23 is output. Is read.

At this time, since the multi-level data counter control unit 25 is also connected to the synchronization signal 35 together with the similar enable signal 31,
The number of synchronization signals during the enable period is counted, and the reading of the multi-value data is completed by the end signal 37 of the read line. As described above, when the reading of the multi-valued data is completed, the above-described enable signal 31 is turned off, and the timing control unit 26 is turned off.
An enable signal 32 for reading binary data is output, and the binary data in the image memory 23 is read in the same manner. At this time, since the synchronous signal 35 is also connected to the binary data counter control unit 26 together with the same enable signal 32, the synchronous signal during the enable period is counted, and the binary signal is read by the read line end signal 28. When the data reading is completed, the enable signal 32 is turned off.

When reading multi-valued data, the read clock
The updating of the read address of the multi-value data in the image memory 23 and the timing of reading the data are given by 33. Similarly, in the case of reading the binary data, the read clock 33 is used.
Thus, reading of the binary data in the image memory 23 and the timing of reading the data are given.

The image data 30 processed by the image memory control unit 23 is subjected to an interpolation process by multiplication and averaging for each line at the time of multi-value data by an interpolation interpolation processing unit 34, and to a duplication process for each line at the time of binary data. By doing so, high-density image data is generated. That is, for example, when the sub-scanning line density in the line direction is 4.7 lines / mm, image data of 18.8 lines / mm can be substantially obtained by performing interpolation processing of four lines.

Further, referring to FIG.
The operation of reading the value data will be described.

As shown in the figure, when storing multi-valued data and binary data in an image memory by separating the area, the binary data is also stored in a byte configuration like the multi-valued data. On the other hand, in the case of multi-valued data, data for each byte may be read for an address in the main scanning direction (an image data string between synchronization signals), and the next line address is switched when reading of all data is completed. .

However, the binary data has an address in the main scanning direction.
First, MSB data in a 1-byte configuration, that is, D7 data is read out in order, and 1-byte data is multiplexed and switched to the last LSB data D0.
In other words, binary data can be read by reading each of the eight bit data and switching the next line address when the reading of the byte data is completed.

The image data 36 that has gone through each process in this way is converted to a D / A converter 27.
The recording is performed on the recording paper by a recording device using a laser light source or the like by the recording control unit 28 via the.

FIGS. 2 and 3 show more detailed block diagrams of the image memory control unit 23 in the configuration of FIG.

In FIG. 2, reference numeral 55 denotes an image memory for storing multi-valued image data and binary image data by dividing an area according to an address of the memory space, and reference numerals 70 and 71 denote address lines connected to the image memory 55, respectively. , Data lines. 51,5
Reference numerals 6 and 60 denote a bidirectional data buffer for a data signal 54 for writing and reading from the CPU to the image memory 55, an address buffer for an address signal 58, and a buffer for a control signal 59, respectively. An R / W control unit 61 controls writing and reading of the image memory 55, and switches between writing and reading of the image memory 55 by a control signal line 68. On the other hand, 50 is an output data buffer for reading data from the image memory 55, and 53 is its output data. Reference numerals 52, 57, and 73 denote latches, counters, and address buffers for setting read addresses of the image memory from the CPU via the data signal 54, respectively. 64 is a control line for setting the reading start address of the image memory 55,
65 is an address clock for updating the read address, 62 is a counter for counting the number of pixels read for one line by the data read clock 33, and 66 is a read end signal. Reference numeral 63 denotes an address signal buffer connected to the image memory 55 for performing address control in the line direction. The opening and closing of the control buffers 50, 51 and the like are controlled by an operation command signal 72 from the CPU, and the image memory 55 is set to a reading state during normal recording.

Further, in FIG. 3, reference numeral 75 denotes a latch for the output image signal 53 from the image memory 55, 78 denotes a buffer, and 30 denotes a converted output image signal which is output to the interpolation processing unit. Numeral 81 denotes a counter, which outputs 3-bit addressing signals 84, 85 and 86 in response to a one-line read end signal 66, which is connected to a multiplexer 76. 77 is a flip-flop, 2
The value data 92 is latched and converted into multi-value data via the buffer 79. Gate circuits 82 and 83 generate an address clock 65 for updating addresses when reading multi-valued data and when reading binary data. 88 is binary data /
Switching signal for reading multi-level data, 89 is output image signal
30 strobe signals.

The operation of the above configuration will be described below with reference to FIGS. 2 and 3.

FIGS. 4 and 5 are diagrams showing the operation timing of the configuration shown in FIG. 1. In particular, FIG. 5 shows the timing between the one-scan synchronization signals shown in FIG. The names and meanings of the signal lines are shown in FIGS.
It is the same as that shown in FIG.

When image data processed by an external computer or the like is sent via a digital line or the like, the image data is transferred to the image memory 55 in the image memory control unit 23 via the line control unit 21 by the CPU 20 and the binary data. Data is stored in such a manner that each area is divided into memory space addresses. This line control unit 21 converts serial transfer into parallel,
The CPU 20 is a control unit that performs a protocol conversion process for fetching data. For this reason, the number of lines and character data (binary data) to be recorded in the gradation data (multi-valued data) in the transmitted image data For example, if a format based on HDLC (High Level Data Link Control) procedure is used, the number of recording lines can be easily incorporated into photographic information and can be recognized as required parameter information. That is, the operation command signal 72 is
By pressing F, data buffer 51, address buffer 5
6, the control buffer 60 is opened and the data signal 54,
Address signal 58, control signal 59 is data signal 71,
Address signal 70 and control signal line 6 via R / W control unit 61
8 are connected to the image memory 55, and can be freely written and read from the CPU 20, and store image data from a predetermined address as described above.

On the other hand, the data buffer 50 and the address buffers 73 and 63 are closed, and external reading is prohibited.
That is, the image memory 55 has a structure that can be used as a memory that can be accessed from both directions.

After the image data for one document is stored in the image memory 55 in this way, before recording, predetermined parameters are set as follows.

The reading start address of the image memory 55 is set in the latch 52 via the control line 64. Since the size of the image data to be accommodated varies depending on the size of the photographic information, this is performed in order to effectively use the memory by deciding the leading address of the reading, so that no margin is formed on the recording paper. There are advantages. At this time, the storage start address of the multivalued data in the image memory 55 is the reading start address.

The number of multi-value data read lines is set in the multi-value data counter control unit 25, and the number of binary data read lines is set in the binary data counter control unit 24.

Next, the operation command signal 72 is turned on by the CPU 20, and when instructed by the timing control unit 26, the synchronization signal 35 is output in synchronization with the input synchronization signal 29, and at the same time, the enable signal 31 for reading multi-valued data is also turned on. I do. At this time, the multi-level / two-level data switching signal is also turned on, and contrary to the above operation, the data buffers 51, 56, and 60 are closed and the data signal 71 and the address signal 70 connected to the image memory 55 are stored in the data buffer, respectively. Five
0, it is controlled to be read by an external read clock via the address buffers 73 and 63.

As described above, the output signal data 53 is input to both the multiplexer 76 and the latch 75 during the reading period of the multi-level data, but since the multi-level / two-level switching signal 88 is ON as described above, the No output occurs, and the output recording signal 30 of multi-level data is obtained from the buffer 78.
Now, assuming that the number of pixels read in one line is 2048, the counter 62 counts the number of pixels in the line direction by the read clock 33, connects the line address signal 70 to the image memory 55 via the buffer 63, and updates the address. I will do it. However, when the read clock 33 for one line reaches 2048 pixels, the counter 62 outputs a pulse-shaped line read end signal 66, resets the counter 62 to the initial state, and specifies the 3-bit address 84, 85 by the counter 81. , 86 are operated by the output gate circuits 82, 83 so as to generate the address clock 65 in synchronization with the end of reading of one line. This means that the same operation is continued during the period of reading multi-value data, as can be seen from the timing shown in FIG. Here, the timing of the data strobe signal 89 is changed so that the output data 53 in the image memory 55 addressed by the read clock 33 is latched.

Thus, when recording multi-valued data, the enable signal 31
This is performed by counting the number of read lines designated by the multi-valued data counter control unit 25 during ON, that is, by counting the synchronization signal 35. When the content of the counter becomes "0", a pulse-like read end signal 37 is output and enabled. Turn off signal 31. This completes the reading of the multi-value data. Subsequently, the multi-value / two-value switching signal 88 is turned off, and reading of binary data is started.

Now, as an example of binary data recording, the case of character data shown in FIG. 6 will be described.

Normally, character fonts such as kanji are 16 × 16 dots, 24 × 24
It is represented by a pattern of dots, 32 x 32 dots, etc.
For example, if a 24 × 24 dot font pattern is used, this is a binary value of 3 bytes for each address (each byte is represented by 8 bits from D7 to D0 shown in the figure, for a total of 24 bits). In general, data having a data structure in which the data is divided into 24 addresses is adopted. That is,
If the kanji data shown in the example is arranged in the line direction, 24
Since data of one character is occupied in the address space of × 3 = 72, when this is stored in the image memory 55, when the number of pixels in the scanning direction to be recorded is 2048, “0” to “7FF” "
The byte data of data 1 is stored up to the address
From the address of "0" to the address of "FFF", the byte data of data 2 is similarly transferred.
May be stored. That is, when the character interval is "0", character data for 85 characters can be arranged,
If the character data of the next line is sequentially stored from the address "1800", a character array of two or more lines can be created.
Since these character data are stored in byte units, when reading, each bit, that is, D7
Into eight bits of data from D7 to D0, and D7, D6 ... D
The character pattern can be recorded by taking out in order of 0. With such an arrangement, the interval between characters can be changed for each dot by the address interval in the line direction to be stored, and the line interval can be easily set for each dot by the bit interval between characters.

Next, the reading of the character pattern and the operation of the data converter will be described with reference to FIG. As described above, the reading of the multi-level data is completed, and the multi-level / two-level switching signal 88 is output.
When turned off, the enable signal 32 for reading binary data is turned on in synchronization with the synchronization signal 35. At this time, the image memory
The image signal 53 read from 55 is input to both the multiplexer 76 and the latch 75, as in the case of reading multi-valued data.
No output from 8 occurs and output image signal 3 via buffer 79
0 will be obtained. As described above, assuming that the number of pixels read in one line of character data is also 2048, the counter 62 counts the number of pixels in the line direction by the read clock 33, and outputs the line address signal 70 to the image memory via the buffer 63. Connect to 55 and update its read address. In this case, since the counter 81 is in the initial state, the counter 81 has a 3-bit addressing signal.
84, 85, 86 remain "0". Therefore, the bit data of D7 is first selected from the byte data from the multiplexer 76 by the address designation signal, and the binary data signal 92
Is output. This signal latches the binary data 92 via the flip-flop 77 by the data strobe signal 89. Since the latched signal remains a binary data signal of logical level “0” or “1”, it is converted to a byte of “00” or “FF” via the buffer 79, that is, converted to multi-valued data. It is possible to configure a common recording processing system with the value data.

However, when the read clock 33 of one line reaches 2048 pixels, the counter 62 outputs a pulse-like line read end signal 66, resets the counter 62, and the counter 81 outputs 3-bit addressing signals 84, 85, 86. I do. The multiplexer 76 selects the bit data of D6 from the byte data according to the address designation signal and outputs the binary data signal 92. This continues the same operation up to the bit data of D0 as can be seen from the timing of FIG. However, when the reading of the bit data of D0 is completed, the reading of the byte data (data 1) is completed, and the gate is determined by the logic of the address designation signals 84, 85, 86 and the logic of the line reading end signal 66 output from the counter 62. The circuits 82 and 83 open to output the line address clock 65. Thus, the reading address of the next byte data (data 2) of the character data is set in the counter 57, and the reading of the character data from the image memory 55 is started.

Similarly, reading of binary data is an enable signal.
The reading is performed by counting the number of read lines set in the binary data counter control unit 24, that is, the synchronization signal 35 while the counter 32 is ON. When the content of the counter becomes "0", a pulse-like read end signal 38 is output. , Enable signal 32
F. This completes the reading of the binary data.

Next, the interpolation processing operation will be described with reference to the timing charts shown in FIG. 1 (a) and FIG.

The image data 30 read by the aforementioned image memory 55
Is input to the interpolation processing unit 34. For example, when the interpolation processing unit performs the interpolation processing of four lines, as shown in FIG. Then, interpolation processing of image data for each line is performed.
That is, in the case of multi-valued data, the lines ♯N and ♯ (N + 1) are used, and if the averaging data is ♯ (N, N + 1), ♯N, (♯N + ♯ (N, N + 1)) / 2, (♯ (N, N + 1)
+ ♯ (N + 1)) / 2 and ♯ (N + 1) are generated. This is normally performed using three line memories, and is performed by averaging the image data of the previous line and the image data of the current line.

Further, in the case of binary data, the same data for four lines are overlapped without performing averaging.
When a line memory similar to that described above is used, this may be simply repeated four times without averaging the data read from the line memory. That is, the interpolation processing unit 34 performs averaging for multi-valued data, and simply performs overlap processing for binary data. Switching between the multi-value data and the binary data can be performed by the same switching means as described above. According to this method, the density in the line direction is substantially quadrupled, and high-density image data can be reproduced. In this example, the case of the interpolation processing of four lines has been described.
Lines or 16 lines can be easily set. The high-density image data 36 obtained by this interpolation processing unit 34
Is converted into an analog signal by a digital / analog converter 27, and then recorded on a recording paper such as a photographic paper by a recording control unit.

As described above, according to the present embodiment, the common recording process can be configured by converting the binary data reading into byte data similar to the multi-valued data. The data is smoother, the binary data is sharper, and high quality recording is possible. In particular, in the recording of gradation data, it is possible to perform recording with inconspicuous scanning lines.

As described above, according to the present invention, image information in which multivalued data and binary data are mixed is divided into areas in the same memory and stored, and is recorded by a recording apparatus capable of gradation recording. At the time of reading, the reading of multi-valued data and the reading of binary data are switched and controlled according to each recording, and for the recording of binary data, pixel data for each bit is converted into the same format as byte data. To update the read address,
Further, by performing interpolation processing on the image data, high-quality image data can be reproduced, and recording of multi-value data and binary data can be shared.

In this case, the character spacing and the line spacing of binary data such as character data can be easily dealt with by changing the storage address of the character information on the image memory, and its industrial value is large.

[Brief description of the drawings]

FIG. 1 (a) is a block connection diagram of an image signal processing element according to one embodiment of the present invention, and FIG. 1 (b) is a conceptual diagram of a memory space which is a main part of the apparatus, and FIGS. Is a detailed block diagram of the main part of the apparatus, FIG. 4, FIG. 5, FIG. 7 is a timing waveform diagram of the main part of the apparatus, FIG. 6 is a diagram showing character data processing according to the present invention, FIG. FIG. 2 is a block connection diagram of a conventional image signal processing device. 20 ... CPU, 21 ... Line controller, 23 ... Image memory controller, 24
... Character data counter control unit, 25 ... Multi-value data counter control unit, 26 ... Timing control unit, 27 ... D / A converter, 28 ...
Recording control unit, 34 ... interpolation processing unit.

 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Kunio Sannomiya 3-10-1, Higashi-Mita, Tama-ku, Kawasaki-shi, Kanagawa Prefecture Inside Matsushita Giken Co., Ltd. (72) Katsuo Nakazato 3-chome, Higashi-Mita, Tama-ku, Kawasaki-shi, Kanagawa No. 10-1 Matsushita Giken Co., Ltd. (56) References JP-A-63-59679 (JP, A) JP-A-59-45765 (JP, A)

Claims (1)

(57) [Claims] 1. A storage means for dividing an input image data into multi-valued image data and binary image data in accordance with an address of the memory space, and storing the divided areas in common, and image data stored in the storage means. Address designating means for designating a read start address of a memory space of the first memory, first counter means for counting the recording length of each of multi-valued image data and binary image data of the image data read from the storage means, First switching means for instructing the storage means to select between multi-valued image data and binary image data according to the recording length of the image data, and the number of pixels in the line direction of the multi-valued image data and binary image data Second counter means for reading and counting the number of bytes for each byte unit and outputting a control signal; and reading the binary image data stored in the storage means for each byte unit. Address generation means for generating a bit-specified address in accordance with a control signal from the second counter means; and binary image data read out in bytes from the storage means, pixel data for each bit designated by the address generation means. Data conversion means for converting pixel data into multi-valued pixel data by bit expansion, a second switching means for switching the reading start address by a control signal from the second counter means, By switching the reading start address of the means, the multi-valued image data read from the storage means and the multi-valued pixel data from the data conversion means are connected as continuous multi-valued image data, and the multi-valued image data is further converted. Interpolation processing means for performing density conversion by interpolation, and a digital image read from the interpolation processing means A digital / analog conversion means for converting the data into an analog image signal, an image signal processing apparatus comprising a recording unit for performing gradation recording based on the analog image signal the digital / analog conversion means has output.