JP2615835B2 - Image signal processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image signal processing device such as a facsimile or a photographic transmission / reception device.

2. Description of the Related Art Image signal data to be recorded by a facsimile or a plotter usually handles binarized data in many cases. Recently, however, a photographic recording device for directly recording multi-valued data for recording with gradation has been developed. Have been coming. For example, a photographic transmission / reception device corresponds to this. In this case, laser light is used as a light source for recording, and data with gradation is recorded by the magnitude of the analog voltage applied to the optical modulator.

In such an apparatus, when multi-value data and binary data are mixed and used, the multi-value data is used for recording image data having gradation such as photographic information, and the binary data is used for character information. It is used for recording of image data having no gradation as described above.

For example, the binary data is used for adding a date, a time, a transmission destination, etc., before recording image information in a facsimile or the like.

Conventionally, the configuration shown in FIG. 7 is known as these methods. The configuration will be briefly described below.

In FIG. 7, reference numeral 1 denotes input image signal data of image information;
Represents output image signal data such as 8 bits per pixel used for recording photographic information processed by the image memory controller 9;
The image signal is converted into an analog signal by the A converter 10. Reference numeral 4 denotes a bus for the CPU unit 11, which is an image memory control unit 9,
The character memory control unit 12 and the switching control unit 14 are connected.
The image memory control unit 9 has an image memory, and one pixel 8
It stores bit multi-level image signal data. 5 is output 2
With the value data, the output image signal 6 adjusted to the maximum and minimum levels of the D / A converter 10 via the level converter 13 is generated.
Reference numeral 7 denotes an input image signal to the recording control unit 15, which receives a multi-value output image signal 3 of photographic information and a binary output image signal 6 of character data via the switching control unit 14.

In the above configuration, the image signal data 1 input from an external device, a computer, or the like (not shown) is temporarily stored in the image memory in the image memory control unit 9.

For example, a photographic transmission / reception device or the like stores image signal data (for one document) of a document to be received in an image memory in the image memory control unit 9 and stores information such as an ID, date, and comment attached to the document. The data is stored in the character memory in the character memory control unit 12 from the CPU 11 via the CPU bus 4. The recording of the image information is performed by first converting the binary image signal data of the character data into a recording control unit.
At the time of recording via 15, the changeover control unit 14 connects the changeover switch to a and records. Next, when recording the multi-valued image signal data of the photograph information, connect the changeover switch to b, take out the multi-valued image signal data in the image memory control unit 9, and convert it to an analog signal by the D / A converter 10. The data is converted and recorded by the recording control unit 15.

However, in this case, the character data is usually obtained by expanding a font pattern obtained by a character generator in a binary memory and reading the binary data in this memory each time recording is performed. The recording of such character data is at most about one line, and it is not possible to record long data such as comments and outlines attached to photographic information.

As described above, in the conventional image signal processing apparatus, the multi-value data forming the photographic information and the binary data forming the character data are stored in separate memories and are switched and extracted by a switch or the like. The control for recording the image data of any length from an arbitrary recording position to an arbitrary length is complicated. In particular, for the recording of binary data such as characters, conversion to a multi-valued data level is required. This has the disadvantage that the processing system cannot be shared. It is also difficult to arbitrarily designate the character data pitch and line spacing of character data and record them.

SUMMARY OF THE INVENTION In view of the above problems, the present invention provides an image signal processing apparatus having a recording control unit for recording multi-valued data such as photographic information when recording image information in which multi-valued data and binary data are mixed. An object of the present invention is to provide a common image signal processing system by converting binary data into multivalued data.

Means for Solving the Problems According to the present invention, a storage means for dividing an input image signal into multi-valued image data and binary image data based on an address of the memory space and sharing and storing the area, Address designating means for designating a reading start address of the memory space of the image data stored in the means, and multi-valued image data of the image data read from the storage means.
First counter means for counting the recording length of each of the value image data, and first switching for instructing the storage means to select the multi-valued image data or the binary image data in accordance with the recording length of the image data Means, second counter means for reading and counting the number of pixels in the line direction of the multi-valued image data and binary image data for each byte, and outputting a control signal; and 2 counters stored in the storage means for each byte. Address generating means for generating a bit-designated address in response to a control signal from the second counter means for reading the value image data; and converting the binary image data read from the storage means in byte units into the address generating means. Data conversion means for converting pixel data into pixel data for each bit designated by Second switching means for switching the read start address according to a control signal from the counter means, and switching between the multi-valued image data read from the storage means and the data from the data conversion means by switching the read start address of the storage means. Digital / analog conversion means for concatenating the pixel data of the value as continuous multi-valued image data and further converting the multi-valued image data into an analog image signal; Recording means for performing the tone recording, so that the image signal processing apparatus for performing the gradation recording can share the reading of the multi-value data and the reading of the binary data, and further, the image data read by the above-mentioned means. Is converted to analog data by a D / A converter, and then recorded on a recording paper such as a photographic paper by a recording unit. It is intended to record.

Function The present invention stores an image signal input through an external device, a digital line, or the like in a specified address space in a memory, and records the image signal with a recording device capable of gradation recording.
Multi-valued data (for example, gradation data such as 8 bits per pixel)
Counter for controlling the reading of binary data (data of one bit per pixel) according to each recording length, and generating a bit-by-bit address for a binary data signal stored in byte units. After decoding into bit-by-bit pixel data by the address specified by the counter and converting it into 8-bit byte data per pixel, the read address in the line direction is updated in accordance with the read end signal of the binary pixel data in byte units By performing the reading control in such a manner, the recording of the multi-value data and the binary data can be made common, and the recording length of an arbitrary length can be easily managed.

Embodiment Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1A shows a block configuration of an image signal processing apparatus according to an embodiment of the present invention.

In FIG. 1A, reference numeral 20 denotes a CPU via a CPU bus 22, a line control unit 21, an image memory control unit 23, a multi-value data counter control unit 25, a binary data counter control unit 24, and a timing control unit 26. It is connected to the. The line control unit 21 is for taking in image data processed by an external computer, a scanner, or the like and transmitted through a communication line or the like. This image data is stored in a memory in the image memory control unit 23.
The character data counter control unit 24 is a counter arranged in the image memory control unit 23 for determining a line for reading character data. The read end signal 28 is connected to the image memory control unit 23. Similarly, the multi-valued data counter control unit 25 is a counter arranged in the image memory control unit 23 for determining a read line of multi-valued data, and the reading end signal 37 is connected to the image memory control unit 23. I have. Reference numeral 26 denotes a timing control unit, which includes an image memory control unit 23, a character data counter control unit 24, and a multi-value data counter control unit.
Controlling the read timing of 25, connecting an enable signal 31 for reading multi-valued data, an enable signal 32 for reading binary data, a read clock 33 for reading these image data, and a synchronization signal 35 I have. Reference numeral 29 denotes an input synchronization signal, which is a basic timing signal for operating the timing control unit 26, and is a main synchronization signal generated by rotation of a main scanning motor or the like. The image data 30 thus obtained by the image memory control unit 23 is converted into analog data by the D / A converter 27, and is then recorded by the recording control unit 28 on recording paper such as photographic printing paper.

 The operation of the above configuration will be described below.

Image data sent via a digital line or the like is controlled by the CPU 20 via the line control unit 21 so as to be stored in a memory in the image memory control unit 23. This memory is a memory that shares multi-valued data and binary data, and divides and stores each area by an address in this memory space.
That is, gradation data such as photographic information and binary data such as character data are stored by separating the address space of the memory.

Prior to recording, first, the CPU 20 executes the processing via the CPU bus 22.
The number of recording lines for gradation data (multi-value data) such as photographic information is set in the multi-value data counter control unit 25, and the number of recording lines for character data (binary data) is set in the binary data counter control unit 24. . These parameters can be specified as a format determined in the photograph information sent from the line control unit 21.

Next, when an operation start is instructed by the CPU 20 to the timing control unit 26, an enable signal 31 for reading multi-valued data is output in synchronization with the input synchronization signal 29, and first the multi-valued data in the image memory control unit 23 is output. Is read.

At this time, since the multi-level data counter control unit 25 is also connected to the synchronization signal 35 together with the similar enable signal 31,
The number of synchronization signals during the enable period is counted, and the reading of the multi-value data is completed by the end signal 37 of the read line. As described above, when the reading of the multi-valued data is completed, the above-described enable signal 31 is turned off, and the timing control unit 26 is turned off.
An enable signal 32 for reading binary data is output, and the binary data in the image memory 23 is read in the same manner. At this time, since the synchronous signal 35 is also connected to the binary data counter control unit 26 together with the same enable signal 32, the synchronous signal during the enable period is counted, and the binary signal is read by the read line end signal 28. When the data reading is completed, the enable signal 32 is turned off.

When reading multi-valued data, the read clock
The updating of the read address of the multi-value data in the image memory 23 and the timing of reading the data are given by 33. Similarly, in the case of reading the binary data, the read clock 33 is used.
Thus, reading of the binary data in the image memory 23 and the timing of reading the data are given.

The image data 30 that has passed through the image signal processing unit is recorded on a recording paper by a recording device 28 via a D / A converter 27 by a laser light source or the like.

Further, referring to FIG.
The operation concept of reading value data will be described.

As shown in the drawing, when multi-valued data and binary data are stored in the image memory by separating the areas, the binary data is also stored in a byte configuration similarly to the multi-valued data. On the other hand, in the case of multi-valued data, it is only necessary to read the data of each byte for the address in the main scanning direction, and when the reading of all the data in the main scanning direction is completed, the next line address is switched.

However, the binary data has an address in the main scanning direction.
First, MSB data in a 1-byte configuration, that is, D7 data, is read out in order, and byte data is multiplexed and switched to the last LSB data (D0).

That is, the binary data can be read by switching the next line address at the end of reading the byte data by reading each of the eight bit data and reading the byte data.

2 and 3 show a more detailed configuration of the image memory control unit 23 in the configuration shown in FIG.

In FIG. 2, 55 is an image memory for storing multi-valued image data and binary image data by dividing an area according to the address of the memory space, 70 and 71 are address lines connected to the image memory 55, respectively. Data line. 51, 5
Reference numerals 6 and 60 denote a bidirectional data buffer for a data signal 54, an address buffer for an address signal 58, and a buffer for a control signal 59 for writing and reading from the CPU to the image memory 55, respectively. An R / W control unit 61 controls writing and reading of the image memory 55, and switches between writing and reading of the image memory 55 by a control signal line 68. On the other hand, 50 is an output data buffer for reading data from the image memory 55, and 53 is its output data. Reference numerals 52, 57, and 73 denote latches, counters, and address buffers for setting a read address of the image memory via the data signal 54 from the CPU. 64 is a control line for setting the reading start address of the image memory 55,
65 is an address clock for updating the read address, 62 is a counter for counting the number of pixels read for one line by the data read clock 33, and 66 is a read end signal. Reference numeral 63 denotes an address signal buffer connected to the image memory 55 for performing address control in the line direction. The opening and closing of the control buffers 50, 51 and the like are controlled by an operation command signal 72 from the CPU, and the image memory 55 is set to a reading state during normal recording.

Further, in FIG. 3, reference numeral 75 denotes a latch for the output image signal 53 output from the image memory 55, 78 denotes a buffer, and 30 denotes a converted output image signal which is output to the interpolation processing unit. Numeral 81 denotes a counter, which outputs 3-bit addressing signals 84, 85 and 86 in response to a one-line reading end signal 66, and is connected to a multiplexer 76. A flip-flop 77 latches the binary data 92 and converts it into multi-valued data via a buffer 79. Gate circuits 82 and 83 generate an address clock 65 for updating addresses when reading multi-valued data and when reading binary data. 88 is a switching signal for reading binary data / multi-valued data, and 89 is a strobe signal of the output image signal 30.

The operation of the above configuration will be described below with reference to FIGS. 2 and 3.

FIGS. 4 and 5 are diagrams showing the operation timing of the configuration shown in FIGS. 2 and 3, and particularly FIG. 5 shows the timing between one horizontal synchronizing signal shown in FIG. Things. The names and meanings of the signal lines are the first
This is the same as that shown in FIGS. 2, 3 and 3.

First, when image data processed by an external computer or the like is sent via a digital line or the like, the image data is sent to the CPU 2
In accordance with 0, the multi-valued data and the binary data are stored in the image memory 55 in the image memory control unit 23 via the line control unit 21 by dividing each area into memory space addresses.
The line control unit 21 is a control unit that performs a protocol conversion process for the CPU 20 to fetch data, such as converting serial transfer into parallel data. For this reason, gradation data (multi-valued data) in the transmitted image data is For example, the number of lines to be recorded and the number of recording lines for character data (binary data) can be easily incorporated into photographic information by using a format based on the HDLC (High Level Data Link Control) procedure. It can be recognized as required parameter information.

That is, by turning off the operation command signal 72 in this state, the data buffer 51, the address buffer 56, and the control buffer 60 are opened, and the data signal 54, the address signal 58,
Control signal 59 is data signal 71, address signal 70,
The CPU 20 is connected to the image memory 55 as a control signal line 68 via the R / W control unit 61, and can freely write and read from the CPU 20, and stores image data from a predetermined address as described above.

On the other hand, the data buffer 50 and the address buffers 73 and 63 are closed, and external reading is prohibited.
That is, the image memory 55 has a structure that can be used as a memory that can be accessed from both directions.

After the image data for one document is stored in the image memory 55 in this way, before recording, predetermined parameters are set as follows.

The reading start address of the image memory 55 is set in the latch 52 via the control line 64. Since the size of the image data to be accommodated varies depending on the size of the photographic information, this is performed in order to effectively use the memory by deciding the leading address of the reading, so that no margin is formed on the recording paper. There are advantages. At this time, the storage start address of the multivalued data in the image memory 55 is the reading start address.

The number of multi-value data recording lines is set in the multi-value data counter control unit 25, and the number of binary data recording lines is set in the binary data counter control unit 24.

Next, the operation command signal 72 is turned on by the CPU 20, and when instructed by the timing control unit 26, the synchronization signal 35 is output in synchronization with the input synchronization signal 29, and at the same time, the enable signal 31 for reading multi-valued data is also turned on. I do. At this time, the multi-level / two-level data switching signal is also turned on, and contrary to the above-described operation, the data buffers 51, 56, and 60 are closed and the data signal 71 and the address signal 70 connected to the image memory 55 are respectively the data buffer.
50, and are controlled so as to be read by an external read clock via the address buffers 73 and 63.

As described above, the output signal data 53 is input to both the multiplexer 76 and the latch 75 during the reading period of the multi-level data, but since the multi-level / two-level switching signal 88 is ON as described above, the No output occurs, and the output recording signal 30 of multi-level data is obtained from the buffer 78.
Now, assuming that the number of pixels read in one line is 2048, the counter 62 counts the number of pixels in the line direction by the read clock 33, connects the line address signal 70 to the image memory 55 via the buffer 63, and updates the address. I will do it. However, when the read clock 33 for one line reaches 2048 pixels, the counter 62 outputs a pulse-like line read end signal 66, resets the counter 62 to the initial state, and specifies the 3-bit address 84, 85 by the counter 81. , 86 are operated by the output gate circuits 82 and 83 so as to generate the address clock 65 in synchronization with the end of the reading of one line. This means that the same operation is continued during the period of reading multi-value data, as can be seen from the timing shown in FIG. Here, the timing of the data strobe signal 89 is changed so that the output data 53 in the image memory 55 addressed by the read clock 33 is latched.

Thus, when recording multi-valued data, the enable signal 31
This is performed by counting the number of recording lines set in the multi-value data counter control unit 25 during ON, that is, by counting the synchronization signal 35. When the content of the counter becomes "0", a pulse-like reading end signal 37 is output, and the enable is performed. Turn off signal 31. This completes the recording of the multi-value data. Followed by multi-value
The / 2 value switching signal 88 is turned off, and reading of the 2 value data is started.

Now, as an example of binary data recording, the case of character data shown in FIG. 6 will be described.

Normally, character fonts such as kanji are 16 × 16 dots, 24 × 24
It is represented by a pattern of dots, 32 x 32 dots, etc.
For example, if a 24 × 24 dot font pattern is used, this is a binary value of 3 bytes for each address (each byte is represented by 8 bits from D7 to D0 shown in the figure, for a total of 24 bits). In general, data having a data structure in which the data is divided into 24 addresses is adopted. That is,
If the kanji data shown in the example is arranged in the line direction, 24
Since data of one character is occupied in × 3 = 72 address spaces, when this is stored in the image memory 55, when the number of pixels to be recorded in the scanning direction is 2048, “0” is changed to “0”. 7F
Byte data of data 1 is stored up to the address of F ",
It is sufficient to store byte data of data 2 from addresses “800” to “FFF”, and similarly store byte data of data 3 from addresses “1000” to “17FF”. That is, when the character interval is "0", character data for 85 characters can be arranged,
If the character data of the next line is sequentially stored from the address "1800", a character array of two or more lines can be created.
Since these character data are stored in byte units, when recording, each bit from the byte data, that is, D7
Expands to 8 bit data up to D0, D7, D6, ...
・ Character pattern can be recorded by taking out in order of D0. With such an arrangement, the interval between characters can be changed for each dot by the address interval in the line direction to be stored, and the line interval can be easily set for each dot by the bit interval between characters.

Next, the operation of the character pattern recording and data conversion unit will be described with reference to FIG. As described above, when the recording of the multi-level data is completed and the multi-level / two-level switching signal 88 is turned off, the enable signal 32 for reading the binary data is turned on in synchronization with the synchronization signal 35. At this time, the image signal 53 read from the image memory 55 is similar to the multi-value data reading,
Input to both multiplexer 76 and latch 75,
Since the multi-value / two-value switching signal 88 is OFF, the output from the buffer 78 does not occur, and the output image signal 30 via the buffer 79 is obtained. As described above, assuming that the number of pixels read in one line of character data is also 2048, the counter 62 counts the number of pixels in the line direction by the read clock 33, and outputs the line address signal 70 to the image memory via the buffer 63. Connect to 55 and update its read address. In this case, since the counter 81 remains in the initial state, the counter 81 outputs the 3-bit addressing signals 84 and 8.
5, 86 remain “0”. For this reason, first of the byte data from the multiplexer 76 is
The bit data of D7 is selected, and the binary data signal 92 is output. This signal latches the binary data 92 via the flip-flop 77 by the data strobe signal 89. Since the latched signal remains a binary data signal of logical level “0” or “1”, it is converted to a byte of “00” or “FF” via the buffer 79, that is, converted to multi-valued data. It is possible to configure a common recording processing system with the value data.

However, when the read clock 33 of one line reaches 2048 pixels, the counter 62 outputs a pulse-like line read end signal 66, resets the counter 62, and sets the counter 81 to a 3-bit addressing signal 84, 85, 86.
Is output. The multiplexer 76 selects the bit data of D6 from the byte data according to the address designation signal and outputs the binary data signal 92. This continues the same operation up to the bit data of D0 as can be seen from the timing of FIG. However, when the reading of the bit data of D0 is completed, the recording of the byte data (data 1) is completed, and the gate is determined by the logic of the address designation signals 84, 85, 86 and the logic of the line reading end signal 66 output from the counter 62. The circuits 82 and 83 open to output the line address clock 65. Thus, the reading address of the next byte data (data 2) of the character data is set in the counter 57, and the reading of the character data from the image memory 55 is started.

Similarly, when the binary data is recorded, the enable signal 32 is
This is performed by counting the number of recording lines set in the binary data counter control unit 24 during ON, that is, by counting the synchronization signal 35. When the content of the counter becomes "0", a pulse-like reading end signal 38 is output, and enable. Turn off signal 32.
Thus, the recording of the binary data is completed, and the high-density image data 30 obtained by the image memory control unit 23 is stored in the D / A converter 2.
After being converted into an analog signal in step 7, the signal is recorded by a recording control unit 28 on a recording paper such as a photographic paper.

As described above, according to the present embodiment, the common recording process can be configured by converting the reading of the binary data into the same byte data as the multi-valued data. Since the data is converted by the D / A converter 27 as byte data of a logic level of “FF”, it is sufficient for modulation input of laser light or the like, and clear character recording is possible.

As described above, according to the present invention, image information in which multi-value data and binary data are mixed is stored by dividing an area in the same memory,
When this is recorded by a recording device capable of gradation recording, reading of multi-valued data and binary data is switched and controlled according to the respective recording lengths. After decoding into data, the data is converted into byte data of 8 bits per pixel, and the read address in the line direction is updated in accordance with the read end signal in units of bytes of the bit data. Data recording can be shared, and the recording length of each arbitrary length can be easily managed. In this case, the character interval and the line interval of binary data such as character data are also stored in the image memory. Free editing can be performed by simply changing the storage address of the above character information.

[Brief description of the drawings]

FIG. 1 (a) is a block diagram of an image signal processing device according to an embodiment of the present invention, and FIG. 1 (b) is a conceptual diagram of a memory space which is a main part of the image signal processing device. 4 is a detailed block diagram of the main part of the apparatus, FIGS. 4 and 5 are timing waveform diagrams of the main part of the apparatus, FIG. 6 is a diagram showing character data processing according to the present invention, and FIG. It is a block connection diagram of a signal processing apparatus. 20 ... CPU, 21 ... Line controller, 23 ... Image memory controller, 24
... Character data counter control unit, 25 ... Multi-value data counter control unit, 26 ... Timing control unit, 27 ... D / A converter, 28 ...
Recording control unit.

 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Kunio Sannomiya 3-10-1, Higashi-Mita, Tama-ku, Kawasaki-shi, Kanagawa Prefecture Inside Matsushita Giken Co., Ltd. (72) Katsuo Nakazato 3-chome, Higashi-Mita, Tama-ku, Kawasaki-shi, Kanagawa No. 10-1 Matsushita Giken Co., Ltd. (56) References JP-A-63-59679 (JP, A) JP-A-59-45765 (JP, A)

Claims (1)

(57) [Claims] 1. A storage means for dividing input image data into multi-valued image data and binary image data in accordance with an address of the memory space, storing the divided areas, and storing the image data stored in the storage means. Address designating means for designating a read start address of a data memory space; first counter means for counting the recording length of each of multi-valued image data and binary image data of the image data read from the storage means; First switching means for instructing the storage means to select between the multi-valued image data and the binary image data in accordance with the recording length of the image data, and a pixel in a line direction of the multi-valued image data and the binary image data Second counter means for reading and counting the number in byte units and outputting a control signal; and for reading binary image data stored in the storage means in byte units, Serial address generating means for generating an address of bits specified by the control signal from the second counter means, read from the storage means into bytes 2
Data conversion means for converting the value image data into pixel data for each bit designated by the address generation means, and further outputting the pixel data as multi-valued pixel data by bit expansion; and control from the second counter means A second switching unit that switches the read start address by a signal, and a multi-valued image data read from the storage unit and a multi-valued pixel data from the data conversion unit by switching the read start address of the storage unit. Are connected as continuous multivalued image data, and further, digital / analog conversion means for converting the multivalued image data into an analog image signal, and recording for performing gradation recording based on the analog image signal output from the digital / analog conversion means Image signal processing apparatus comprising: