JP2584054B2 - Parameter signal generator - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a parameter signal generation device that generates a parameter signal.

[Summary of the Invention] According to the present invention, parameter generation information storage means for storing parameter generation information necessary for parameter signal generation is provided separately from parameter signal generation means for actually generating parameter signals. The parameter generation information is sequentially read out by the information storage unit and preset in the parameter signal generation unit, so that the parameter generation information storage unit is provided separately from the parameter signal generation unit, and a general-purpose memory is used as the parameter generation information storage unit. Thus, the parameter signal generator is made more inexpensive.

[Prior Art] Conventionally, as a parameter signal generating apparatus, there are those shown in FIGS. 15 and 16 taking, as an example, musical tone waveform read address data and envelope waveform generating information.

<Example of Envelope Waveform Generator> FIG. 16 shows an envelope waveform generator. This envelope waveform generator corresponds to the portion of the envelope waveform generator 29 shown in FIG. 4 in the present invention, and the circuit shown in FIG. Correspond to the tone generators 15, 16,... In FIG.

In FIG. 16, the level data LVLi and the speed data SPDi for each phase of the envelope waveform are read from a ROM (not shown) by a control device (not shown), and are all written into the envelope forming data memory 239. This level data LVLi and speed data SPDi
Is the level (target) and rate (target speed) in each phase of the envelope waveform, as shown in FIG.
Is the data indicating the size of.

At the key-on timing (or at a timing preceding this), the start amplitude value at the start point of the envelope waveform is read from the ROM and set in the start amplitude value holding memory 230 by the control device. The start amplitude value LVL0 is selected by the selector 23 at the start of musical sound emission.
It is provided to the adder 234 via 2.

On the other hand, from the envelope formation data memory 239,
The level data LVLi read based on the address data from the read address generator 240 is inverted to the complement value of “2”, that is, a negative value by the complementer 233, and is added to the start amplitude value LVL0 by the adder 234. Is added. As a result, the target level data LVLi is subtracted from the start amplitude value LVLO.

The selector 232 is also provided with envelope data ENV from an amplitude holding circuit 238, which will be described later.After the start of musical sound emission, the selector 232 is provided with the adder 234 to reach the target level data LVLi from the envelope data ENV. Is subtracted. The envelope data ENV indicates the current level of the envelope waveform at each timing.

Next, from the current value of this envelope data ENV,
The multiplier 235 multiplies the subtraction data (envelope data ENV-level data LVLi) from which the target level data LVLi is subtracted by the speed data SPDi from the envelope formation data memory 239. The speed data SPDi is read from the envelope forming data memory 239 based on the address data from the read address generator 240. The multiplied data (envelope data ENV−level data LVLi) × speed data SPDi from the multiplier 235 is added to the target level data LVL by the adder 236.
The value is added to i, stored in the amplitude holding circuit 238, and output to a multiplier (not shown) as envelope data ENV. .

As a result, the envelope data as shown in FIG.
ENV changes at a rate corresponding to speed data SPDi, and the step of change further changes according to subtraction data (envelope data ENV-level data LVLi). This means that the step of changing the envelope data ENV becomes smaller as the level data LVLi of the target is approached.

While a key on a keyboard (not shown) is being pressed,
The high-level key-on signal is input to the key-on event detector 231, which outputs a high-level key-on signal at the up-edge timing of the key-on signal, and outputs a low-level key-on event signal after the start of musical sound emission. This key-on level signal is supplied to the selector 232 to perform selection switching to the start amplitude value LVL0 of the start amplitude value holding memory 230, and also to the read address generator 240 to generate a read address. Container 240
Is reset. The key-on signal is also supplied to the read address generator 240, and the address count of the read address generator 240 is controlled by the key-on signal.

The multiplication data (envelope data ENV−level data LVLi) × speed data SPDi from the multiplier 235 is
The signal is also given to the comparator 237 to judge whether the value has become "0". If the value becomes "0", the coincidence signal is given to the read address generator 240 as a phase end signal, and the read address The read address data of generator 240 is incremented by one. Thus, the level data LVL for the next phase is stored in the envelope formation data memory 239.
i, the speed data SPDi is read out, and the process shifts to generation of the envelope data ENV of the next phase.

<Example of Waveform Read Address Generating Device> FIG. 15 shows a waveform read address generating device, which in the present invention corresponds to the portion of the waveform read address generating device 28 in FIG. The circuit of FIG. 4 corresponds to the tone generators 15, 16,... Of FIG.

In Fig. 15, the loop top data LT
i, loop end data LEi, loop count data LCi
The data is read from a ROM (not shown) by a control device (not shown), and is all written into the waveform read address control data memory 284. This loop top data L
Ti, loop end data LEi, loop count data LCi
As shown in FIG. 8, the head address data, the last address data, and the data of the number of times of repeated reading of the loop section for repeatedly reading the tone waveform data WD are shown.

The read address data ST is stored in the start address holding memory 270 at the key-on timing (or at a timing preceding this) by the above-described control device.
The phase angle step data PD is read from M and is set in the phase angle step data memory 271. The phase angle step data PD is also read from the ROM by the above-described control device at the key-on timing (or at a timing preceding the same). Set.

As shown in FIG. 8, the read start address data ST indicates the read address data RAD at the start point of the reading of the musical tone waveform data WD. The phase angle step data PD is the read address data RA of the tone waveform data WD.
D indicates the increment step value of D, and the phase angle step data PD is sequentially added to generate new read address data RAD. As this value is larger, the reading speed of the musical tone waveform data WD becomes faster, and the pitch Will also be higher. For the above tone waveform data WD, read start address data S
T, loop top data LTi, loop end data LEi,
By changing the loop count data LCi in various ways,
Various tones can be realized.

The read start address data ST from the start address holding memory 270 is supplied to the adder 273 via the selector 272 at the start of musical sound emission, and is added to the phase angle step data PD from the phase angle step data memory 271. You. This addition data is stored in the waveform read address holding circuit 279 via the selector 278 and sent out to the waveform data memory (not shown) as read address data RAD. The phase angle step data PD is sent to the adder 273 via the unit 272, and is added again. In an addition loop circuit of the adder 273 and the waveform read address holding circuit 279, accumulation of the phase angle step data PD with respect to the read address data RAD is performed.

The read address data RAD from the adder 273 is inverted by the complementer 274 to the complement value of “2”, that is, a negative value, and is added to the loop end data LEi from the waveform read address control data memory 284 by the adder 275. Is done. As a result, the read address data RAD is subtracted from the loop end data LEi.

By this subtraction, the reading of the musical tone waveform data WD reaches the end of the loop section for repeated reading, the read address data RAD reaches the loop end data LEi,
When the signal exceeds the loop end data LEi, a carry signal is output from the adder 275. This carry signal is supplied to the difference holding circuit 276 as a latch signal, and fractional data of the read address data RAD exceeding the loop end data LEi is latched.

The fraction data is added to the loop top data LTi by an adder 277, and fraction correction is performed.
Via 78, it is output as new read address data RAD. As a result, the read address data RAD of the tone waveform data WD jumps from the loop end data LEi to the loop top data LTi, and at the time of this jump, the fractional data corresponding to the read address data RAD exceeding the loop end data LEi is corrected. Is also performed. Adder 27 above
The carry signal from 5 is
In addition to being given to the selector 278 to perform selection switching to the adder 277 side, it is also given to the loop counter 281,
Increment is performed.

The loop count value of the loop counter 281 is supplied to a comparator 283, and a judgment is made as to whether or not the loop count data LCi matches. If they match, the match signal is used as a loop end signal as a read address generator. 285, and the read address data of the read address generator 285 is +
1 is done. As a result, the loop top data LTi, loop end data LEi, and loop count data LCi for the next loop are read from the waveform read address control data memory 284, and shifted to the next loop reproduction. The coincidence signal from the comparator 283 is supplied to the loop counter 281 as a clear signal via the NOR gate 282.

While a key on a keyboard (not shown) is being pressed,
The high-level key-on signal is input to the key-on event detector 280, which outputs a high-level key-on signal upon rising edge timing of the key-on signal, and outputs a low-level key-on signal after the start of the musical sound. This key-on event signal is output from the NOR gate 282
Is supplied to the loop counter 281 as a clear signal, and also to the read address generator 285 to reset the read address generator 285.

[Problems to be Solved by the Invention] However, in the above-described configuration, the data stored in the envelope forming data memory 239 and the waveform read address control data memory 284 are the number of phases of the envelope, the section of the loop reproduction of the musical tone waveform data WD. Increase with the number of. Therefore, in order to realize a musical tone close to a natural sound in which the musical tone waveform changes in a complicated manner, the number of data set in the envelope forming data memory 239 and the waveform read address control data memory 284 also increases.

Then, the memory capacities of the envelope forming data memory 239 and the waveform read address control data memory 284 built in the envelope waveform generator and the waveform read address generator become large, and the envelope waveform generator and the waveform read address generator become expensive. There was a problem that would be.

On the other hand, using a general-purpose memory, the level data LVLi, speed data SPDi, loop top data LT
i, loop end data LEi, and loop count data LCi are stored, and these data are read out by the CPU or the like each time and sent to an envelope waveform generator or a waveform read address generator. In this case, the envelope waveform generator and the waveform read address generator are less expensive, and the LS of the tone generators 15, 16,... Including the envelope waveform generator and the waveform read address generator are reduced.
It becomes easy to make I. Further, a memory for storing data is also a general-purpose memory, and is inexpensive.

However, using such general-purpose memory is
The CPU must send the necessary data to the envelope waveform generator and the waveform read address generator each time, which increases the load on the control device such as the CPU and delays the processing. The sound will be difficult. However, in recent years, CP capable of high-speed processing
U has also been manufactured, and even if data necessary for the envelope waveform generator or the waveform read address generator is stored in a location other than the envelope waveform generator or the waveform read address generator, the generation and release of musical tones is smooth. You can do it.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and an object of the present invention is to provide a less expensive parameter signal generation device without delay in musical sound generation and sound emission processing.

[Means for Solving the Problems] In order to achieve the above object, in the present invention, a parameter generation information storage unit for storing parameter generation information necessary for generating a parameter signal includes a parameter signal for actually generating a parameter signal. The parameter generation information is provided separately from the generation means, and the parameter generation information is sequentially read from the parameter generation information storage means and preset in the parameter signal generation means.

[Operation] This allows the parameter generation information storage unit to be provided separately from the parameter signal generation unit, so that a general-purpose memory can be used as the parameter generation information storage unit, and the parameter signal generation device can be manufactured at lower cost. it can.

In this case, even if the parameter generation information storage means is separate from the parameter signal generation means, the tone generation and sound emission processing can be performed.
Higher speeds of control devices such as CPUs are sufficient. The parameter signal includes a signal whose level changes sequentially with time, such as a musical tone waveform, an envelope waveform, a waveform obtained by combining an envelope waveform with a musical tone waveform, read address data of the musical tone waveform, and an envelope waveform in the musical tone waveform. It includes time function information such as read address data of a synthesized waveform whose value changes over time, and the musical sound waveform includes any waveform such as a rectangular wave, a triangular wave, a sine wave, and a natural sound waveform.

[Embodiment] <Overall Circuit> FIG. 3 shows an overall circuit of the parameter signal generating apparatus. In the ROM 13, in addition to a program for the controller 10 to perform various processes, the tone waveform data WD is repeatedly read. Loop top data LTi, loop end data LEi, loop time data LTMi, speed data SPDi for envelope waveform formation, level data LVLi,
Various data necessary for generating a tone signal, such as phase angle step data PD, read start address data ST, and start amplitude value LVL0, which will be described later, are stored. The RAM 14 stores various kinds of intermediate processing data of the control device 10, data for detecting the operation state of the keyboard 11 and the tone / parameter switch unit 12, or data assigned according to the operation state. The RAM 14 may store information relating to musical sounds assigned to each of the tone generators 15, 16 described below.

The operation of each key and each switch of the keyboard 11 and the tone / parameter switch unit 12 is sampled and detected by the control device 10, and the pitch, the key touch, and the tone / parameter designated by each switch are specified by each key. The corresponding tone generation and sound emission processing is executed. The tone generators 15, 16,... Generate the tone signals of the designated pitch, key touch, and timbre / parameter, and are mixed and output from the sound system 17. Tone generator
15, 16,... Are composed of one chip LSI.

The tone generators 15, 16,... Reproduce the tone waveform data WD for each loop and generate the envelope waveform for each phase, and output a write request signal at the end of each loop or at the end of each phase. Is done. This write request signal is given to the control device 10 once,
Are given as write signals to the address controllers 40, 85,..., And the read address data for the ROM 13 includes the next loop top data LTi, loop end data LEi, loop time data LTMi, speed data SPDi, and level data LVLi.
, And these data are read out and sent to the tone generators 15, 16,. A plurality of address controllers 40, 85,... Are provided corresponding to the tone generators 15, 16,. Access to the ROM 13 composed of the address controllers 40, 85,... Is actually performed in a time-division manner through a selector 122 as shown in FIG. 12, and is alternately switched with address data from the control device 10.

FIG. 4 shows one of the tone generators 15, 16,..., And the key information memory 20 stores, among the simultaneously operated keys of the keyboard 11, the tone generators 15, 16,. 16…
The key information of the key to which the channel has been assigned is stored in the memory, and the key information is sent to the waveform read address generator 28 and the envelope waveform generator 29, and a musical tone corresponding to the key information is generated. The key information mainly stores phase angle step data PD, read start address data, start amplitude value LVL0, and the like, which will be described later. This key information memory 20 is completely omitted, and these data are directly
It can be read from the ROM 13 by the control device 10, or R
It may be set once from the OM 13 to the RAM 14 and read out by the control device 10.

These waveform read address generator 28 and envelope waveform generator 29 have loop top data LTi, loop end data LEi, loop time data LTMi, speed data SPDi, and level data LV read from ROM 13 described above.
Li is also given and read address data required for loop playback
The RAD and the envelope data ENV are generated for each phase. Among them, the read address data RAD for loop reproduction generated by the waveform read address generator 28 is
The tone waveform data WD is read to the waveform data memory 25, and the envelope waveform generator
The envelope data ENV from 29 is multiplied by the D / A converter
Via 27, it is output as an analog signal.

<Envelope Waveform Generator 29> FIG. 2 shows a circuit configuration of the envelope waveform generator 29. The level data LVLi and speed data SPDi for each phase of the envelope waveform are controlled by the control device 10 and the address controller 40. The data is read from the ROM 13 and latched by one of the data latches 61 and 62.

The non-latched data latch contains level data for the phase of the envelope currently being generated.
The LVLi and the speed data SPDi are latched, and the data latch for writing and the data latch for reading are alternately switched. Data latch
Of the level data LVLi and the speed data SPDi from 61 or the data latch 62, for the level data LVLi,
Via selector 60, it is provided to complementer 33 and adder 36, and for speed data SPDi, also via selector 60,
This is provided to the multiplier 35.

As shown in FIG. 6, the level data LVLi and the speed data SPDi are data indicating the magnitude of the level (target) and the rate (target speed) in each phase of the envelope waveform.

The start amplitude value LVL0 at the start point of the envelope waveform is read from the key information memory 20 and set in the start amplitude value holding memory 30 at the key-on timing (or at a timing earlier than this). in this case,
The start amplitude value LVL0 may be read directly from the ROM 13 or the RAM 14 by the control device 10 and the address controller 40. The start amplitude value LVL0 is supplied to the adder 34 via the selector 32 at the start of the musical sound emission.

On the other hand, the level data LVLi from the data latch 61 or the data latch 62 is inverted to a complement value of “2”, that is, a negative value by the complementer 33, and is added to the start amplitude value LVL0 by the adder. This gives the start amplitude value
The target level data LVLi is subtracted from LVL0. The complementer 33 can be composed of, for example, an inverter group. A high-level signal is input to a Cin terminal of the next adder 34, and the complement is inverted.

The selector 32 is also provided with envelope data ENV from an amplitude holding circuit 38, which will be described later.After the start of musical sound emission, the selector 32 is provided with the adder 34 to reach the target level data LVLi from the envelope data ENV. Is subtracted.
The envelope data ENV indicates the current level of the envelope waveform at each timing.

Next, from the current value of this envelope data ENV,
The multiplier 35 applies the data latch 61 or data latch to the subtraction data (envelope data ENV-level data LVLi) from which the target level data LVLi has been subtracted.
The speed data SPDi from 62 is multiplied. This multiplication data (envelope data ENV−level data LVLi) ×
The speed data SPDi is added to the attained target level data LVLi by the adder 36 and stored in the amplitude holding circuit 38, and the multiplier 2 outputs the envelope data ENV as the envelope data ENV.
Output to 6.

As a result, the envelope data as shown in FIG.
ENV changes at a rate corresponding to speed data SPDi, and the step of change further changes according to subtraction data (envelope data ENV-level data LVLi). This means that the step of changing the envelope data ENV becomes smaller as the level data LVLi of the target is approached.

Multiplied data (envelope data) from the multiplier 35
ENV-level data LVLi) × speed data SPDi is also given to the comparator 37, and a judgment is made as to whether or not it has become “0”. When the judgment becomes “0”, the coincidence signal is used as a phase end signal. Is output. This phase end signal
The signal is input to the CK terminal of the D-type flip-flop 67, and the D terminal of the flip-flop 67 is always supplied with a high-level signal. When a phase end signal is supplied to the CK terminal, the Q output thereof becomes high-level. Becomes

The high-level Q output is output as a write request signal for the next phase speed data SPDi and level data LVLi to the address controller 40 via the edge detector 66. The edge detector 66 detects an up edge of an input signal, and can be constituted by, for example, a waveform shaping circuit using an operational amplifier.

As described above, the speed data SPDi and the level data LVLi are transmitted to the data latches 61 and 62 by the write request signal.
Is latched by any of The latch signal in this case is
This is a low-level write signal in response to the write request signal from the control device 10, and this signal is supplied to the data latch 61 or the data latch 62 via the OR gate 63 or the OR gate 64.
Given to. This write signal is
67 is also given as a reset clear signal.

The phase end signal from the comparator 37 is input to the flip-flop 69 via the AND gate 69A, and inverts the state of the Q output of the flip-flop 69. The flip-flop 69 is a T-type flip-flop that performs a toggle operation by connecting the inverted Q output of a D-type flip-flop having set (S) and reset (R) inputs to a D input, and receives a reset clear signal. As a result, the Q output becomes low level. The Q output of the flip-flop 69 is supplied to the selector 160 as a selection switching signal, and the selection contents of the selector 60 are changed to the data latch 61 each time one phase ends.
And the data latch 62, and shifts to execution of envelope data ENV generation in the next phase.

The Q output of the flip-flop 69 is directly input to the OR gate 64, inverted by the inverter 65 and input to the OR gate 63, and the latchable data latch is switched between the data latch 61 and the data latch 62. Can be The inverted Q output of the flip-flop 67 is
The opening signal is given to the AND gate 69A, and this opening is maintained until the next speed data SPDi and level data LVLi are written.

A key-on signal that goes high while a key on the keyboard 11 is being pressed is input to the key-on event detector 31 and goes high at the up-edge timing of the key-on signal, and goes low after the start of musical sound emission. A key-on event signal is output. The key-on event detector 31 detects an up edge of an input signal, and can be constituted by, for example, a waveform shaping circuit using an operational amplifier. The key-on event signal is supplied to the selector 32, and at the start of musical sound emission, selection switching to the start amplitude value LVL0 of the start amplitude value holding memory 30 is performed. Further, the key-on event signal is inverted by the inverter 68 to clear the flip-flop 69 so that the data latch 61 is used at the time of key-on.

<Address Controller 40> FIG. 5 is a circuit diagram showing the address controller 40 and a part of the ROM 13 to be read out by the address controller 40. The counter 43 is provided with a key-on event signal from the tone generators 15, 16,. Cleared by As the key-on event signal in this case, the signal actually inverted by the inverter 41 is used.

The counter 43 is incremented by a write signal from the control device 10, and the address designation for the level data LVLi and the speed data SPDi at each address of the ROM 13 is sequentially switched. From the address controller 40, the level data LVLi and the speed data SPD are stored in the ROM13.
The upper address data of the storage area of i is added and output. The higher-order address data is preset by the control device 10 in the latch 43A using the latch 43A. Alternatively, the storage area may be switched and selected according to the timbre, the pitch (tone range), or the like. A specific bit of a plurality of low level bits (earth level) may be inverted by an inverter to be used as upper address data.

The AND gate 42 is closed while maintaining a constant level during key-on in FIG. 6 and CL2 while also maintaining a constant level ("0" level) after key-off. That is, the key-on final detector 44 detects the level data LVL6 and the speed data SPD6 immediately before the certain level period CL1 during key-on, and detects that from the output data content of the counter 43. The signal is inverted by the NOR gate 46 via the AND gate 47 and
42, the AND gate 42 is closed, and the counter 43
To temporarily stop the increment.

Further, the key-off final detector 45 detects the level data LVLm and the speed data SPDm immediately before the fixed level period CL2 after the key-off, from the output data content of the counter 43, and detects it. The signal is inverted by the NOR gate 46 via the AND gate 48 and the AND gate
42, the AND gate 42 is closed, and the counter 43
To stop incrementing. At this time, the key-on signal is at the low level, and the AND gate 48 is opened via the inverter 49.

In this way, the location where the level data LVLi and the speed data SPDi are stored can be stored in the ROM 13 instead of in the tone generators 15 and 16. Since the ROM 13 can use a general-purpose memory, the envelope waveform can be used. The generator 29 can be made cheaper, and the tone generator including the envelope waveform generator 29
It becomes easy to make 15, 16,.

<Waveform Read Address Generator 28> FIG. 1 shows a circuit configuration of the waveform read address generator 28. Loop top data LTi, loop end data LEi, and loop time data for loop reproduction of tone waveform data WD. LTMi is read from the ROM 13 by the control device 10 and the address controller 85, and the data latch 10
7, 108. In the data latch whose data is not latched, the loop top data LTi, the loop end data LEi, and the loop time data LTMi relating to the loop section for repeatedly reading the tone waveform data WD currently being reproduced are latched, and writing is performed. The data latch to be read and the data latch to be read are alternately switched.

Loop top data LTi, loop end data LEi, loop time data of data latch 107 or data latch 108
Among the LTMis, the loop top data LTi is provided to the adder 77 via the selector 103, and the loop end data LEi is also provided to the adder 75 via the selector 103, for the loop time data LTMi. Is also supplied to the loop time determination unit 81 via the selector 103.

Loop top data LTi and loop end data LE
i, loop time data LTMi indicates the start address data, the last address data, and the time data of the repeated reading of the loop section for repeatedly reading out the tone waveform data WD.

In the start address holding memory 70, the read start address data ST is read out from the key information memory 20 and set at the key-on timing (or at a timing preceding this), and the phase angle step data memory 71 stores The phase angle step data PD is also read out from the key information memory 20 and set at the key-on timing (or at a timing earlier thereto). In this case, the read start address data ST and the phase angle step data PD are directly transmitted to the control device 10 and the address controller.
Depending on 40, the data may be read from the ROM 13 or the RAM 14.

As shown in FIG. 8, the read start address data ST indicates the read address data RAD at the start point of the reading of the musical tone waveform data WD. The phase angle step data PD is the read address data RA of the tone waveform data WD.
D represents the increment step value of D, the readout address data RAD is generated by accumulating the phase angle step data PD, and the larger this value is, the faster the reading device of the musical tone waveform data WD is, and the higher the pitch is. Become. Various tone colors can be realized by variously changing the read start address data ST, the loop top data LTi, the loop end data LEi, and the loop time data LTMi with respect to the musical tone waveform data WD.

The read start address data ST of the start address holding memory 70 is added with the phase angle step data PD from the phase angle step data memory 71 by the adder 73 via the selector 72 at the start of the musical sound emission. . This addition data is supplied to the waveform read address holding circuit via the selector 78.
Stored in 79 and sent out to the waveform data memory 25 as read address data RAD, and after the start of musical sound emission, sent out to the adder 73 via the selector 72,
The phase angle step data PD is added again. In an addition loop circuit of the adder 73 and the waveform read address holding circuit 79, the phase angle step data PD for the read address data RAD
Is accumulated.

The read address data RAD from the adder 73 is inverted by the complementer 74 to the complement value of “2”, that is, a negative value, and the adder 75 outputs the loop end data LEi from the data latch 107 or the data latch 108. Is added to As a result, the read address data RAD is subtracted from the loop end data LEi. The complementer 74 can be composed of, for example, an inverter group.
A high-level signal is input to the Cin terminal, and the signal is inverted.

As a result of this subtraction, the reading of the tone waveform data WD reaches the end of the loop section for repeated reading, and the read address data RAD reaches the loop end data LEi, and further exceeds the loop end data LEi. Is output. The carry signal is supplied to the difference holding circuit 76 as a latch signal, and fractional data of the read address data RAD exceeding the loop end data LEi is latched.

This fraction data is added to the loop top data by the adder 77.
LTi, and fraction correction is performed.
Is output as new read address data RAD. As a result, the read address data RAD of the tone waveform data WD jumps from the loop end data LEi to the loop top data LTi, and at the time of this jump,
Correction of fractional data in which the read address data RAD exceeds the loop end data LEi is also performed. The carry signal from the adder 75 is provided as a loop end arrival signal to the selector 78, which performs selection switching to the adder 77, and also to the loop time determination unit 81.

<Loop Time Discriminating Unit 81> FIG. 10 shows a circuit configuration of the loop time discriminating unit 81. The reference time changing unit 140 can be composed of, for example, a decoder or the like, and is provided from the key information memory 20. Or given from the ROM 13 or RAM 14 by the control device 10,
The timbre data, the tone range data, and other various parameter data (dynamic factors or static factors) are decoded and provided to the reference time generator 141. Tone data and parameter data are
The tone range / data is selected and designated by the tone color / parameter switch unit 12, and the gamut data is based on the key code from the keyboard 11, and for example, octave data of the key code is used. The parameter data indicates selection contents such as effects and rhythms, and specification contents of a controller such as a modulation wheel and a pitch bender.

The reference time generator 141 can be composed of, for example, a programmable radix counter, a programmable frequency division counter, or the like, and supplies a pulse signal having a cycle corresponding to the decode data from the reference time changer 140 to the loop counter 142. As a result, the loop time data LTM of the loop section for repeatedly reading out the musical tone waveform data WD can be changed according to the timbre, the tone range, and various parameters.

Loop counter 142 counts the applied pulse signal in time, and provides it to comparator 146. The comparator 146 compares the loop time data LTMi provided from the data latch 107 or the data latch 108 with the time count data from the loop counter 142, and when they match, outputs a match signal as a loop time arrival signal. This loop time reaching signal is input to the S terminal of the SR type flip-flop 145, the flip-flop 145 is set, and the Q output opens the AND gate 144.

Then, the immediately following loop end arrival signal is output as the loop end signal via the opened AND gate 144. This loop end signal is input to the R terminal of the flip-flop 145,
Is reset, and is input to the loop counter 142 via the NOR gate 143 as a clear signal. A key-on event signal is also supplied to the loop counter 142 as a clear signal via the NOR gate 143. This key-on event signal is a signal that goes high at the start of musical sound emission.

In FIG. 1, the loop end signal is input to the CK terminal of a D-type flip-flop 102, and the D terminal of the flip-flop 102 is always supplied with a high-level signal. When an end signal is given, its Q output goes high. The high level Q output is output as a write request signal for the next loop top data LTi, loop end data LEi, and loop time data LTMi to the control device 10 and the address controller 85 via the edge detector 101. Is done. The edge detector 101 detects an up edge of an input signal, and can be constituted by, for example, a waveform shaping circuit using an operational amplifier.

According to the write request signal, the loop top data LTi, the loop end data LEi, and the loop time data LTMi are latched by one of the data latches 107 and 108, as described above. The latch signal in this case is a low-level write signal in response to the write request signal from the control device 10, and this signal is supplied to the data latch 107 or the data latch 108 via the OR gate 109 or the OR gate 110. Can be This write signal is also supplied to the flip-flop 102 as a reset clear signal.

The loop end signal from the loop time determining unit 81 is input to the flip-flop 105 via the AND gate 106, and inverts the state of the Q output of the flip-flop 105. The flip-flop 105 is a T-type flip-flop that performs a toggle operation by connecting the inverted Q output of a D-type flip-flop with a set (S) and reset (R) input to a D input, and receives a reset clear signal. By the Q
The output goes low. The Q output of the flip-flop 105 is supplied to the selector 103 as a selection switching signal, and every time one loop section ends, the selection of the selector 103 is switched between the data latch 107 and the data latch 108, Shift to execution of read address data generation for the next loop section.

The Q output of the flip-flop 105 is input to the OR gate 110 as it is, and the
Are input to the OR gate 109 and latchable by the data latch 107 and the data latch 108.
Can be switched with. The inverted Q output of the flip-flop 102 is supplied to the AND gate 106 as an opening signal, and the opening is maintained until the next loop top data LTi, loop end data LEi, and loop time data LTMi are written.

A key-on signal that goes high while a key of the keyboard 11 is being pressed is input to the key-on event detector 80, and goes high at the up-edge timing of the key-on signal, and goes low when the musical sound starts to be emitted. A key-on event signal is output. The key-on event detector 80 detects an up edge of an input signal, and can be constituted by, for example, a waveform shaping circuit using an operational amplifier. The key-on event signal is given to the selector 72, and at the start of musical sound emission, selection switching to the read start address data ST from the start address holding memory 70 is performed. Further, the key-on event signal is inverted by the inverter 104 to clear the flip-flop 105, and the data latch 1 at the time of key-on.
I try to use 07.

<Address Controller 85> FIG. 7 is a circuit diagram showing the address controller 85 and a part of the ROM 13 from which the address is read by the address controller 85. The counter 86 controls the key-on from the tone generators 15, 16,. Cleared by event signal. As the key-on event signal in this case, the signal actually inverted by the inverter 88 is used.

The counter 86 is incremented by a write signal from the control device 10, and the address designation for the loop top data LTi, the loop end data LEi, and the loop time data LTMi at each address of the ROM 13 is sequentially switched. From the address controller 85, the ROM 13
The upper address data of the storage area of the loop top data LTi, the loop end data LEi, and the loop time data LTMi is added and output. The upper address data is preset by the control device 10 in the latch 86A using the latch 86A. The storage area may be switched and selected according to the timbre, the pitch (tone range), or the like. Of the low-level bits (earth level), a specific bit may be inverted by an inverter to be used as upper address data.

The read address data from the counter 86 is given to the final detector 89.When the read address data reaches the final address of the storage area of the loop top data LTi, the loop end data LEi, and the loop time data LTMi,
The output of the final detector 89 becomes low level, and the AND gate 87 is closed. Thus, after the loop top data LTi, the loop end data LEi, and the loop time data LTMi of the final loop section are read from the ROM 13, the repeated reading of the final loop section of the tone waveform data WD is continued.

In this way, the location where the loop top data LTi, the loop end data LEi, and the loop time data LTMi are stored is not stored in the tone generators 15, 16,.
Since the ROM 13 can use a general-purpose memory, the waveform read address generator 28 can be made cheaper, and the tone generator 15 including the waveform read address generator 28 can be used. 16 can also be easily made into an LSI.

As described above, when the tone waveform data WD of the waveform data memory 25 is repeatedly read by the waveform read address generating device 28, the comparator 146 in FIG. A comparison determination is performed. Accordingly, even if the tone pitch is low and the reading speed of the musical tone waveform data WD is low as shown in FIG. 9 (1), the tone pitch is high and the tone waveform data WD is read out as shown in FIG. 9 (3). Even if the speed is high, the loop playback time of one loop section is always constant. As shown in FIG. 9 (2), the tone pitch is high, the reading speed of the musical tone waveform data WD is increased, and the time for loop reproduction is not shortened.

Thus, whether the pitch is high or low, the loop playback time of each loop section is constant, the loop section is balanced between one tone emission, and the extra tone is generated by the change in pitch. The content change factor does not enter.

<Example of Polyphonic System> FIGS. 11A, 11B, and 12 show an embodiment in which polyphonic musical sounds can be generated by time division processing.

FIG. 11A shows the data latches 61, 62, 107, 1 of the waveform read address generator 28 and the envelope waveform generator 29.
08 corresponds to the musical sound generation system for 8 channels. RAM 112 has 16 storage addresses,
Up to 8 level data LVLi for each set with 8 sets of 2
The speed data SPDi or the loop top data LTi, the loop end data LEi, and the loop time data LTMi are set by the control device 10 and the address controllers 40 and 85. The recording addresses of the two sets are alternately switched between those for which data is currently being read to generate musical tones and those for which data to be executed next is to be written.

The channel signals A0 to A2, which are the designation addresses of the eight storage addresses of the RAM 112, are supplied to the data selectors 113a and 113a.
3b, provided via 113c. This channel signal A0 ~
A2 has a data selector 113a, 113
Selected by b, 113c. Read channel signals A0 to A2
Uses data counted by a system clock signal for synchronizing the entire electronic musical instrument, and is the same as the channel timing signal, as shown in FIG. 11B (1). Write channel signals A0 to A2 are provided from control device 10. The write channel signals A0 to A2 are read channel signals A0 if the write timings have the same cycle as the channel timing of FIG. 11B (1).
A2 may be used as it is.

The two sets of the RAM 112 are switched and selected by an area switching signal, and this signal is supplied to the data selector 113d as it is and after being inverted by the inverter 115. This area switching signal is composed of the read and write channel signals A0 to
This becomes the address data A3 of A2, and the output from the shift register 118 is used. This shift register 1
Numeral 18 denotes a type whose output is fed back through an exclusive OR gate 116 and an AND gate 117. The exclusive OR gate 116 has the comparator 37
, Or a loop end signal from the loop time discriminating section 81, and the area switching signal is inverted at the end of the phase or at the end of the loop. The AND gate 117 is supplied with a low-level key-on event signal from the inverter 68 or the inverter 104, and clears the area switching signal.

The read signal of the RAM 112 is at the high level, and the write signal is at the low level, as shown in FIG. 11B (3).
The write signal is supplied from the control device 10, and the read signal is a signal which is always at a high level, and is supplied to the RAM 112 via the data selector 113e.

It is a read / write timing signal that performs the selection switching of the data selectors 113a to 113e, and this signal is read and written within one channel timing as shown in FIGS. 11B (2) and (4). Switch writing. This signal is directly used for data selection 113a to 113e.
Of the data selectors 113a to 113e is supplied to the AND gate on the write side of the data selector 113a to 113e as an open signal. Note that the write channel timing in FIG. 11B (4) is determined by the write channel signal from the control device 10 irrespective of the channel timing in FIG. 11B (1).

FIG. 12 shows an envelope waveform generator 29A, a waveform read address generator 28A, a controller 10A, address controllers 40A and 85A, etc., which also correspond to a musical tone generation system for a plurality of channels. The write request signal key-on event signal from the envelope waveform generator 29A and the waveform read address generator 28A is sent to the address controllers 40A and 85A at the same timing, and the write request signal is sent to the request signal discriminator 123. Is sent to the control device 10A via the The read channel signal described in FIG. 11A in the envelope waveform generator 29A and the waveform read address generator 28A is also used for the request channel discriminator.
Via 124, it is sent to the control device 10A.

The request signal discriminator 123 and the request channel discriminator 124 can be configured by, for example, an interface, and perform discrimination of signals and data, synchronization of processing timing, and the like. The control device 10A supplies a write signal to the address controllers 40A and 85A for the channel for which the write request signal has been issued, increments the address data for the ROM 13 by 1, and increases the level data LVLi, speed data SPDi, or speed data SPLi of the next phase. Read the loop top data LTi, loop end data LEi, and loop time data LTMi of the next loop from ROM13,
The envelope signal is sent to the RAM 112 of the envelope waveform generator 29A and the waveform read address generator 28A together with the write signal.

The address data for the ROM 13 is switched from the address controllers 40A and 85A and the control device 10A in a time-division manner by the selector 122. As the select signal of the selector 122, a clock pulse signal having a frequency four times the frequency of the channel timing signal is used, and each input is switched and selected. As the write channel signal, the read channel signal from the request channel discriminator 124 is diverted as it is by the control device 10A. Of course, without using the request channel discriminator 124, the read channel signal from the envelope waveform generator 29A and the waveform read address generator 28A is converted into a write channel signal via an AND gate group opened by the write request signal. You may make it output.

At the start of musical sound emission, the control device 10A is connected to the envelope waveform generator 29A and the waveform read address generator 28A.
Key information such as phase angle step data PD, read start address data ST, start amplitude value LVL0,
And read out and sent. Note that the read start address data ST and the start amplitude value LVL0 may be stored in the RAM 14 or a key information memory (not shown).

In order to configure such a tone generation system for a plurality of channels, the following is necessary. That is, the phase angle step data memory 71 may be a feedback input type shift register having the same number of stages as the number of channels, a readable / writable memory (RAM), and the counters 43 and 86 of the address controllers 40A and 85A may correspond to the number of channels. Prepare the same number of minutes, and use a write request signal or a key-on event signal via a demultiplexer or a selector.
Each count data is counted or cleared, and the reference time changer 140 and the reference time generator 14 of the loop time determination unit 81 are used.
1. The same number of loop counters 142 as the number of channels are prepared, and each time count data from the loop counters 142 is supplied to the comparator 146 via a multiplexer or a data selector.

<Repeat Reproduction of Envelope Waveform> FIG. 13A shows another embodiment of the envelope waveform generating device 29. This embodiment employs, as shown in FIG.
Level data LV for each phase of the envelope waveform
Li, speed data SPDi phase and level data LVL
j and the phase of the speed data SPDj are alternately repeated. The repeat count data RPi indicates the number of repeats.

These level data LVLi, LVLj, speed data SP
Di, LVLj, and the number-of-repeats data RPi are read from the ROM 13 by the control device 10 and the address controller 85, and latched in one of the data latches 61 and 62. Level data LV from data latch 61 or data latch 62
Among the Li, LVLj, speed data SPDi, LVLj, and repeat count data RPi, the level data LVLi and LVLj are selected by the selector 60.
And the level data LVL via the selector 170
i, one of the level data LVLj is selected and given to the adder 36. Speed data SPDi and LVLj are
Either the speed data SPDi or the speed data SPDj is selected via the selector 60 and further via the selector 171 and supplied to the multiplier 35. Further, the repeat number data RPi is provided to the comparator 172 via the selector 60.

Then, when the envelope data ENV reaches the final point of the phase and a coincidence signal is output from the comparator 37, this coincidence signal is input to the flip-flop 175 to invert the state of the Q output of the flip-flop 175. . This flip-flop 175 is exactly the same as the flip-flops 69 and 105 described above, and is cleared by a key-on event signal. The Q output of the flip-flop 175 is supplied as a selection switching signal to the selectors 170 and 171. Each time one phase ends, the selection contents of the selectors 170 and 171 are changed to the level data LVLi, the speed data SPDi and the level data LVLj. , Speed data SPDj.

The Q output of the flip-flop 175 is input to a repeat counter 173 to count the number of phase repeats, and the count data is provided to the comparator 172. The comparator 172 includes the repeat number data RPi.
When the two data match, a match signal is input as a clear signal to a repeat counter 173 via a NOR gate 174, and is input to a flip-flop 69 via an AND gate 69A, and the flip-flop The state of the Q output at 69 is inverted. As a result, the content selected by the selector 60 is switched between the data latch 61 and the data latch 62, and the process shifts to execution of envelope data generation for the next repeat section. The repeat counter 173 is also cleared by a key-on event signal. Other details are the same as those of the envelope waveform generator 29 in FIG.

Thus, the parameter data generator that repeats the phase of the envelope waveform also has the level data
The location where the LVLi, LVLj, speed data SPDi, SPDj, and repeat count data RPi are stored is stored in the tone generator 1
Instead of 5, 16,..., The ROM 13 can be stored in the ROM 13. Since the ROM 13 can use a general-purpose memory, the envelope waveform generator 29 can be made less expensive, and the envelope waveform generator 29 can be used. The tone generators 15, 16,...

Note that the repeat count data RPi is replaced with the repeat time data R
It is easy to change the PTi as shown in FIG. 1 and FIG. 10, and it is also possible to change the loop time data RPTi of the loop section according to the timbre, the tone range, and various parameters. .

In this case, in the envelope waveform generating device 29 of FIG. 13A, the portion of the reintroduction frame including the comparator 172 and the repeat count 173 may be replaced with the same one as in FIG. Then, the phase end signal is input to the AND gate 114 instead of the loop end arrival signal, the key-on event signal is used as it is from the key-on event detector 31, and the loop end signal is output as the repeat end signal. , Replace the repeat number data RP with the repeat time data, and the Q output of the flip-flop 175 is
Only the selectors 170 and 171 need to be provided.

As described above, the repeat generation of the envelope waveform can be performed for a fixed period of time.

<Another Example of Loop Reproduction> FIGS. 14A to 14C show the waveform read address generator 28.
This shows another embodiment of the loop reproduction.

FIG. 14A shows the repetition of reciprocal reading of the loop section not in one direction but in both directions. In this case, each time the loop end arrival signal is output from the adder 75, the data provided to the adder 75 and the adder 77 may be exchanged using two selectors. That is, the loop arrival signal is input to the same flip-flop as the flip-flop 105, and the Q output thereof is used as a select signal of the two selectors. The two selectors are provided with loop top data LTi and loop end data LEi
To one, the select signal is supplied as it is, and to the other, the select signal is inverted by an inverter and supplied, and the select data from each selector is added to adders 75 and 77.
Give to. Further, the phase angle step data PD from the phase angle step data memory 71 is provided to an adder 73 via an exclusive OR gate group, and the select signal is provided to each gate of the exclusive OR gate group,
Further, the select signal is input to the Cin terminal of the adder 73.

FIG. 14B is a diagram in which each loop section is repeatedly read only in one direction from the opposite direction. In this case, the loop top data LTi is made smaller than the loop end data LEi, the read start address data ST is made smaller than the loop top data LT1, and the phase angle step data PD from the phase angle step data memory 71 is stored in the inverter group. And a high-level signal is input to the Cin terminal of the adder 73.

FIG. 14C shows the repetition of reciprocating reading of each loop section from opposite directions in both directions. In this case, the configuration is exactly the same as that of FIG. 14A described above, and the loop top data LTi is made smaller than the loop end data LEi, and the read start address data ST is made smaller than the loop top data LT1.

Regarding such a loop reproduction, whether the pitch is high or low, the loop reproduction time of each loop section is constant, the loop section is balanced between one musical sound emission, and the pitch change is performed. As a result, an extra factor for changing the tone content does not enter.

The present invention is not limited to the above embodiment, and can be variously modified without departing from the spirit of the present invention. For example, in the present invention, the level data LVLi, speed data SPDi, repeat count data RPi or loop top data LTi, loop end data LEi, loop time data LTMi (loop count data LCi), and the like have been described as one word data. However, the present invention is not limited to this, and the data may be divided into a plurality of pieces in accordance with the number of bits of the system to form data composed of a plurality of words. Level data LVLi, speed data SPDi,
The locations for storing the repeat count data RPi, loop top data LTi, loop end data LEi, loop time data LTMi, etc. are stored in the RAM 14, the key information memory 20, the assignment memory 121, the memories in the control devices 10, 10A in addition to the ROM 13. The memory may be stored in any location as long as a general-purpose memory, such as a memory externally connected to the parameter signal generator or the like, can be used.

[Effects of the Invention] As described above in detail, according to the present invention, the parameter generation information storage means for storing parameter generation information necessary for parameter signal generation is replaced with a parameter signal generation means for actually generating parameter signals. Since the parameter generation information is sequentially read out by the parameter information generation storage unit and preset in the parameter signal generation unit, the parameter generation information storage unit is provided separately from the parameter signal generation unit. As a result, a general-purpose memory can be used as the parameter generation information storage means, so that the parameter signal generation device can be made more inexpensive.

[Brief description of the drawings]

1 to 14 show an embodiment of the present invention.
The figure is a circuit diagram of the waveform read address generator 28,
The figure is a circuit diagram of the envelope waveform generator 29,
FIG. 11 is an overall circuit diagram of the parameter signal generation device.
The figure is a circuit diagram of the tone generators 15, 16 ...
The figure shows the address controller for the envelope waveform
FIG. 6 is a circuit diagram showing each phase of the envelope waveform, FIG. 7 is a circuit diagram showing the address controller 85 for the musical tone waveform and the ROM 13, and FIG. Waveform data WD and tone waveform data WD
FIG. 9 is a diagram showing a change according to the pitch of the loop reproduction, FIG. 10 is a circuit diagram of the loop time discriminating unit 81, and FIGS. FIG. 13 is a diagram showing an embodiment of a multi-channel tone generation system according to the present invention. FIG. 13 is a circuit diagram of an embodiment for repeatedly reproducing each phase of an envelope waveform.
FIG. 15 is a circuit diagram showing another embodiment of the loop reproduction of the musical tone waveform data WD, and FIGS. 15 to 16 are diagrams showing a conventional example. 10, 10A ... control device, 13 ... ROM, 15, 16 ... tone generator, 28, 28A ... waveform read address generator, 2
9, 29A: Envelope waveform generator, 40, 85: Address controller, 61, 62, 107, 108: Data latch, 81: Loop time discriminator, 112: RAM, 140: Reference time changer , 141 ... Reference time generator.

Claims (4)

(57) [Claims] A parameter signal storage means for storing a tone parameter signal; a parameter signal reading means for reading a tone parameter signal stored in the parameter storage means; and a parameter signal reading means other than the parameter signal storage means and the parameter signal reading means. The parameter signal storage means and the parameter signal reading means are connected to each other via an address bus and a data bus, and parameter repetition information necessary for repetitively reading the tone parameter signal is stored in a tone parameter generated by the repetitive reading. Parameter repetition information storage means for storing all steps over the entire signal; and parameter repetition information reading means for sequentially reading parameter repetition information from the parameter repetition information storage means using the address bus. Presetting means for presetting the parameter repetition information read by the parameter repetition information reading means in the storage section in the parameter signal reading means via the data bus. A parameter signal for reading the tone parameter signal by one step based on the parameter repetition information preset in the storage unit by the preset means before the preset in the storage unit. Repetition control means; read amount measurement means for measuring the amount of one step of reading a tone parameter signal read by the parameter signal read generation means under the control of the parameter signal repetition control means; Measurement Determining whether or not the amount of data for one step in the parameter repetition information read out from the parameter repetition information storage means has been reached; and The parameter signal repetition control means causes the parameter signal reading means to repeatedly read a tone parameter signal based on the parameter repetition information preset in the storage unit by the preset means, and further comprises the parameter repetition information reading Means for reading the parameter repetition information necessary for repeatedly reading the tone parameter signal in the subsequent step.
An output instructing unit for presetting the preset unit in a storage unit in the parameter signal reading unit. 2. Parameter signal generating means for calculating and generating a musical tone parameter signal, and provided at a place other than the parameter signal generating means.
Moreover, the parameter signal generating means is connected to the parameter signal generating means via an address bus and a data bus, and stores parameter generating information necessary for generating the tone parameter signal for all steps over the generated tone parameter signal. Parameter generation information reading means for sequentially reading parameter generation information from the parameter generation information storage means using the address bus; and parameter generation information read by the parameter generation information reading means via the data bus. Preset means for presetting in a storage unit in the parameter signal generation means, wherein the storage unit is smaller than the storage capacity of the parameter generation information storage means, and by this preset means, before the preset to the storage unit, This note Parameter signal generation control means for generating one step of a musical tone parameter signal based on parameter generation information preset in the unit; and one step generated by the parameter signal generation means under the control of the parameter signal generation control means. Generation amount measuring means for measuring the generation amount of the musical tone parameter signal for one minute, and the measurement amount for one step of the generation amount measuring means is one of the parameter generation information read out from the parameter generation information storage means. Determining means for determining whether or not the generation amount data for the step has been reached; and, in accordance with the determination result of the determining means, the parameter signal generation control means is preset in the storage unit by the presetting means. A tone parameter signal is generated by the parameter signal generating means based on the parameter generation information. And causing the parameter generation information reading means to read parameter generation information necessary for generating a tone parameter signal in a subsequent step. An output instructing unit for presetting the preset unit in a storage unit in the parameter signal generating unit; 3. The parameter signal storage means stores tone waveform signals, and the parameter repetition information storage means stores information on a range of repetitive reading and a time of repetitive reading of a part of the tone waveform signals. Means for storing, wherein the storage unit comprises at least two storage units, one of which is preset with parameter repetition information, and the other is with which parameter repetition information is read, and the preset and the read are alternately switched. The parameter signal generating device according to claim 1, wherein: 4. The parameter signal generation means for calculating and generating an envelope waveform signal, and the parameter generation information storage means stores information on a calculation level, a calculation speed, and the number of repetitions of each phase of the envelope waveform signal. Means for storing, wherein the storage unit includes at least two storage units, one of which is preset with parameter generation information, and the other is with which parameter generation information is read, and the preset and the read are alternately switched. 3. The parameter signal generator according to claim 2, wherein: