JP2544511B2 - High efficiency digital multiplexer transmission system. - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] A transmission system of a high-efficiency digital multiplexer that inserts and transmits packet data from a packet switch when there is no voice signal to be transmitted to a high-speed digital line and there is no voice signal. For the purpose of a high-efficiency digital multiplexer capable of requesting the transmission and reception of only data below the maximum processing speed, the packet switch can respond to the request. A clock output permission unit that permits output of only clocks at speeds less than or equal to is provided, and when there is no audio signal to be transmitted, the clock output permission unit permits the clock by
It is configured to insert and transmit packet data obtained by processing the data of the packet switch.

[Industrial applications]

The present invention relates to a digital multiplex transmission system of data and a voice signal, and more particularly to a transmission system of a high efficiency digital apparatus for inserting and transmitting packet data from a packet switch instead when there is no voice signal.

In recent years, the construction of corporate networks has become popular, and the scale of networks is expanding from domestic to overseas. Along with this, it is required to improve the transmission efficiency of international network lines. For this reason, a so-called high-efficiency digital multiplexer that inserts packetized data and transmits the voice signal when there is no voice signal is provided when the voice signal is transmitted. At this time, a packet switch with various maximum processing speeds is provided. Used by being connected to.

[Conventional technology]

The high-speed digital line used as an international network has a data transmission rate of 48 Kbps, 56 Kbps, 64x n K
A speed of bps (n is a positive integer) is used. On the other hand, the maximum data processing speed of the packet switch connected to the high efficiency digital multiplexer is 9600bps, 14.4Kbp.
s, 19.2Kbps, 64Kbps, etc.
It is often slower than the transmission speed of the high speed digital lines used. Therefore, a highly efficient digital device
When the voice is silent, even if the packet switch is requested to transmit or receive data at a speed equal to or higher than the maximum processing speed of the packet switch, there is a problem that the packet switch cannot respond to the request.

[Problems to be Solved by the Invention]

An object of the present invention is not to request a packet switch connected to a digital transmission line to transmit or receive data at a speed equal to or higher than its maximum processing speed, that is, to send only data at a speed equal to or lower than the maximum processing speed of the packet switch. The purpose of this is to provide a transmission system for a high-efficiency digital multiplexer that requests a reception and the packet switch can respond to the request.

[Means for solving the problem]

This problem is, as shown in the principle diagram of FIG. 1, the multiplexing unit 200 of the multiplexer 100 for inserting and transmitting the packet data from the packet switch 70 when there is no voice signal to be transmitted to the high speed digital line 80 when there is no sound. Is provided with a clock output permitting unit 2000 which permits output of only a clock having a speed equal to or lower than the maximum processing speed of the packet switch 70, and the clock of the packet switch 70 is controlled by the clock permitted by the clock output permitting unit when there is no voice signal to be transmitted. This is solved by the present invention in which packet data obtained by processing data is inserted and transmitted.

[Action]

The clock output permission unit 2000 newly provided in the multiplexing unit 200 of the multiplexing device 100 does not output the clocks higher than the maximum processing speed to the packet switch 70, and outputs only the clocks lower than the maximum processing speed. To give permission. Therefore, the multiplexing unit 200 of the multiplexer 100 of the transmission system of the high-efficiency digital multiplexer of the present invention, the packet switch 7 when the voice is silent.
For 0, it requests the transmission and reception of only the data below the maximum processing speed of the packet switch, so the packet switch can respond to the request and can insert and transmit the packet data instead when it is silent. To be done.

〔Example〕

FIG. 2 shows the configuration of the high-efficiency digital multiplex transmission system according to the first embodiment of the present invention, and FIG. 3 is a time chart explaining its operation. FIG. 4 shows the configuration of the second embodiment of the present invention, and FIG. 5 is a time chart for explaining the operation.

In the high-efficiency multiplexer 100 of the first embodiment of the present invention shown in FIG. 2A, the data from the data terminal 60 passes through the data interface 104, and the voice signal from the PBX 90 receives the voice interfaces 101 # 1 to 101 # 1. The high-efficiency multiplexer 200 is passed through the data bus 102 in the apparatus via 101 # n. The high-efficiency multiplexer 200 transmits the packet data from the packet switch 70 to the high-speed digital line 80 via the data bus 102 and the line interface 103 when there is no voice signal and there is no sound. And the high-efficiency multiplexer 200 of the high-efficiency multiplexer 100
The clock output permission unit 2000 provided inside is shown in FIG.
As described above, the output enable signal generator 210, the AND circuit 223 for the output of the transmission clock generation circuit 221, and the AND circuit 233 for the output of the reception clock generation circuit 231 are configured.

The transmission operation will be described. A transmission signal from the in-device data bus 102 is received by the interface 201, becomes various transmission data 205, and is transmitted to the MUX 203. High efficiency multiplexer 20
As shown in the time chart of FIG. 3, 0 is, for example, 1, 2 and 4 to P and P + 3, P + 4 channels among 1 to T channels of the transmission data 205 with no sound in a certain multiplexing processing period T. When there is no data, the MUX 203 sends out a signal 220 indicating that state to the packet data transmission clock generation circuit 221 and the corresponding transmission clock 2
Raises 22. If the transmission speed of the high-speed digital line 80 is 64 Kbps, the maximum data processing speed of the packet switch 70 is 19.2 Kbps, and the multiplexing processing cycle T of the high efficiency multiplexer 200 is 10 msec (0.1 KHz), The maximum number t of transmission clocks 222 in the processing cycle T is 64 / 0.1 = 640, and the maximum number of clocks p in the range N of transmission / reception clocks capable of processing the maximum data of the packet switch in the processing cycle T is 19.2 / 0.1 = 192. Becomes Now, even if the transmission clock 222 in the multiplexing period T of the transmission data 205 in the time chart of FIG. 3 is used as it is as the packet transmission clock 224 of the packet switch 70, the packet switch generates the output permission signals 211 and 212 shown in FIG. The output of the device 210 cannot follow the transmission clock 222 in the section Q. Then, the AND circuit 223 of FIG. 2B takes the logical product of the transmission clock 222 and the output permission signal 211, supplies the output as the packet transmission clock 224 to the packet switch 70, and processes it by the flip-flop FF71. Packet transmission data 255
To the MUX 203 of the high efficiency multiplexing unit 200. And MUX
203 multiplexes various transmission data 205 and packet transmission data 225 from the packet switch 70,
2, to the high-speed digital line 80 via the data bus 102 and the interface 103.

Next, the reception operation will be described. A signal from the high-speed digital line 80 via the interface 103 and the in-device data bus 102 is received by the interface 202 of the multiplexing unit 200,
It becomes various received data 208 and is sent to the DMUX 204. As shown in the time chart of FIG. 3, the high-efficiency multiplexer 200 has, for example, 1,2 and 4 to P and P + 3, P + of the channels 1 to T of the received data 208 in a certain multiplexing processing cycle T.
If the 4 channels have no audio or no data, DMU
The X204 sends a signal 230 indicating the state to the packet data reception clock generation circuit 231 to generate a corresponding reception clock 232.

Similar to the transmission operation, the reception clock 232 in the multiplexing cycle T of the reception data 208 shown in the time chart of FIG.
The packet reception clock 23 of the packet switch 70
Even if the packet switching device 4 is used, the packet switch 2 receives the reception clock 2 in the section Q of the output of the output permission signal generator 210 indicated by 211 and 212 in FIG.
34 cannot follow. Therefore, the AND circuit 233 of FIG.
At the logical product of the reception clock 232 and the output permission signal 212, the output is supplied to the packet switch 70 as the packet reception clock 234, and its flip-flop FF72.
The reception data 235 from the DMUX 204 is processed to obtain packet reception data.

The second embodiment of the present invention shown in FIG.
The clock supply permission unit 2000 provided in 0 outputs the output permission signal 211, or 212 to the output 220 of the MUX 203 when transmitting packet data and to the output 230 of the DMUX 203 when receiving packet data. ANDed with and output 320
Or, it is the same as the first embodiment of FIG. 2 except that the transmitting clock generating circuit 221 or the receiving clock generating circuit 231 is driven by 330. Also in the operation of the second embodiment, as shown in the time chart of FIG. 5, various transmission data 205 or various reception data 208 in a certain multiplexing cycle T of the high efficiency multiplexing unit 200.
1 to T channels of 1, 2 and 4 to P and P +
When there is no voice or data on channels 3 and P + 4, MUX203 or DMUX204 sends a signal 220 indicating those states.
Alternatively, 230 is sent to the AND circuit 223 or the AND circuit 233. The AND circuit 223 ANDs the signal 220 indicating silence and no data with the output signal 211 of the output permission signal generator 210, and the AND circuit 233 outputs the signal 230 indicating silence and no data and the output permission signal generator 210. Of the output signal 212 of the packet switch 70 and the output thereof to drive the transmission clock generator 221 or the reception clock generator 231 for transmission within the range N of the maximum switchable clock speed of the packet switch 70. clock
224 or a reception clock 234 is generated. Then, by the generated transmission clock 224 or reception clock 234, the transmission data of the packet switch 70 is processed and transmitted to the high-speed digital line 80, or the packet data is received from the high-speed digital line 80 to the packet switch 70.

Therefore, both the high efficiency digital multiplexer of the first embodiment shown in FIG. 2 and the second embodiment shown in FIG.
Since the packet switch 70 is requested to send and receive only the data that is less than or equal to the maximum processing speed of the packet switch, the packet switch can respond to the request and insert the packet data when there is no sound to the high-speed digital line 80. Since it can be transmitted or the packet data can be separated from the high-speed digital line 80, there is no problem.

〔The invention's effect〕

As described above, according to the present invention, a high-efficiency digital multiplexer that inserts / separates packet data when there is no sound is used for a packet switch connected to the device. If it is applied to an international line, it is convenient to use and the transmission efficiency of the international line is improved.

[Brief description of drawings]

FIG. 1 is a principle diagram showing a basic configuration of a transmission system of a high efficiency digital multiplexer of the present invention, FIG. 2 is a block diagram showing a configuration of a first embodiment of the present invention, and FIG. 1 is a time chart for explaining the operation of the first embodiment, FIG. 4 is a block diagram showing the configuration of the second embodiment of the present invention, and FIG. 5 is an operation of the second embodiment of the present invention. It is a time chart for. In the figure, 60 is a data terminal, 70 is a packet switch, and 80
Is a high-speed digital line, 90 is a PBX, 100 is a high-efficiency digital multiplexer, 200 is a multiplexer, 203 is a MUX, 204 is a DMUX, 20
00 is a clock output permission unit.

Claims (1)

(57) [Claims] 1. A multiplexer (200) of a high efficiency digital multiplexer (100) for inserting and transmitting packet data from a packet switch (70) when there is no voice signal to be transmitted to a high-speed digital line (80) and there is no sound. ) Is provided with a clock output permission unit (2000) for permitting output of only a clock having a speed equal to or lower than the maximum processing speed of the packet switch, and the data of the packet switch is processed by the clock permitted by the clock output enable unit when there is no sound. A high-efficiency digital multiplexer transmission system characterized by inserting the packet data into a high-speed digital line for transmission.