JP2021056516A - Display device - Google Patents

Abstract

To examine internal stress of a semiconductor device including a conductive film, which is affected by the internal stress of the conductive film.SOLUTION: A semiconductor device including an n-channel type TFT provided on an insulating surface is configured so that impurity elements are introduced to a conductive film, for instance, a gate electrode so that a semiconductor film is subjected to pulling stress. The semiconductor device including a p-channel type TFT provided on the insulating surface is configured so that the impurity elements are introduced to the conductive film, for instance, the gate electrode so that the semiconductor film is subjected to compression stress.SELECTED DRAWING: Figure 6

Description

The present invention relates to a semiconductor device having a circuit composed of a thin film transistor (hereinafter referred to as a TFT) and a method for manufacturing the same. In particular, the present invention relates to an electro-optical device typified by a liquid crystal display device, a semiconductor device equipped with such an electro-optic device as a component, and a method for manufacturing the same. In the present specification, the semiconductor device refers to all devices that can function by utilizing the semiconductor characteristics, and the electro-optical device, the semiconductor circuit, and the electronic device are all semiconductor devices.

In recent years, T has been used by using a thin film (thickness of several to several hundred nm) formed on a substrate having an insulating surface.
Development of a semiconductor device that constitutes an FT and has a large-area integrated circuit formed by this TFT is in progress. As a typical example, an active matrix type liquid crystal display device and a light emitting device are known. In particular, since a TFT having a crystalline silicon film as an active region has high field effect mobility, it is possible to form various functional circuits.

For example, in an active matrix type liquid crystal display device, in order to control a pixel circuit that displays an image for each functional block, a shift register circuit based on a CMOS circuit, a level shifter circuit, a buffer circuit, a sampling circuit, and the like. The drive circuit of is formed on one substrate.

Further, the TFT has at least a semiconductor film, an insulating film made of a silicon oxide film, a silicon nitride film, or the like, and a wiring made of various metal materials or the like. The wiring includes source wiring, gate wiring (including a gate electrode), and the like. Since the thickness of these films is about several to several hundred nm, it can be said to be a thin film.

These thin films are formed by a known film forming technique such as a CVD method (chemical vapor deposition method) or a sputtering method. However, it is known that the thin film has internal stress. The internal stress includes an intrinsic stress and a thermal stress caused by a difference in the coefficient of thermal expansion between the thin film and the substrate.

The effect of thermal stress can be ignored by considering the material of the substrate, process temperature, pressure, etc., but the mechanism of intrinsic stress generation is not always clarified, but rather the film growth process and It is considered that the phase change and composition change due to the subsequent heat treatment are intricately intertwined and occur.

Generally, internal stress includes compressive stress and tensile stress. As shown in FIG. 5 (A)
When the thin film 311 is about to stretch, the substrate 312 is compressed to form the thin film 311 on the outside, which is called compressive stress. On the other hand, as shown in FIG. 5B, when the thin film 311 tries to shrink with respect to the substrate 312, the substrate 312 deforms with the thin film inside in order to pull in a direction that hinders it, and this is called tensile stress. I'm out. In general, the tensile stress value is often indicated by +, and the compressive stress value is often indicated by-.

Regarding the effect of such internal stress on the electrical characteristics of the transistor, for example, "0"
.. Effect of stress of etch stop nitride film on 13 μm CMOS transistor performance; Japan Society of Applied Physics Subcommittee Silicon Technology No. 25 ULSI device related special issue (200)
1) pp36-39 ”. According to this, it has been reported that the mobility of an NMOS transistor improves when the channel formation region receives tensile stress, and that of a NMOS transistor improves when it receives compressive stress.

As described above, the wiring of the TFT is also formed of a thin film. Therefore, the wiring also has an internal stress, and if the internal stress is strong, peeling may occur.
Further, the gate electrode formed of the same material as the wiring is formed on the semiconductor film via the insulating film. The internal stress of the gate electrode acts on the semiconductor film and distorts the interface between the insulating film and the semiconductor film and the semiconductor film, thereby causing electricity represented by a threshold voltage and field effect mobility. It may adversely affect the physical characteristics.

The present invention is a technique for solving such a problem, and improves the operating characteristics and reliability of a semiconductor device in an electro-optical device and a semiconductor device represented by an active matrix type liquid crystal display device having wiring. , The purpose is to improve the yield.

The present invention makes it possible to control the wiring to a desired internal stress by introducing an impurity element into the wiring of the TFT, or by performing both the introduction of the impurity element and the heat treatment. In particular, the present invention
It is extremely effective to apply it to the gate electrode. Further, it is also possible to introduce an impurity element only in a desired region or perform heat treatment to control the desired internal stress.

For example, by applying the present invention, the stress received by the channel forming region in the n-channel TFT can be set as the tensile stress, and the stress received by the channel forming region in the p-channel TFT can be set as the compressive stress. Further, the channel formation region in the n-channel TFT has a relatively stronger tensile stress than the channel formation region in the p-channel TFT, and the channel formation region in the p-channel TFT is n-channel type. TFT
It is also possible to make the compressive stress relatively stronger than the channel formation region in. By doing so, it is possible to improve the electrical characteristics of the TFT and to significantly improve the operating characteristics of the semiconductor device.

The method for introducing the impurity element may be a plasma doping method, an ion implantation method, an ion shower doping method, or the like. In such a method of introducing an impurity element, the energy of the ion driven into the thin film is very large as compared with the binding energy of the element forming the thin film. Therefore, the ions that are driven into the thin film flick the atoms forming the semiconductor film from the lattice points and exist at the lattice position, and the ions that are driven and the atoms that are flicked from the lattice points are located at the interstitial positions. Will exist in. Since the thin film is stretched in this way, the compressive stress is increased when the thin film has compressive stress, and the tensile stress is relaxed when the thin film has tensile stress.

Further, the heat treatment returns the atoms existing at the interstitial positions to the lattice positions, so that the regularity of the arrangement of the atoms is improved. Therefore, since the thin film shrinks, the tensile stress increases when the thin film has a tensile stress, and the compressive stress is relaxed when the thin film has a compressive stress.

Further, when the impurity element is introduced after the heat treatment, the accelerated ions are driven into the film having improved regularity of the atomic arrangement, so that the ions do not collide along the gaps of the crystal lattice. It is possible to enter deep. (Channeling) Therefore,
In the introduction of impurity elements to control internal stress, the amount of dose is small, and
It is possible to perform with a low acceleration voltage.

In addition, when the heat treatment is performed after introducing the impurity element, more atoms are introduced into the thin film than the atoms forming the thin film, so that the atoms existing in the interstitial position return to the lattice position. Atoms will exist. Therefore, since the shrinkage of the thin film is smaller than that in the case where the impurity element is not introduced, the amount of increase in tensile stress is also small. That is, when it is known that the heat treatment is performed in the subsequent process, it is possible to reduce the amount of change in the internal stress by introducing an impurity element in advance.

In this way, it is possible to control the desired internal stress by performing both the introduction of the impurity element, the introduction of the impurity element, and the heat treatment. Of course, the introduction of impurities and the heat treatment are not limited to one time, and may be performed a plurality of times. The present invention applies these characteristics to wiring and controls the stress of the wiring to improve the operating characteristics and reliability of the semiconductor device. In particular, by controlling the internal stress at the gate electrode of the TFT, it is possible to control the stress received by the semiconductor film. Therefore, it is possible to improve the electrical characteristics typified by the threshold voltage and the field effect mobility. Further, since it is possible to control the stress of each gate electrode, it is possible to suppress variations in electrical characteristics.

The production method of the present invention disclosed in the present specification is characterized in that an impurity element is introduced into the conductive film so that the internal stress in the conductive film is ± 1 GPa or less.

Further, another production method of the present invention is characterized in that an impurity element is introduced into the conductive film and the conductive film is heat-treated so that the internal stress in the conductive film is ± 1 GPa or less.

Further, another production method of the present invention is characterized in that the conductive film is heat-treated to introduce an impurity element into the conductive film so that the internal stress in the conductive film is ± 1 GPa or less.

In each of the above-mentioned production methods, the method of introducing the impurity element can be carried out by a plasma doping method, an ion implantation method, an ion shower doping method or the like.

Further, in each of the above-mentioned production methods, the impurity element is not particularly limited, but is one or more kinds of elements selected from the impurity element that imparts n-type, the impurity element that imparts p-type, and the rare gas element. Is desirable. Impurity elements that impart n-type and impurity elements that impart p-type are impurity elements that are indispensable for forming the source region and drain region. Therefore, it is economical because it is not necessary to newly prepare other impurity elements. In particular, when an impurity element is introduced into the gate electrode, it can be introduced at the same time as the step of introducing the impurity element into the source region and the drain region, and thus it can be introduced without increasing the number of steps, which is preferable. Further, since the rare gas element is an inert element, it does not affect the electrical characteristics of the TFT, which is preferable.

Further, as the amount of the impurity element introduced increases, the compressive stress increases when the internal stress in the thin film is compressive stress, and when the internal stress in the thin film is tensile stress, the tensile stress is relaxed and then relaxed. It may also have compressive stress. That is, depending on the amount of impurity elements introduced, the internal stress in the thin film may be a compressive stress or a tensile stress.

Further, in each of the above-mentioned manufacturing methods, it is desirable that the value of the internal stress in the conductive film is ± 1 GPa or less. It is known that peeling occurs when the internal stress of the conductive film is strong, and generally, the guideline for suppressing the occurrence of peeling is ± 1 GPa or less. Of course, the occurrence of peeling greatly affects the conditions under which the conductive film is formed.

Further, in each of the above-mentioned production methods, the conductive film is not limited to a single layer, and may have a laminated structure of two or more layers.

Further, in each of the above-mentioned production methods, the heat treatment can be applied to an RTA method, a laser annealing method, a thermal annealing method using a furnace anneal furnace, or the like.

In addition, the heat treatment greatly affects the change in internal stress in the thin film depending on the time and temperature. The longer the heat treatment time and the higher the heat treatment temperature, the greater the tensile stress when the internal stress in the thin film is tensile stress, and when the internal stress in the thin film is compressive stress, the compressive stress increases. After relaxation, it may have tensile stress. That is, depending on the conditions of the heat treatment, the internal stress in the thin film may be a compressive stress or a tensile stress.

Moreover, the structure of this invention is shown below.

A semiconductor device having an n-channel TFT, wherein the n-channel TFT has a semiconductor film and a conductive film, the semiconductor film is subjected to tensile stress, and an impurity element is introduced into the conductive film. It is characterized by.

A semiconductor device having a p-channel TFT, wherein the p-channel TFT has a semiconductor film and a conductive film, the semiconductor film is subjected to compressive stress, and an impurity element is introduced into the conductive film. It is characterized by.

A semiconductor device having an n-channel TFT and a p-channel TFT, wherein the n-channel TFT has a first semiconductor film and a first conductive film formed on the first semiconductor film. The p-channel TFT has a second semiconductor film and a second conductive film formed on the second semiconductor film, and the first semiconductor film receives tensile stress. The second
The semiconductor film of No. 1 is subjected to compressive stress, and the first conductive film and the second conductive film are characterized in that an impurity element is introduced.

In each of the above configurations, the impurity element is not particularly limited, but it is desirable that the impurity element is one or more selected from an impurity element that imparts n-type, an impurity element that imparts p-type, and a rare gas element. .. Impurity elements that impart n-type and impurity elements that impart p-type are impurity elements that are indispensable for forming the source region and drain region. Therefore, it is economical because it is not necessary to newly prepare other impurity elements. In particular, when an impurity element is introduced into the gate electrode, it can be introduced at the same time as the step of introducing the impurity element into the source region and the drain region, and thus it can be introduced without increasing the number of steps, which is preferable. Further, since the rare gas element is an inert element, it does not affect the electrical characteristics of the TFT, which is preferable.

Further, it is characterized in that a semiconductor device typified by a liquid crystal display device or a light emitting device is formed by using a TFT having each of the above configurations.

By adopting the configuration of the present invention, the following basic significance can be obtained.
(A) A simple method suitable for the conventional manufacturing process.
(B) The formation of wiring having a desired internal stress can be realized. Therefore, the stress in other films can also be reduced. In addition, the wiring patterning process can be performed well.
(C) In a semiconductor device represented by an active matrix type liquid crystal display device, the operating characteristics and reliability of the semiconductor device can be improved, and the yield can be improved, while satisfying the above advantages.

The figure which shows an example of the concept of this invention. The figure which shows an example of the concept of this invention. The figure which shows the example of the amount of change in the direction of compressive stress by the introduction of an impurity element. The figure which shows the example of the amount of change in the direction of tensile stress by heat treatment. The figure explaining tensile stress and compressive stress. The figure which shows an example of the concept of this invention. The figure which shows an example of the concept of this invention. The cross-sectional view which shows the manufacturing process of the pixel TFT and the TFT of the drive circuit. The cross-sectional view which shows the manufacturing process of the pixel TFT and the TFT of the drive circuit. The cross-sectional view which shows the manufacturing process of the pixel TFT and the TFT of the drive circuit. The cross-sectional view which shows the manufacturing process of the pixel TFT and the TFT of the drive circuit. The cross-sectional view which shows the manufacturing process of the pixel TFT and the TFT of the drive circuit. Top view showing the structure of a pixel TFT. The cross-sectional view which shows the manufacturing process of the pixel TFT and the TFT of the drive circuit. The cross-sectional view which shows the manufacturing process of the active matrix type liquid crystal display device. FIG. 3 is a cross-sectional view of a drive circuit and a pixel portion of a light emitting device. (A) Top view of the light emitting device. (B) Cross-sectional structure diagram of a drive circuit and a pixel portion of a light emitting device. The figure which shows the example of the semiconductor device. The figure which shows the example of the semiconductor device. The figure which shows the example of the semiconductor device. The cross-sectional view which shows the manufacturing process of MOSFET. The cross-sectional view which shows the manufacturing process of MOSFET. The cross-sectional view which shows the manufacturing process of MOSFET.

[Embodiment 1]
An embodiment of the present invention will be described with reference to FIG. In the present embodiment, the present invention is referred to as a TFT.
The case where it is applied to the gate electrode of the above will be described.

First, the underlying insulating film 11 is formed on the substrate 10. As the substrate 10, a glass substrate, a quartz substrate, a single crystal silicon substrate, a metal substrate, or a stainless steel substrate on which an insulating film is formed may be used. Further, a plastic substrate having heat resistance that can withstand the processing temperature may be used.

Further, as the base insulating film 11, a base insulating film 11 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxide film is formed. Here, an example in which a single-layer structure is used as the base film 11 is shown, but a structure in which two or more layers of the insulating film are laminated may be used. The underlying insulating film 1
It is not necessary to form 1.

Next, the semiconductor film 12 is formed on the underlying insulating film 11. The semiconductor film 12 is a means known for forming a semiconductor film having an amorphous structure (sputtering method, LPCVD method, plasma CVD method, etc.).
After the film is formed by the above method, a known crystallization treatment (laser crystallization method, thermal crystallization method, thermal crystallization method using a catalyst such as nickel, etc.) is performed to form a crystalline semiconductor film. This semiconductor film 12
Is formed to have a thickness of 25 to 200 nm (preferably 30 to 100 nm). The material of the semiconductor film is not limited, but it is preferably formed of silicon, silicon germanium (SiGe) alloy, or the like.

Next, the insulating film 13 is formed on the semiconductor film 12. The insulating film 13 is formed by a single layer or laminated structure of an insulating film containing silicon with a thickness of 40 to 150 nm by using a plasma CVD method, a sputtering method, or the like. The insulating film 13 is a gate insulating film.

Next, a sputtering method, a plasma CVD method, or the like is used on the insulating film 13, and the film thickness is 250 to 600.
A conductive film 14 having a nm is formed. Here, an example in which a single-layer structure is used as the conductive film 14 is shown, but a structure in which two or more layers of the conductive film are laminated may be used.

However, when formed by the CVD method, the conductive film 14 may have a strong tensile stress 15. Therefore, an impurity element is introduced to relax the internal stress in the conductive film 14 to obtain a desired internal stress. Impurity elements may be introduced by a plasma doping method, an ion implantation method, an ion shower doping method, or the like. Further, as the impurity element to be introduced, one or more kinds of elements selected from the impurity element that imparts n-type, the impurity element that imparts p-type, and the rare gas element are used, and the acceleration voltage is 30 to 120 keV and the dose amount is adjusted. The ratio is 1 × 10 ^{12 to} 9 × 10 ¹⁶ / cm ² , and the peak density is 1 × 10 ¹⁷ to 1 × 10 ²² / cm ³ .
(FIG. 1 (C)) Of course, the optimum introduction conditions for the impurity element also differ depending on the state of the conductive film and the desired internal stress. Further, if an impurity element is introduced only in a desired region by using a mask made of a resist, it is possible to change the internal stress of only the desired region.

The internal stress of the conductive film thus formed becomes a desired internal stress, and the stress exerted on the semiconductor film can be reduced. When a TFT is manufactured using such a conductive film, its electrical characteristics are improved and the operating characteristics of the semiconductor device can be significantly improved.

[Embodiment 2]
An embodiment of the present invention will be described with reference to FIG. In this embodiment, a case where the internal stress is controlled by performing heat treatment after introducing the impurity element will be described.

First, according to the first embodiment, the introduction of impurity elements is performed.

Subsequently, heat treatment is performed to increase the internal stress in the conductive film 14 if it is a tensile stress and relax it if it is a compressive stress. The heat treatment may be performed by a known method such as a thermal annealing method using a furnace anneal furnace, a laser annealing method, or an RTA method. For example, when the thermal annealing method using a furnace annealing furnace is performed, it may be exposed to a nitrogen atmosphere having a temperature of about 500 to 1000 ° C. for about 3 minutes to 12 hours. Of course, the optimum heat treatment conditions also differ depending on the state of the conductive film and the desired internal stress. Further, if the heat treatment for a long time is performed at the same time as the crystallization of the semiconductor film and the activation of the impurity element in the manufacturing process of the TFT, the heat treatment can be performed without increasing the number of steps, which is efficient.

Further, it is also possible to change the internal stress of only the desired region by performing the heat treatment only in the desired region by a laser annealing method or the like.

The internal stress of the conductive film thus formed becomes a desired internal stress, and the stress exerted on the semiconductor film can be reduced. When a TFT is manufactured using such a conductive film, its electrical characteristics are improved and the operating characteristics of the semiconductor device can be significantly improved.

[Embodiment 3]
An embodiment of the present invention will be described with reference to FIG. In this embodiment, a case where the internal stress is controlled by performing heat treatment after introducing the impurity element will be described.

First, the insulating film 13 is formed according to the first embodiment.

Next, a sputtering method, a plasma CVD method, or the like is used on the insulating film 13, and the film thickness is 250 to 600.
A conductive film 17 having a nm is formed. Here, an example in which a single-layer structure is used as the conductive film 17 is shown, but a structure in which two or more layers of the conductive film are laminated may be used.

However, the conductive film 17 formed by the sputtering method may have a strong compressive stress 15. Therefore, heat treatment is performed to change the internal stress in the conductive film 17. The heat treatment includes a thermal annealing method using a furnace anneal furnace, an RTA method, a laser annealing method, etc.
A known method may be used. (Fig. 2 (B))

Subsequent heat treatment increases the internal stress in the conductive film 14 if it is a tensile stress, and relaxes it if it is a compressive stress. (FIG. 2 (C)) The heat treatment may be performed by a known method such as a thermal annealing method using a furnace annealing furnace, a laser annealing method, or an RTA method. For example, if the thermal annealing method using a furnace anneal furnace is performed, the temperature is 500 to 10
It may be exposed to a nitrogen atmosphere at about 00 ° C. for about 3 minutes to 12 hours. Of course, the optimum heat treatment conditions also differ depending on the state of the conductive film and the desired internal stress.

Furthermore, the internal stress is changed by introducing an impurity element. Impurity elements may be introduced by a plasma doping method, an ion implantation method, an ion shower doping method, or the like. Further, as the impurity element to be introduced, one or more kinds of elements selected from the impurity element that imparts n-type, the impurity element that imparts p-type, and the rare gas element are used, and the acceleration voltage is 30 to 30 to.
120 keV, dose amount is 1 × 10 ^{12 to} 9 × 10 ¹⁶ / cm ^2, and peak concentration is 1 × 1.
Perform so as to be 0 ¹⁷ to 1 × 10 ²² / cm ^3. (FIG. 2 (D)) Further, by introducing an impurity element after the heat treatment, the internal stress can be changed by channeling with a small dose amount and a low acceleration voltage.

The internal stress of the conductive film thus formed becomes a desired internal stress, and the stress exerted on the semiconductor film can be reduced. When a TFT is manufactured using such a conductive film, its electrical characteristics are improved and the operating characteristics of the semiconductor device can be significantly improved.

The present invention having the above configuration will be described in more detail by the following examples.

Examples of the present invention will be described below, but it goes without saying that the present invention is not particularly limited to these examples.

The experiments performed to show the effectiveness of the present invention will be described. In this embodiment, W (tungsten) is used as the conductive film and Ar is used as the impurity element, but the present invention is not particularly limited thereto.

First, W was formed on the synthetic quartz substrate 10 by a sputtering method with a film thickness of 300 nm. Next, a silicon nitride film having a film thickness of 70 nm (composition ratio Si = 32.8%, O = 63.) By the CVD method.
After forming 7%, H = 3.5%), heat treatment was performed at 950 ° C. for 30 minutes. Then, the silicon nitride film was removed. The reason why the silicon nitride film is formed on W is to prevent W from peeling due to the heat treatment. Impurity elements are introduced by the ion shower doping method, and the conditions are shown in Table 1. Further, the impurity elements were introduced under three conditions: before the heat treatment, after the heat treatment, and after removing the silicon nitride film. The result is shown in FIG. Here, when the change in internal stress is an increase in tensile stress, it is set to +, and when it is an increase in compressive stress, it is set to-.

From FIG. 3, it can be seen that when Ar is introduced, the internal stress changes in the direction of the compressive stress under all conditions. When the impurity element is introduced after the heat treatment, the crystallinity is improved by the heat treatment, so that the impurity element can be easily introduced deep into the film, and the internal stress changes greatly in the direction of the compressive stress. However, when Ar is introduced through the silicon nitride film, the amount of Ar introduced in W is substantially small, so that the change in the direction of the compressive stress is also small.

Subsequently, FIG. 4 shows the change in internal stress before and after the heat treatment in the above experiment. In addition, changes in internal stress were also investigated when only heat treatment was performed without introducing impurity elements. From FIG. 4, at an acceleration voltage of 30 keV, the increase in tensile stress is larger than when no impurity element is introduced. It is considered that this is because the compressive stress increased due to the introduction of the impurity element, and the tensile stress due to the heat treatment also increased. Further, since the change in the tensile stress direction is small at 80 keV, it is considered that when the acceleration voltage is high, the impurity element is introduced deep enough into the film and is not easily affected by the heat treatment.

As described above, it was confirmed that the compressive stress increases as the internal stress increases due to the introduction of the impurity element, and the tensile stress increases as the internal stress increases due to the heat treatment. That is, the internal stress can be controlled by performing both the introduction of the impurity element, the introduction of the impurity element, and the heat treatment, and a conductive film having a desired internal stress can be obtained.

In this embodiment, the case where the present invention is applied to the gate electrode of the TFT will be described with reference to FIG.

First, the underlying insulating film 11 is formed on the substrate 10. As the substrate 10, a glass substrate, a quartz substrate, a single crystal silicon substrate, a metal substrate, or a stainless steel substrate on which an insulating film is formed may be used. Further, a plastic substrate having heat resistance that can withstand the processing temperature may be used.

Further, as the base insulating film 11, a base insulating film 11 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxide film is formed. Here, an example in which a single-layer structure is used as the underlying insulating film 11 is shown, but a structure in which two or more layers of the insulating film are laminated may be used. It is not necessary to form the underlying insulating film. In this embodiment, the silicon oxide film 11 having a film thickness of 150 nm (
Composition ratio Si = 32%, O = 27%, N = 24%, H = 17%).

Next, after forming a semiconductor film on the underlying insulating film 11, etching is performed to form the semiconductor layer 20,
Get 21. Here, it is assumed that the semiconductor layer 20 forms an n-channel type TFT, and the semiconductor layer 21 forms a p-channel type TFT. The semiconductor film is formed by forming a semiconductor film having an amorphous structure by a known means (spatter method, LPCVD method, plasma CVD method, etc.) and then a known crystallization treatment (laser crystallization method, thermal crystallization method, etc.). , Or a thermal crystallization method using a catalyst such as nickel) to form a crystalline semiconductor film. The thickness of the semiconductor film 12 is 2
It is formed at 5 to 200 nm (preferably 30 to 100 nm). The material of the semiconductor film is not limited, but it is preferably formed of silicon, silicon germanium (SiGe) alloy, or the like.
In this embodiment, a semiconductor film having a crystal structure is formed by irradiating a laser beam, and patterning is performed to form semiconductor layers 20 and 21.

Then, the insulating film 22 that covers the semiconductor layer 12 is formed. The insulating film 22 is formed by a single layer or laminated structure of an insulating film containing silicon with a thickness of 40 to 150 nm by using a plasma CVD method or a sputtering method. The insulating film 13 is a gate insulating film. In this example, a silicon oxide film (composition ratio Si = 32%, O = 59%) having a thickness of 110 nm by the plasma CVD method.
, N = 7%, H = 2%).

Subsequently, a sputtering method, a plasma CVD method, or the like is used on the insulating film 22, and the film thickness is 250 to 600.
A conductive film 23 having a nm is formed. Here, an example in which a single-layer structure is used as the conductive film 23 is shown, but a structure in which two or more layers of the conductive film 23 are laminated may be used.
Further, the conductive film may be formed of an element selected from Ta, W, Ti, Mo, Al, Cu, Cr and Nd, or an alloy material or compound material containing the element as a main component. Also,
A semiconductor film typified by a polycrystalline silicon film into which an impurity element such as phosphorus has been introduced may be used. Moreover, you may use AgPdCu alloy. In this example, the film thickness is 400 nm by the sputtering method.
To form a Ta film. Further, the film formed by the sputtering method often has compressive stress.

Next, the conductive film 23 is etched by a patterning process using a photolithography method to form the first conductive film 24 and the second conductive film 25. (Fig. 6 (
B))

Then, the first impurity element is introduced to form the impurity region 27 on the semiconductor film. Impurity elements may be introduced by a plasma doping method, an ion implantation method, an ion shower doping method, or the like. In this embodiment, As is used as an impurity element that imparts n-type.
Further, in the introduction of the first impurity element, the amount introduced in the introduction of the first impurity element is set to be larger than the amount of the impurity element introduced in the introduction of the second impurity element. By introducing the first impurity element, an impurity region 27 for functioning as an n-channel TFT is formed.
As is also introduced into the first conductive film 24 and the second conductive film 25, and the compressive stress 15 increases.

Subsequently, the second impurity element is introduced to form the impurity region 28 on the semiconductor film. At this time, since the semiconductor layer 20 forming the n-channel TFT is covered with the mask 26b made of resist, no impurity element is introduced. In this embodiment, B is used as an impurity element that imparts p-type. By introducing a second impurity element, a p-channel TFT
Although the impurity region 28 for functioning as is formed, B is also introduced into the second conductive film 25, and the compressive stress 15 of the second conductive film 25 is further increased.

In this way, the impurity region is formed, and more impurity elements are introduced into the second conductive film 25 than the first conductive film 24.

Subsequent heat treatment restores the crystallinity of the semiconductor film and activates the impurity elements. In addition, the heat treatment also changes the internal stresses of the first conductive film 24 and the second conductive film 25. However, since the amounts of the impurity elements introduced into the first conductive film 24 and the second conductive film 25 are different, the internal stress after the heat treatment is also different. Since the amount of impurity elements introduced into the first conductive film 24 is small, the heat treatment significantly changes the tensile stress in the direction of increase 16, and the internal stress in the first conductive film 24 becomes the tensile stress. so that,
The stress received by the semiconductor film forming the n-channel TFT is tensile stress. Also, the second
Since the amount of impurity elements introduced into the conductive film 25 is large, the internal stress does not change much due to the heat treatment, and the internal stress in the second conductive film 25 becomes a compressive stress. Therefore, the stress received by the semiconductor film forming the n-channel TFT is compressive stress.

In this way, the internal stress of the conductive film is controlled, the stress received by the semiconductor film forming the n-channel type TFT is set as the tensile stress, and the stress received by the semiconductor film forming the p-channel type TFT is set as the compressive stress. Can be done. When a TFT is manufactured using such a semiconductor film, its electrical characteristics are improved, and the operating characteristics of the semiconductor device can be significantly improved.

In this embodiment, the case where the present invention is applied to the wiring of the TFT will be described with reference to FIG.

An underlying insulating film was formed on the substrate, a semiconductor layer was formed on the underlayer insulating film, an insulating film was formed over the semiconductor layer, and a conductive layer was formed on the semiconductor layer via the insulating film. After that, the impurity element is introduced into the semiconductor film using the conductive layer as a mask. Further, the method shown in Example 2 may be followed.

Subsequently, an interlayer insulating film 29 made of an inorganic insulating film material or an organic insulating material is formed. In this embodiment, the interlayer insulating film 29 has a single-layer structure, but a laminated structure of two or more layers may be used.

Then, a conductive film that is electrically connected to each impurity region is formed. The conductive film may have a strong tensile stress. Therefore, an impurity element is introduced to change the internal stress of the conductive film in the direction of increasing the compressive stress. The internal stress can be controlled by such a method to form a conductive film having an internal stress of ± 1 GPa or less, and patterning is performed to wire 31 to 33.
Prevents the wiring pattern from shifting when forming.

Further, the internal stress of the conductive layer thus formed is ± 1 GPa or less, and it is possible to reduce the stress exerted on the interlayer insulating film and the semiconductor film.
When a TFT is manufactured using such a conductive layer, its electrical characteristics are improved, and the operating characteristics of the semiconductor device can be significantly improved.

In this embodiment, a case where the present invention is applied to a gate electrode of a TFT having a structure different from that of the second embodiment will be described with reference to FIG.

First, the conductive film 35 is formed on the substrate 10. As the substrate 10, a glass substrate, a quartz substrate, a single crystal silicon substrate, a metal substrate, or a stainless steel substrate on which an insulating film is formed may be used. Further, a plastic substrate having heat resistance that can withstand the processing temperature may be used.

Further, as the conductive film 35, a sputtering method, a plasma CVD method, or the like is used, and the film thickness is 250 to 6.
After forming the 00 nm conductive film 20, it is formed by performing a patterning process by a photolithography method. Here, an example in which a single-layer structure is used as the conductive film 35 is shown, but a structure in which two or more layers of the conductive film are laminated may be used. Further, as the conductive film, Ta, W, Ti, Mo,
It may be formed of an element selected from Al, Cu, Cr, and Nd, or an alloy material or compound material containing the element as a main component.
Further, a semiconductor film typified by a polycrystalline silicon film into which an impurity element such as phosphorus has been introduced may be used. Moreover, you may use AgPdCu alloy. In this embodiment, the film thickness is 40 by the sputtering method.
A 0 nm Al—Ti film is formed.

Subsequently, an impurity element is introduced to reduce the internal stress in the conductive film in the direction of increasing the compressive stress15.
Change to. This is a process to be performed in advance in order to alleviate the internal stress because the internal stress in the conductive film changes in the direction of increasing the tensile stress due to the heat treatment in the subsequent step.

Then, the insulating film 36 that covers the conductive film 35 is formed. The insulating film 36 is formed by a single layer or laminated structure of an insulating film containing silicon with a thickness of 40 to 150 nm by using a plasma CVD method or a sputtering method. The insulating film 36 serves as a gate insulating film. In this example, a silicon oxide film having a thickness of 110 nm by the plasma CVD method (composition ratio Si = 32%, O = 59%,
N = 7%, H = 2%).

Next, the semiconductor film 37 is formed on the insulating film 36. The semiconductor film 37 is formed by forming a semiconductor film having an amorphous structure by a known means (spatter method, LPCVD method, plasma CVD method, etc.) and then a known crystallization treatment (laser crystallization method, thermal crystallization method, etc.). A crystalline semiconductor film is formed by performing a method or a thermal crystallization method using a catalyst such as nickel). The thickness of the semiconductor film 37 is 25 to 200 nm (preferably 30 to 100 nm). The material of the semiconductor film is not limited, but it is preferably formed of silicon, silicon germanium (SiGe) alloy, or the like. In this embodiment, after forming a 55 nm amorphous silicon film by using the plasma CVD method,
The nickel-containing solution is retained on the amorphous silicon film. Dehydrogenation (50) on this amorphous silicon film
After performing (0 ° C., 1 hour), thermal crystallization (550 ° C., 4 hours) is performed. By heat treatment, the semiconductor film 37 becomes a semiconductor film having a crystal structure. Further, since the impurity element is introduced in advance, the amount of change in the internal stress in the conductive film 35 can be small.

The internal stress of the conductive film thus formed becomes a desired internal stress, and the stress exerted on the semiconductor film can be reduced. When a TFT is manufactured using such a conductive film, its electrical characteristics are improved and the operating characteristics of the semiconductor device can be significantly improved.

In this embodiment, the present invention is an insulated gate field effect transistor (MOSFET or IG).
An example in which a CMOS circuit is configured by applying it to a FET) will be described with reference to FIGS. 21 to 23.

First, a single crystal silicon substrate 401 is prepared, and an impurity element is injected into the P-type well 402.
Form an N-shaped well 403. The single crystal silicon substrate may be P-type or N-type. Such a configuration is a so-called twin-tab structure, and the well concentration is formed at 1 × 10 ¹⁸ / cm ³ or less (typically 1 × 10 ^{16 to} 5 × 10 ¹⁷ / cm ³ ).

Next, selective oxidation is performed by a known LOCOS method or the like to form a field oxide film 404, and then a 30 nm-thick oxide film (later gate insulating film) 4 is formed on the silicon surface by a thermal oxidation step.
05 is formed. (Fig. 21 (A))

Next, the first gate electrode 406 and the second gate electrode 407 are formed. In this embodiment, a conductive silicon film is used as the material constituting the gate electrode, but Ta,
An element selected from W, Ti, Mo, Al, Cu, Cr, and Nd, or an alloy material or compound material containing the element as a main component can be used.

After the formation of the first gate electrode 406 and the second gate electrode 407, the region to be a p-channel MOSFET (on the right side in the drawing) is covered with a resist mask 408 to form an n-type with respect to the single crystal silicon substrate 401. Introduce the impurity element to be added. (FIG. 21 (B)) As a method for introducing an impurity element, any one of a laser doping method, a plasma doping method, an ion implantation method and an ion shower doping method is used, and the concentration is 5 × 10 ¹⁸ to 1 × 10.
Introduce so that it becomes ¹⁹ / cm ^3. In this embodiment, As is used as an impurity element that imparts n-type.
Is used. A part of the impurity regions 410 and 411 thus formed (the end on the side in contact with the channel forming region) later functions as an LDD region of the n-channel MOSFET.

Next, the region to be the n-channel MOSFET is covered with the resist mask 412.
Then, an impurity element that imparts p-type to the single crystal silicon substrate 401 is introduced. (FIG. 21 (C)) In this embodiment, B (boron) is used as the impurity element that imparts the n-type.
In this way, impurity regions 414 and 415 that later function as LDD regions of the p-channel MOSFET are formed.

When the state shown in FIG. 21 (C) is obtained, a silicon oxide film (not shown) is then deposited and etched back to form sidewalls 416 and 417. (Fig. 22 (A))
)

Next, the region to be a p-channel MOSFET is covered with a resist mask 418 again, and an impurity element that imparts n-type is introduced at a concentration of ^{1 × 10 20} / cm ^3. In this way, the source area 41
9. A drain region 420 is formed, and an LDD region 421 is formed under the sidewall 416. (Fig. 22 (B))

Similarly, the region to be an n-channel MOSFET is covered with a resist mask 422, and an impurity element that imparts p-type is introduced at a concentration of ^{1 × 10 20} / cm ^3. In this way, the drain region 42
3. A source region 424 is formed, and an LDD region 425 is formed under the sidewall 417. (FIG. 22 (C)) Further, one or a plurality of elements selected from the rare gas elements are introduced while being covered with the resist mask 422. In this way, the second gate electrode 40
7 is introduced with a larger amount of impurity elements than the first gate electrode 406. As a result, the second
The compressive stress of the gate electrode 407 is stronger than that of the first gate electrode 406, and the p-channel type M
The compressive stress received by the channel forming region in the OSFET is also stronger than the stress received by the channel forming region in the n-channel MOSFET.

When the state shown in FIG. 22C is obtained, the first heat treatment is performed to activate the introduced impurity elements.

Subsequently, a titanium film is formed and a second heat treatment is performed to form a titanium silicide layer 426 on the surface of the source region, the drain region and the gate electrode. Of course, it is also possible to form a metal silicide using another metal film. After forming the silicide layer, the titanium film is removed.

By the first heat treatment and the second heat treatment, the first gate electrode 406 and the second
The internal stress of the gate electrode 407 also changes, but the change in the internal stress is small because the amount of impurity elements introduced into the second gate electrode 407 is larger than that of the first gate electrode 406. Therefore, the second
The compressive stress of the gate electrode 407 is stronger than that of the first gate electrode 406, and the p-channel type MOS
The compressive stress received by the channel forming region in the FET is also stronger than the stress received by the channel forming region in the n-channel MOSFET.

Next, an interlayer insulating film 427 is formed, a contact hole is opened, and source electrodes 428 and 42 are formed.
9. The drain electrode 430 is formed. Of course, it is also effective to perform hydrogenation after forming the electrode.

By the above steps, a CMOS circuit as shown in FIG. 23 can be obtained. The electrical characteristics of the CMOS circuit in which the internal stress of the gate electrode is controlled are improved, and the operating characteristics of the semiconductor device can be significantly improved.

In this embodiment, a method of manufacturing the active matrix substrate will be described with reference to FIGS. 9 to 8. In the present specification, a substrate in which a CMOS circuit, a drive circuit, a pixel TFT, and a pixel portion having a holding capacitance are formed on the same substrate is referred to as an active matrix substrate for convenience.

First, in this embodiment, a substrate 501 made of glass such as barium borosilicate glass represented by Corning's # 7059 glass or # 1737 glass, or aluminoborosilicate glass is used. As the substrate 501, a quartz substrate, a single crystal silicon substrate, a metal substrate, or a stainless steel substrate on which an insulating film is formed may be used. Further, a plastic substrate having heat resistance that can withstand the processing temperature of this example may be used. In this embodiment, a synthetic quartz glass substrate is used.

Next, a lower light-shielding film is formed on the quartz substrate 501. First, the film thickness is 10 to 150 nm (preferably 50 to 10 nm) composed of an insulating film such as a silicon oxide film, a silicon nitride film or a silicon nitride film.
A base film of 0 nm) is formed. Then, Ta, W, Cr, which can withstand the processing temperature of this embodiment,
A lower light-shielding film is formed with a film thickness of about 300 nm by using a conductive material such as Mo and a laminated structure thereof. The lower light-shielding film also has a function as a gate wiring. In this embodiment, a crystalline silicon film having a film thickness of 75 nm is formed, and then WSix (x = 2.0 to 2.8) having a film thickness of 150 nm is formed, and then an unnecessary portion is etched to form a lower light-shielding film. Form 503. In this embodiment,
A single-layer structure is used as the lower light-shielding film 503, but a structure in which two or more layers of the insulating film are laminated may be used.

Then, a base film 504 having a film thickness of 10 to 650 nm (preferably 50 to 600 nm) is formed on the substrate 501 and the lower light-shielding film 503, which is composed of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxide film. In this embodiment, a single-layer structure is used as the base film 504, but a structure in which two or more layers of the insulating film are laminated may be used. In this embodiment, the base film 504 is a film thickness 5 formed _{by using the plasma CVD method and using SiH 4} , NH ₃ , and N _{2 O as reaction gases.}
80 nm silicon oxide nitride film 504 (composition ratio Si = 32%, O = 27%, N = 24%, H =
17%) is formed at 350 ° C.

Next, the semiconductor film 505 is formed on the base film 504. The semiconductor film 505 forms a semiconductor film having an amorphous structure with a thickness of 25 to 80 nm (preferably 30 to 60 nm) by a known means (sputtering method, LPCVD method, plasma CVD method, etc.). The material of the semiconductor film is not limited, but it is preferably formed of silicon, silicon germanium (SiGe) alloy, or the like.

Then, the semiconductor film is crystallized by performing a thermal crystallization method using a catalyst such as nickel. Further, in addition to the thermal crystallization method using a catalyst such as nickel, known crystallization treatments (laser crystallization method, thermal crystallization method, etc.) may be combined. In this example, a nickel acetate solution (weight conversion concentration 10 ppm, volume 5 ml) is applied to the entire surface of the film by spin coating to form a metal-containing layer 405, which is exposed to a nitrogen atmosphere at a temperature of 600 ° C. for 12 hours.

When the laser crystallization method is also applied, a pulse oscillation type or continuous emission type excimer laser, a YAG laser, a YVO ₄ laser, or the like can be used. When these lasers are used, it is preferable to use a method in which the laser beam emitted from the laser oscillator is linearly focused by an optical system and irradiated to the semiconductor film. The crystallization conditions are appropriately selected by the practitioner, but when using an excimer laser, the pulse oscillation frequency is set to 300 Hz and the laser energy density is 100 to 800 mJ / cm ² (typically 200 to 700 ^{mJ / cm 2).} ). When a YAG laser is used, the second harmonic is used and the pulse oscillation frequency is set to 1 to 300 Hz, and the laser energy density ^{is preferably set to 300 to 1000 mJ / cm 2} (typically 350 to 800 mJ / cm ² ). Then, a laser beam linearly focused with a width of 100 to 1000 μm, for example, 400 μm is irradiated over the entire surface of the substrate, and the superposition rate (overlap rate) of the linear laser beams at this time is set to 50 to 98%. May be good.

Subsequently, gettering is performed in order to remove or reduce the metal element used for promoting crystallization from the semiconductor layer to be the active region. For gettering, see Japanese Patent Application Laid-Open No. 10-27
The method disclosed in Japanese Patent Application Laid-Open No. 0363 may be applied. In this embodiment, a silicon oxide film having a film thickness of 50 nm is formed as a mask, and patterning is performed to obtain a silicon oxide film 50 having a desired shape.
Obtain 6a-506d. Then, an element (typically P) that selectively belongs to Group 15 in the semiconductor film.
By introducing (phosphorus)) and performing heat treatment, it is possible to remove metal elements from the semiconductor layer or reduce them to the extent that they do not affect the semiconductor characteristics. The TFT having the active region thus produced has a low off-current value and good crystallinity, so that a high field effect mobility can be obtained.
Good characteristics can be achieved.

Then, the crystalline semiconductor film is etched to form the semiconductor layers 507a to 510a. (Fig. 9 (D))

Next, it is desirable to remove the masks 506a to 506d, form a new insulating film 511, and perform heat treatment to improve the crystallinity of the semiconductor film to thermally oxidize the upper part of the semiconductor layer. In this embodiment, a 20 nm silicon oxide film is formed with a reduced pressure CVD apparatus, and then heat treatment is performed with a furnace annealing furnace. By this treatment, the upper part of the semiconductor layers 507a to 510a is oxidized. Then, when the silicon oxide film and the oxidized portion of the semiconductor layer are etched, the semiconductor layers 507b to 510b having improved crystallinity can be obtained.

After forming the semiconductor layers 507b to 510b, a trace amount of impurity element (boron or phosphorus) may be introduced to control the threshold value of the TFT.

Next, the first gate insulating film 511 that covers the semiconductor layers 507b to 510b is formed. The first gate insulating film 511 uses a plasma CVD method or a sputtering method and has a thickness of 20 to 15.
It is formed of an insulating film containing silicon at 0 nm. In this example, 35 by the plasma CVD method
Silicon oxide film with a thickness of nm (composition ratio Si = 32%, O = 59%, N = 7%, H = 2%)
Formed in. Of course, the gate insulating film is not limited to the silicon oxide film, and an insulating film containing other silicon may be used.

When a silicon oxide film is used, TEOS (Tetraethyl Ortho) is used by the plasma CVD method.
It can be formed by mixing silicate) and O ₂ at a reaction pressure of 40 Pa, a substrate temperature of 300 to 400 ° C., and ^{discharging at a high frequency (13.56 MHz) power density of 0.5 to 0.8 W / cm 2.} The silicon oxide film thus produced can subsequently obtain good properties as a gate insulating film by thermal annealing at 400 to 500 ° C.

Then, the gate insulating film is partially etched to expose the semiconductor layer 510a which is one of the electrodes having a holding capacity, and an impurity element is introduced into the semiconductor layer 510a. (Fig. 10 (B)
)) At this time, the resist 513 is formed in the other region, and the impurity element is not introduced. In this embodiment, P (phosphorus) is used as the impurity element, and the impurity element is introduced at an acceleration voltage of 10 keV and a dose amount of 5 × 10 ¹⁴ / cm ^2.

Subsequently, the second gate insulating film 512 is formed. The second gate insulating film 512 is formed of an insulating film containing silicon with a thickness of 20 to 150 nm by using a plasma CVD method or a sputtering method. In this example, a silicon oxide film having a thickness of 50 nm by the plasma CVD method (composition ratio Si = 32%, O = 59%, N = 7%, H = 2%).
Formed in. Of course, the gate insulating film is not limited to the silicon oxide film, and an insulating film containing other silicon may be used.

Then, after forming a contact to be connected to the lower light-shielding film, a first film having a film thickness of 20 to 100 nm is formed.
The conductive film 515 and the second conductive film 516a having a film thickness of 100 to 400 nm are laminated and formed.
In this embodiment, a first conductive film 515 made of a TaN film having a film thickness of 30 nm and a film thickness of 370 nm.
A second conductive film 516a made of the W film of No. 1 is laminated. The TaN film is formed by the sputtering method and
Sputtering was performed in a nitrogen-containing atmosphere using a Ta target. Further, the W film is formed by a sputtering method using a W target. Alternatively, it can be formed by a thermal CVD method using tungsten hexafluoride (WF _6). In any case, it is necessary to reduce the resistivity in order to use it as a gate electrode, and it is desirable that the resistivity of the W film is 20 μΩcm or less.

In this embodiment, the first conductive film 515 is TaN and the second conductive film 516a is W, but the present invention is not particularly limited, and all of them are Ta, W, Ti, Mo, Al, Cu, Cr, and Nd. It may be formed of an element selected from the above, or an alloy material or a compound material containing the element as a main component. Further, a semiconductor film typified by a crystalline silicon film into which an impurity element such as phosphorus has been introduced may be used. Moreover, you may use AgPdCu alloy. In addition, the first conductive film is tantalum (Ta).
) Film, the second conductive film is a W film, and the first conductive film is titanium nitride (Ti).
A combination of N) film and a second conductive film as a W film, and the first conductive film is tantalum nitride (Tantalum nitride).
A combination of a TaN) film and a second conductive film as an Al film, a first conductive film formed of a tantalum nitride (TaN) film, and a second conductive film as a Cu film may be used.

Here, in order to obtain the desired internal stress in the second conductive film 516a, a third impurity element is introduced. Impurity elements may be introduced by a plasma doping method, an ion implantation method, or an ion shower doping method. This makes it possible to form a second conductive film 516b that changes in the direction of increasing compressive stress and has a desired internal stress. (Fig. 10 (
D)) In this embodiment, the acceleration voltage is 70 keV, and an impurity element is introduced using Ar.

Next, a mask (not shown) made of resist is formed using a photolithography method.
Etching is performed to form the electrodes and wiring. In this embodiment, ICP (Inductively Coupled Plasma) etching method is used as the etching condition.
_{CF 4} , Cl _2, and O ₂ are used as the etching gas, and the respective gas flow rate ratios are 25/25 /.
It was set to 10 (sccm), and 500 W RF (13.56 MHz) power was applied to the coil type electrode at a pressure of 1 Pa to generate plasma and perform etching. 150 on the substrate side (sample stage)
The RF (13.56MHz) power of W is applied, and a substantially negative self-bias voltage is applied.

Then, the fourth impurity element is introduced, and the impurity element that imparts n-type to the semiconductor layer is introduced. (Fig. 11 (A)) The conditions for introducing impurity elements are 1 × 10 ^{13 to} 5 × 10 ¹⁴ / cm ²
Then, the acceleration voltage is set to 30 to 80 keV. In this example, the dose amount is 1.5 × 10 ¹³
Set to / cm ² and set the acceleration voltage to 60 keV. An element belonging to Group 15 as an impurity element that imparts n-type, typically phosphorus (P) or arsenic (As), is used, but here phosphorus (P) is used.
) Is used. In this case, the conductive layers 517 to 521 serve as a mask for impurity elements that impart n-type, and low-concentration impurity regions 523 to 524 are formed in a self-aligned manner. Impurity elements that impart n-type in a concentration range of ^{1 × 10 18} to 1 × 10 ²⁰ / cm ³ are added to the low-concentration impurity regions 523 to 524. Here, a mask 522 made of a resist is formed on the semiconductor layer forming the p-channel type TFT, and an impurity element that imparts the n-type is not introduced.

Next, the mask made of the resist is removed, a new mask is formed, and the fifth impurity element is introduced as shown in FIG. 11 (B). The conditions for introducing the impurity element are that the dose amount is 1 × 10 ¹³ to 1 × 10 ¹⁵ / cm ² and the acceleration voltage is 30 to 120 keV. At this time, a mask 525b is formed so as not to introduce an impurity element that imparts n-type to the semiconductor layer forming the p-channel TFT, and a high concentration is selectively applied to the semiconductor layer for forming the n-channel TFT. Masks 525a and 525c are formed to form the impurity region. In this example, the dose amount was 2 × 10 ¹⁵ / cm ² , and the acceleration voltage was 50 keV. In this way, high-concentration impurity regions 526 and 529 are formed.

Next, after removing the mask made of resist, a new mask made of resist 532
A and 532b are formed, and as shown in FIG. 11C, the sixth impurity element is introduced. By introducing the sixth impurity element, an impurity region 533 is formed in which an impurity element that imparts a conductive type opposite to that of the one conductive type is added to the semiconductor layer that is the active layer of the p-channel type TFT. The second conductive layer 518 is used as a mask for impurity elements, and an impurity element that imparts p-type is added to form an impurity region in a self-aligned manner. In this embodiment, the impurity region 533
Is formed by the ion shower doping method using diborane (B ₂ H _6). The conditions of the ion shower doping method are that the dose amount is 1 × 10 ¹³ to 1 × 10 ¹⁴ / cm ² and the acceleration voltage is 30 to 1.
Perform as 20 keV. At the time of introducing the sixth impurity element, the semiconductor layer forming the n-channel TFT is covered with masks 532a and 532b made of resist.

Next, the mask made of resist is removed, a new mask is formed, and the seventh impurity element is introduced as shown in FIG. 12 (A). The conditions for introducing the impurity element are that the dose amount is 1 × 10 ¹³ to 1 × 10 ¹⁵ / cm ² and the acceleration voltage is 20 to 120 keV. At this time, masks 534a and 534c are formed so as not to introduce an impurity element that imparts p-type to the semiconductor layer forming the n-channel TFT, and the semiconductor layer for forming the p-channel TFT is selectively formed. A mask 534b is formed to form a high concentration impurity region. In this embodiment, the dose amount is 1 × 10 ¹⁵ / cm ² , and the acceleration voltage is 40 keV. In this way, the high-concentration impurity region 535 is formed.

In the steps up to the above, a high-concentration impurity region and a low-concentration impurity region are formed in each semiconductor layer.

Next, the mask 534 made of the resist is removed to form the first interlayer insulating film 538. The first interlayer insulating film 538 is formed of an insulating film containing silicon with a thickness of 100 to 200 nm by using a plasma CVD method or a sputtering method.
In this example, a silicon oxide film having a film thickness of 150 nm was formed by a plasma CVD method. Of course, the first interlayer insulating film 538 is not limited to the silicon oxide nitride film, and an insulating film containing other silicon may be used as a single layer or a laminated structure.

Next, as shown in FIG. 12B, heat treatment is performed to restore the crystallinity of the semiconductor layers and activate the impurity elements added to each semiconductor layer. This heat treatment is performed by a thermal annealing method using a furnace annealing furnace. The thermal annealing method is performed in a nitrogen atmosphere having an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less, at 400 to 700 ° C., typically 500 to 55.
The activation treatment may be carried out at 0 ° C., and in this example, the activation treatment was carried out by heat treatment at 550 ° C. for 4 hours. In addition to the thermal annealing method, the laser annealing method or the rapid thermal annealing method (RTA)
Law) can be applied.

Further, the heat treatment may be performed before forming the first interlayer insulating film. However, if the wiring material used is sensitive to heat, heat treatment is performed after forming an interlayer insulating film (an insulating film containing silicon as a main component, for example, a silicon nitride film) in order to protect the wiring and the like as in this embodiment. It is preferable to carry out.

Then, hydrogenation can be performed by performing a heat treatment (heat treatment at 300 to 550 ° C. for 1 to 12 hours). This step is a step of terminating the dangling bond of the semiconductor layer with hydrogen contained in the first interlayer insulating film 461. Of course, the semiconductor layer can be hydrogenated regardless of the presence of the first interlayer insulating film. Other means of hydrogenation include plasma hydrogenation (using plasma-excited hydrogen) or 300-450 in an atmosphere containing 3-100% hydrogen.
Heat treatment may be performed at ° C. for 1 to 12 hours.

Next, a second interlayer insulating film 539 made of an inorganic insulating film material or an organic insulating material is formed on the first interlayer insulating film 538. In this embodiment, a silicon nitride film having a film thickness of 1 μm is formed.

Then, in the drive circuit 555, the wiring 54 that is electrically connected to each impurity region.
Form 0 to 542. Further, in the pixel portion 556, the source wiring 543 and 545 and the drain electrode 544 are formed. These wirings have a Ti film with a film thickness of 50 nm and a film thickness of 5.
A laminated film of a 00 nm alloy film (alloy film of Al and Ti) is patterned and formed.

FIG. 13 shows a top view of the state produced so far. The same reference numerals are used for the parts corresponding to FIGS. 9 to 12. The chain line AA'in FIG. 12C corresponds to the cross-sectional view cut along the chain line AA'in FIG. Further, the chain line BB'in FIG. 12C corresponds to the cross-sectional view cut along the chain line BB'in FIG.

Next, a third interlayer insulating film 560 made of an inorganic insulating film material or an organic insulating material is formed on the second interlayer insulating film 539. In this embodiment, a silicon nitride film having a film thickness of 1.8 μm is formed.

A film having high light-shielding properties such as Al, Ti, W, Cr, or black resin is patterned into a desired shape on the third interlayer insulating film 539 to form light-shielding films 561 and 562. This light-shielding film 5
61 and 562 are arranged in a mesh pattern so as to block light other than the openings of the pixels. Further, a fourth interlayer insulating film 563 is formed of an inorganic insulating material so as to cover the light-shielding film 117.

Then, a contact hole leading to the connection wiring 544 is formed, and a transparent conductive film such as ITO is applied.
Pixel electrodes 564 and 565 are formed by forming a thickness of 00 nm and patterning it into a desired shape.

As described above, the active matrix substrate in which the drive circuit 555 having the n-channel type TFT 551 and the p-channel type TFT 552 and the pixel portion 556 having the pixel TFT 553 and the holding capacity 554 are formed on the same substrate is completed.

The internal stress of the gate electrode thus formed becomes a desired internal stress, and the stress exerted on the semiconductor film can be reduced. When a TFT is manufactured using such a gate electrode, its electrical characteristics become good and the operating characteristics of the semiconductor device can be significantly improved.

In addition, this Example can be freely combined with Example 2 or Example 3.
Of course, it is also possible to manufacture an active matrix substrate using the TFT formed in Example 4 and the MOSFET formed in Example 5.

In this embodiment, a step of manufacturing a reflective liquid crystal display device from the active matrix substrate manufactured in Example 6 will be described below. FIG. 15 is used for the explanation.

First, according to Example 6, an active matrix substrate in the state shown in FIG. 14B is obtained, and then an alignment film 567 is formed on at least the pixel electrodes 564 and 565 on the active matrix substrate to perform a rubbing treatment. In this example, before forming the alignment film 567, a columnar spacer 572 for maintaining the substrate spacing was formed at a desired position by patterning an organic resin film such as an acrylic resin film. Further, instead of the columnar spacer, a spherical spacer may be sprayed on the entire surface of the substrate.

Next, the facing substrate 569 is prepared. Next, a colored layer 570 and a flattening film 573 are formed on the facing substrate 569.

Next, a counter electrode 576 made of a transparent conductive film was formed on the flattening film 573 at least in the pixel portion, an alignment film 574 was formed on the entire surface of the facing substrate, and a rubbing treatment was performed.

Then, the pixel portion, the active matrix substrate on which the drive circuit is formed, and the facing substrate are bonded together with the sealing material 568. A filler is mixed in the sealing material 568, and the two substrates are bonded together at a uniform interval by the filler and the columnar spacer. afterwards,
Liquid crystal material 575 is injected between the two substrates and completely sealed with a sealant (not shown). A known liquid crystal material may be used as the liquid crystal material 575. In this way, the reflective liquid crystal display device shown in FIG. 15 is completed. Then, if necessary, the active matrix substrate or the facing substrate is divided into a desired shape. Further, a polarizing plate (not shown) was attached only to the opposing substrate. Then, the FPC was attached using a known technique.

In the liquid crystal display device manufactured as described above, since the internal stress of the gate electrode is controlled to a desired value, it is possible to reduce the stress applied to the semiconductor film, and the operating characteristics of the liquid crystal display device. Can also be significantly improved. Then, such a liquid crystal display device can be used as a display unit of various electronic devices.

In addition, this Example can be freely combined with Example 2 or Example 3 or Example 6.

In this embodiment, an example in which a light emitting device is manufactured using the present invention will be described. In the present specification, the light emitting device refers to a display panel in which a light emitting element formed on a substrate is enclosed between the substrate and a cover material, and a display module in which an IC (Integrated Circuit) is mounted on the display panel. It is a generic term. The light emitting device has a layer (light emitting layer) containing an organic compound for obtaining luminescence (Electro Luminescence) generated by applying an electric field, an anode layer, and a cathode layer. Luminescence in organic compounds includes luminescence (fluorescence) when returning from the singlet excited state to the ground state and luminescence (phosphorus light) when returning from the triplet excited state to the ground state.
Includes emission of either or both of these.

FIG. 16 is a cross-sectional view of the light emitting device of this embodiment. In FIG. 16, the drive circuit provided on the substrate 700 is formed by using the CMOS circuit of FIG. Therefore, for the explanation of the structure, the description of the n-channel type TFT 551 and the p-channel type TFT 552 may be referred to, but the internal stress is controlled by introducing Ar into the gate electrodes of the n-channel type TFT 551 and the p-channel type TFT 552. , The stress on the semiconductor film is reduced. Therefore, it is possible to improve the electrical characteristics of the TFT. Although the single gate structure is used in this embodiment, a double gate structure or a triple gate structure may be used.

The switching TFT 603 provided on the substrate 700 is an n-channel type T in FIG. 12 (C).
It is formed using FT551. Therefore, for the explanation of the structure, the description of the n-channel type TFT 551 may be referred to, but the internal stress is controlled by introducing Ar into the gate electrode of the n-channel type TFT 551, and the stress exerted on the semiconductor film is reduced. is there. Therefore, it is possible to improve the electrical characteristics of the TFT.

In this embodiment, the double gate structure in which two channel forming regions are formed is used, but a single gate structure in which one channel forming region is formed or a triple gate structure in which three channel forming regions are formed may be used.

Further, the wirings 701 and 703 function as the source wiring of the CMOS circuit, and the wiring 702 functions as the drain wiring. Further, the wiring 704 functions as a wiring for electrically connecting the source wiring (not shown) and the source region of the switching TFT, and the wiring 705 electrically connects the drain wiring (not shown) and the drain region of the switching TFT. Functions as wiring to connect to.

The current control TFT 604 is formed by using the p-channel type TFT 552 shown in FIG. 12 (C). Therefore, for the explanation of the structure, the explanation of the p-channel type TFT 552 may be referred to, but p.
Internal stress is controlled by introducing Ar into the gate electrode of the channel type TFT 552.
The stress on the semiconductor film is reduced. Therefore, it is possible to improve the electrical characteristics of the TFT. Although the single gate structure is used in this embodiment, a double gate structure or a triple gate structure may be used.

Further, the wiring 706 is the source wiring (corresponding to the current supply line) of the current control TFT, and is an electrode electrically connected to the pixel electrode 711.

Reference numeral 711 is a pixel electrode (anode of a light emitting element) made of a transparent conductive film. As the transparent conductive film, a compound of indium oxide and tin oxide, a compound of indium oxide and zinc oxide, zinc oxide, tin oxide or indium oxide can be used. Further, a transparent conductive film to which gallium is added may be used. The pixel electrode 711 is formed on the flat interlayer insulating film 710 before the wiring is formed. In this embodiment, the flattening film 7 made of resin
It is very important to flatten the step by the TFT using 10. Since the light emitting layer formed later is very thin, the presence of a step may cause light emission failure. Therefore, it is desirable to flatten the light emitting layer before forming the pixel electrodes so that the light emitting layer can be formed on a flat surface as much as possible.

After forming the wirings 701 to 707, the bank 712 is formed as shown in FIG.
The bank 712 may be formed by patterning an insulating film or an organic resin film containing silicon having a diameter of 100 to 400 nm.

Since the bank 712 is an insulating film, care must be taken to prevent electrostatic breakdown of the element during film formation. In this embodiment, carbon particles and metal particles are added to the insulating film that is the material of the bank 712 to lower the resistivity and suppress the generation of static electricity. At this time, the resistivity is 1 × 10 ⁶ to 1 × 1.
The amount of carbon particles or metal particles added may be adjusted so as to be ^{0 12} Ωm (preferably 1 × 10 ⁸ to 1 × 10 ^{10 Ωm).}

A light emitting layer 713 is formed on the pixel electrode 711. Although only one pixel is shown in FIG. 16, in this embodiment, light emitting layers corresponding to each color of R (red), G (green), and B (blue) are made separately. Further, in this embodiment, a low molecular weight organic light emitting material is formed by a thin film deposition method.
Specifically, a 20 nm-thick copper phthalocyanine (CuPc) film is provided as a hole injection layer, and a 70 nm-thick tris-8-quinolinolatoaluminum complex (Alq _{3) as a light emitting layer is provided on the copper phthalocyanine (CuPc) film.}
) It has a laminated structure with a film.
The emission color can be controlled by adding a fluorescent dye such as quinacridone, perylene or DCM1 to _{Alq 3.}

However, the above example is an example of an organic light emitting material that can be used as a light emitting layer, and there is no need to limit it to this. A light emitting layer (a layer for causing light emission and carrier movement for that purpose) may be formed by freely combining a light emitting layer, a charge transport layer, or a charge injection layer. For example, in this example, a low molecular weight organic light emitting material is used as the light emitting layer, but a high molecular weight organic light emitting material may be used. It is also possible to use an inorganic material such as silicon carbide as the charge transport layer and the charge injection layer.
Known materials can be used as these organic light emitting materials and inorganic materials.

Next, a cathode 714 made of a conductive film is provided on the light emitting layer 713. In the case of this embodiment, an alloy film of aluminum and lithium is used as the conductive film. Of course, known MgAg films (
An alloy film of magnesium and silver) may be used. As the cathode material, a conductive film composed of elements belonging to Group 1 or Group 2 of the periodic table or a conductive film to which those elements are added may be used.

The light emitting element 715 is completed when the cathode 714 is formed. The light emitting element 715 referred to here refers to a diode formed by a pixel electrode (anode) 711, a light emitting layer 713, and a cathode 714.

It is effective to provide the passivation film 716 so as to completely cover the light emitting element 715. The passivation film 716 is made of an insulating film including a carbon film, a silicon nitride film or a silicon nitride film, and the insulating film is used as a single layer or a combination of layers.

At this time, it is preferable to use a film having good coverage as the passivation film, and it is effective to use a carbon film, particularly a DLC (diamond-like carbon) film. Since the DLC film can be formed in a temperature range of room temperature to 100 ° C. or lower, it can be easily formed on the light emitting layer 713 having low heat resistance. In addition, the DLC film has a high blocking effect on oxygen and can suppress the oxidation of the light emitting layer 713. Therefore, it is possible to prevent the problem that the light emitting layer 713 is oxidized during the subsequent sealing step.

Further, a sealing material 717 is provided on the passivation film 716, and the cover material 718 is attached. An ultraviolet curable resin may be used as the sealing material 717, and it is effective to provide a substance having a hygroscopic effect or a substance having an antioxidant effect inside. Further, in this embodiment, the cover material 718 uses a glass substrate, a quartz substrate, or a plastic substrate (including a plastic film) having a carbon film (preferably a diamond-like carbon film) formed on both sides.

In this way, a light emitting device having a structure as shown in FIG. 16 is completed. It is effective to continuously process the steps from the formation of the bank 712 to the formation of the passivation film 716 using a multi-chamber type (or in-line method) film forming apparatus without releasing to the atmosphere. .. Further, it is also possible to continuously process up to the step of further developing and laminating the cover material 718 without releasing it to the atmosphere.

Further, in this embodiment, only the configuration of the pixel portion and the drive circuit is shown, but according to the manufacturing process of this embodiment, other logic circuits such as a signal division circuit, a D / A converter, an operational amplifier, and a γ correction circuit are shown. Can be formed on the same insulator, and even a memory or a microprocessor can be formed.

Further, the light emitting device of this embodiment after performing the sealing (or sealing) step for protecting the light emitting element will be described with reference to FIG. The reference numerals used in FIG. 16 are cited as necessary.

FIG. 17A is a top view showing a state in which the light emitting element is sealed, and FIG. 17B is FIG.
It is sectional drawing which cut 7 (A) by CC'. 801 shown by a dotted line is a source side drive circuit, 806 is a pixel portion, and 807 is a gate side drive circuit. 901 is a cover material, 902
Is a first sealing material, 903 is a second sealing material, and a sealing material 907 is provided inside surrounded by the first sealing material 902.

Note that 904 is a wiring for transmitting signals input to the source side drive circuit 801 and the gate side drive circuit 807, and receives a video signal and a clock signal from an FPC (flexible printed circuit) 905 which is an external input terminal. Although only the FPC is shown here, a printed wiring board (PWB) may be attached to the FPC. The light emitting device in the present specification includes not only the light emitting device main body but also FPC or P.
It shall also include the state in which the WB is attached.

Next, the cross-sectional structure will be described with reference to FIG. 17 (B). A pixel portion 806 and a gate side drive circuit 807 are formed above the substrate 700, and the pixel portion 806 is a current control TFT 60.
It is formed by a plurality of pixels including a pixel electrode 711 electrically connected to the 4 and its drain. Further, the gate side drive circuit 807 includes an n-channel type TFT 601 and a p-channel type TFT 6
It is formed using a CMOS circuit (see FIG. 16) in combination with 02.

The pixel electrode 711 functions as an anode of the light emitting element. Banks 712 are formed at both ends of the pixel electrode 711, and the light emitting layer 713 and the cathode 714 of the light emitting element are formed on the pixel electrode 711.
Is formed.

The cathode 714 also functions as wiring common to all pixels, and FPC9 via the connection wiring 904.
It is electrically connected to 05. Further, all the elements included in the pixel portion 806 and the gate side drive circuit 807 are covered with the cathode 714 and the passivation film 567.

Further, the cover material 901 is attached by the first sealing material 902. A spacer made of a resin film may be provided in order to secure a space between the cover material 901 and the light emitting element.
The inside of the first sealing material 902 is filled with a sealing material 907. It is preferable to use an epoxy resin as the first sealing material 902 and the sealing material 907. Further, it is desirable that the first sealing material 902 is a material that does not allow moisture or oxygen to permeate as much as possible. further,
A substance having a hygroscopic effect or a substance having an antioxidant effect may be contained in the sealing material 907.

The sealing material 907 provided so as to cover the light emitting element also functions as an adhesive for adhering the cover material 901. Further, in this embodiment, FRP (Fiberglass-Reinforced Plastics), PVF (polyvinyl fluoride), mylar, polyester or acrylic can be used as the material of the plastic substrate 901a constituting the cover material 901.

Further, after the cover material 901 is adhered using the sealing material 907, the second sealing material 903 is provided so as to cover the side surface (exposed surface) of the sealing material 907. The second sealing material 903 is the first sealing material 90.
The same material as in 2 can be used.

By encapsulating the light emitting element in the sealing material 907 with the above structure, the light emitting element can be completely blocked from the outside, and substances such as moisture and oxygen that promote deterioration due to oxidation of the light emitting layer invade from the outside. You can prevent it from happening. Therefore, a highly reliable light emitting device can be obtained.

In the light emitting device manufactured as described above, since the internal stress of the gate electrode is controlled to a desired value, it is possible to reduce the stress applied to the semiconductor film, and the operating characteristics of the light emitting device are also significantly improved. Can be improved. Then, such a light emitting device can be used as a display unit of various electronic devices.

In addition, this Example can be freely combined with Example 2 or Example 3 or Example 6.

The CMOS circuit and pixel unit formed by applying the present invention can be used in various electro-optical devices (active matrix type liquid crystal display device, active matrix type EC display device, active matrix type light emitting device). That is, the present invention can be applied to all electronic devices incorporating these electro-optical devices in the display unit.

Such electronic devices include video cameras, digital cameras, projectors, head-mounted displays (goggles-type displays), car navigation systems, car stereos, personal computers, personal digital assistants (mobile computers, mobile phones, electronic books, etc.). Can be mentioned. Examples of them are shown in FIGS. 18, 19 and 20.

FIG. 18A shows a personal computer, which includes a main body 3001 and an image input unit 3002.
The display unit 3003, the keyboard 3004, and the like are included. The present invention can be applied to the display unit 3003.

FIG. 18B shows a video camera, which is a main body 3101, a display unit 3102, and an audio input unit 31.
03, operation switch 3104, battery 3105, image receiving unit 3106 and the like are included. The present invention can be applied to the display unit 3102.

FIG. 18C shows a mobile computer (mobile computer), which is the main body 3201.
, Camera unit 3202, image receiving unit 3203, operation switch 3204, display unit 3205, and the like. The present invention can be applied to the display unit 3205.

FIG. 18D is a goggle type display, which includes a main body 3301, a display unit 3302, an arm unit 3303, and the like. The present invention can be applied to the display unit 3302.

FIG. 18E is a player that uses a recording medium on which a program is recorded (hereinafter referred to as a recording medium), and is a main body 3401, a display unit 3402, a speaker unit 3403, and a recording medium 3404.
, Operation switch 3405 and the like. This player uses a DVD (Di) as a recording medium.
You can listen to music, watch movies, play games, and play the Internet using a gitial Versail Disc), a CD, or the like. The present invention can be applied to the display unit 3402.

FIG. 18F shows a digital camera, which includes a main body 3501, a display unit 3502, and an eyepiece unit 350.
3. Includes an operation switch 3504, an image receiving unit (not shown), and the like. The present invention can be applied to the display unit 3502.

FIG. 19A shows a front type projector, which is a projector 3601 and a screen 36.
Includes 02 etc. The present invention can be applied to a liquid crystal display device 3808 and other drive circuits that form a part of the projection device 3601.

FIG. 19B is a rear projector, which includes a main body 3701, a projection device 3702, a mirror 3703, a screen 3704, and the like. The present invention can be applied to a liquid crystal display device 3808 and other drive circuits that form a part of the projection device 2702.

Note that FIG. 19 (C) shows the projection device 3601 in FIGS. 19 (A) and 19 (B).
It is a figure which showed an example of the structure of 3702. The projection devices 3601 and 3702 include a light source optical system 3
It is composed of 801 and mirrors 3802, 3804 to 3806, a dichroic mirror 3803, a prism 3807, a liquid crystal display device 3808, a retardation plate 3809, and a projection optical system 3810. The projection optical system 2810 is composed of an optical system including a projection lens. Although this embodiment shows an example of a three-plate type, the present embodiment is not particularly limited, and for example, a single-plate type may be used. In addition, an optical lens, a film having a polarizing function, or a film having a polarizing function can be appropriately arranged by the practitioner in the optical path indicated by the arrow in FIG.
An optical system such as a film or an IR film for adjusting the phase difference may be provided.

Further, FIG. 19 (D) is a diagram showing an example of the structure of the light source optical system 3801 in FIG. 19 (C). In this embodiment, the light source optical system 3801 includes a reflector 3811 and a light source 38.
12. It is composed of lens arrays 3813 and 3814, a polarization conversion element 3815, and a condenser lens 3816. The light source optical system shown in FIG. 19D is an example and is not particularly limited.
For example, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting the phase difference, or an IR film in the light source optical system.

However, in the projector shown in FIG. 19, a case where a transmission type electro-optic device is used is shown, and an application example in a reflection type electro-optic device and a light emitting device is not shown.

FIG. 20A shows a mobile phone, which is a main body 3901, a voice output unit 3902, and a voice input unit 39.
03, display unit 3904, operation switch 3905, antenna 3906 and the like are included. The present invention can be applied to the display unit 3904.

FIG. 20B is a portable book (electronic book), which is a main body 4001, display units 4002, 400.
3. The storage medium 4004, the operation switch 4005, the antenna 4006, and the like are included. The present invention can be applied to the display units 4002 and 4003.

FIG. 20C shows a display, which is a main body 4101, a support base 4102, and a display unit 4103.
Etc. are included. The present invention can be applied to the display unit 4103. The display of the present invention is particularly advantageous when the screen is enlarged, and is advantageous for a display having a diagonal of 10 inches or more (particularly 30 inches or more).

As described above, the scope of application of the present invention is extremely wide, and it can be applied to electronic devices in various fields. Further, the electronic device of this embodiment can be realized by using a configuration composed of any combination of Examples 2 to 7. It is also possible to apply Example 8 to the electronic devices shown in FIGS. 18 and 20.

Claims (1)

The first conductive layer, the first insulating layer in contact with the first conductive layer, the semiconductor layer in contact with the first insulating layer, the second insulating layer in contact with the semiconductor layer, and the above. It has a second conductive layer in contact with the second insulating layer, a third insulating layer in contact with the second conductive layer, and a light emitting element on the third insulating layer.
The semiconductor layer has a transistor channel forming region and has a transistor channel forming region.
The channel forming region overlaps with the first conductive layer via the first insulating layer.
The first insulating layer has a first contact hole and has a first contact hole.
The second insulating layer has a second contact hole and has a second contact hole.
The second contact hole has a region that overlaps with the first contact hole, and has an area that overlaps with the first contact hole.
At the periphery of the region, the second insulating layer is in contact with the first insulating layer.
A display device in which the second conductive layer is in contact with the first conductive layer in the region.

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