JP2019075572A - Semiconductor device - Google Patents

Abstract

To examine internal stress of a semiconductor device including a conductive film, which is affected by the internal stress of the conductive film.SOLUTION: The semiconductor device including an n-channel type TFT provided on an insulating surface is so configured that impurity elements are introduced to a conductive film, for instance, a gate electrode so that a semiconductor film is subjected to a pulling stress. The semiconductor device including a p-channel type TFT provided on an insulating surface is so configured that impurity elements are introduced to a conductive film, for instance, a gate electrode so that a semiconductor film is subjected to a compression stress.SELECTED DRAWING: Figure 6

Description

The present invention relates to a semiconductor device having a circuit formed of thin film transistors (hereinafter referred to as TFT) and a method of manufacturing the same. In particular, the present invention relates to an electro-optical device represented by a liquid crystal display device, a semiconductor device on which such an electro-optical device is mounted as a component, and a method of manufacturing the same. Note that in this specification, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics, and electro-optical devices, semiconductor circuits, and electronic devices are all semiconductor devices.

In recent years, a thin film (a thickness of several to several hundred nm) formed on a substrate having an insulating surface is used for T
Development of a semiconductor device having a large-area integrated circuit which constitutes an FT and is formed of this TFT is in progress. As a typical example, an active matrix liquid crystal display device and a light emitting device are known. In particular, since TFTs having a crystalline silicon film as an active region have high field effect mobility, various functional circuits can be formed.

For example, in an active matrix liquid crystal display device, a pixel circuit that displays an image for each functional block, and a pixel circuit such as a shift register circuit based on a CMOS circuit, a level shifter circuit, a buffer circuit, and a sampling circuit are controlled. The drive circuit of is formed on a single substrate.

In addition, the TFT has at least a semiconductor film, an insulating film made of a silicon oxide film, a silicon oxynitride film or the like, and a wiring made of various metal materials or the like. The wiring includes a source wiring, a gate wiring (including a gate electrode), and the like. Since the thickness of these films is about several to several hundreds nm, it can be said to be a thin film.

These thin films are formed by known film forming techniques such as CVD (chemical vapor deposition) and sputtering. However, it is known that the thin film has internal stress. The internal stress includes intrinsic stress and thermal stress caused by the difference in thermal expansion coefficient between the thin film and the substrate.

The effects of thermal stress can be ignored by considering the material of the substrate, process temperature, pressure, etc., but the mechanism of intrinsic stress generation is not necessarily clarified, but rather the growth process of the film or It is considered that the phase change and the composition change due to the subsequent heat treatment etc. are generated in a complicated manner.

Generally, internal stress includes compressive stress and tensile stress. As shown in FIG. 5 (A),
When the thin film 311 is to be stretched, the substrate 312 is compressed and formed with the thin film 311 facing outward, so this is called compressive stress. On the other hand, as shown in FIG. 5B, when the thin film 311 tries to shrink with respect to the substrate 312, the substrate 312 is deformed in such a way that the thin film is inside because it is pulled in the direction to prevent it. It is. Generally, the value of tensile stress is indicated by +, and the value of compressive stress is often indicated by-.

As to the influence of such internal stress on the electrical characteristics of the transistor, for example, “0
. Influence of stress of etch stop nitride film on the performance of 13 μm CMOS transistor; 25 Special Issue on ULSI Devices (200
1) pp. 36-39. According to this, it is reported that the mobility of the NMOS transistor is improved when the channel formation region is subjected to tensile stress, and the mobility of the PMOS transistor is improved when subjected to compressive stress.

As described above, the TFT wiring is also formed of a thin film. Therefore, the wiring also has internal stress, and peeling may occur if the internal stress is strong.
In addition, the gate electrode formed of the same material as the wiring is formed over the semiconductor film through the insulating film. The internal stress of the gate electrode acts on the semiconductor film, and distortion is given to the interface between the insulating film and the semiconductor film, and the semiconductor film, thereby typifying the threshold voltage and the electric field effect mobility. Characteristics may be adversely affected.

The present invention is a technique for solving such problems and improves the operation characteristics and reliability of a semiconductor device in an electro-optical device and a semiconductor device represented by an active matrix liquid crystal display device having a wiring. The purpose is to realize an improvement in yield.

The present invention makes it possible to control the wiring to a desired internal stress by introducing the impurity element into the wiring of the TFT or performing both the introduction of the impurity element and the heat treatment. In particular,
Application to the gate electrode is extremely effective. In addition, it is possible to introduce an impurity element only in a desired region or perform heat treatment to control to a desired internal stress.

For example, by applying the present invention, it is possible to set the stress to which the channel formation region in the n-channel TFT is subjected as a tensile stress and to set the stress to which the channel formation region in the p-channel TFT is a compressive stress. In addition, the channel formation region in the n-channel TFT can be made relatively stronger in tensile stress than the channel formation region in the p-channel TFT, and the channel formation region in the p-channel TFT can be n-channel. TFT
It is also possible to make the compressive stress relatively stronger than the channel formation region in. By doing so, the electrical characteristics of the TFT can be improved, and the operating characteristics of the semiconductor device can be significantly improved.

The impurity element may be introduced by plasma doping, ion implantation, ion shower doping, or the like. In such a method of introducing an impurity element, the energy of ions implanted into the thin film is very large compared to the binding energy of the element forming the thin film. Therefore, the ions to be implanted into the thin film repel atoms forming the semiconductor film from the lattice points to be present at lattice positions, or the ions to be implanted and atoms repelled from lattice points are interlattice positions Will be present. Since the thin film is stretched in this manner, the compressive stress is increased when the thin film has a compressive stress, and the tensile stress is relieved when the thin film has a tensile stress.

In addition, since the atoms present at interstitial positions return to lattice positions by heat treatment, the regularity of atomic arrangement is improved. Therefore, since the thin film shrinks, when the thin film has a tensile stress, the tensile stress is increased, and when the thin film has a compressive stress, the compressive stress is relieved.

Further, when the impurity element is introduced after the heat treatment, accelerated ions are implanted into the film with improved atomic arrangement regularity, so the ions do not collide along the gaps of the crystal lattice. It is possible to enter deep. (Channeling) Therefore,
In the introduction of the impurity element for controlling the internal stress, the dose amount can be small, and
It is possible to do with a low acceleration voltage.

In addition, when heat treatment is performed after the impurity element is introduced, more atoms are introduced into the thin film than the atoms forming the thin film, so that the atoms existing in the interstitial position return to the lattice position or more. The atoms will be present. Therefore, since the shrinkage of the thin film is smaller than in the case where the introduction of the impurity element is not performed, the amount of increase in tensile stress is also small. That is, when it is known that heat treatment is to be performed in a later step, the amount of change in internal stress can be reduced by introducing an impurity element in advance.

As described above, it is possible to control to a desired internal stress by performing the introduction of the impurity element or both the introduction of the impurity element and the heat treatment. Needless to say, the introduction of the impurity and the heat treatment may be performed not only once but a plurality of times. The present invention applies these characteristics to a wire and controls the stress of the wire to improve the operating characteristics and reliability of the semiconductor device. In particular, by controlling the internal stress in the gate electrode of the TFT, it is possible to control the stress to which the semiconductor film is subjected. Therefore, it becomes possible to improve the electrical characteristics represented by the threshold voltage and the field effect mobility. In addition, since it is also possible to control the stress of individual gate electrodes, it is also possible to suppress variations in electrical characteristics.

A manufacturing method of the present invention disclosed in this specification is characterized in that an impurity element is introduced into a conductive film to make an internal stress in the conductive film ± 1 GPa or less.

Further, another manufacturing method of the present invention is characterized in that an impurity element is introduced into a conductive film and heat treatment is performed on the conductive film so that an internal stress in the conductive film is ± 1 GPa or less.

Further, another manufacturing method of the present invention is characterized in that the conductive film is heat-treated to introduce an impurity element into the conductive film so that the internal stress in the conductive film is ± 1 GPa or less.

In each of the above manufacturing methods, the method of introducing the impurity element can be performed by a plasma doping method, an ion implantation method, an ion shower doping method, or the like.

In each of the above manufacturing methods, the impurity element is not particularly limited, but it is an element selected from an impurity element imparting n-type, an impurity element imparting p-type, and a rare gas element. Is desirable. The impurity element imparting n-type or the impurity element imparting p-type is an impurity element indispensable for forming a source region or a drain region. Therefore, it is economical because it is not necessary to newly prepare other impurity elements. In particular, when an impurity element is introduced into the gate electrode, it can be introduced simultaneously with the step of introducing the impurity element into the source region and the drain region, which is preferable because it can be introduced without increasing the number of steps. Further, since a rare gas element is an inert element, it is preferable because it does not affect the electrical characteristics of the TFT.

Also, as the amount of introduced impurity element increases, if the internal stress in the thin film is compressive stress, the compressive stress increases, and if the internal stress in the thin film is tensile stress, the tensile stress is relaxed, It may come to have a compressive stress. That is, depending on the amount of impurity element introduced, the internal stress in the thin film may be compressive stress or tensile stress.

Further, in each of the above manufacturing methods, the value of the internal stress in the conductive film is preferably ± 1 GPa or less. Peeling is known to occur when the internal stress of the conductive film is strong, and in general, the standard that can suppress the occurrence of peeling is ± 1 GPa or less. Of course, the occurrence of peeling greatly affects the conditions under which the conductive film is formed.

In each of the above manufacturing methods, the conductive film is not limited to a single layer, and may have a stacked structure of two or more layers.

In each of the above manufacturing methods, the heat treatment may be performed by an RTA method, a laser annealing method, a thermal annealing method using a furnace annealing furnace, or the like.

Further, the heat treatment greatly affects the change in internal stress in the thin film depending on time and temperature. The longer the heat treatment time, and the higher the heat treatment temperature, the tensile stress increases when the internal stress in the thin film is a tensile stress, and the compressive stress increases when the internal stress in the thin film is a compressive stress. After relaxation, it may have tensile stress. That is, depending on the conditions of heat treatment, the internal stress in the thin film may be compressive stress or tensile stress.

  Further, the configuration of the present invention is shown below.

A semiconductor device having an n-channel TFT, wherein the n-channel TFT has a semiconductor film and a conductive film, the semiconductor film is subjected to tensile stress, and the conductive film is doped with an impurity element. It is characterized by

A semiconductor device having a p-channel TFT, wherein the p-channel TFT has a semiconductor film and a conductive film, the semiconductor film is subjected to compressive stress, and the conductive film is doped with an impurity element. It is characterized by

A semiconductor device having an n-channel TFT and a p-channel TFT, wherein the n-channel TFT includes a first semiconductor film and a first conductive film formed on the first semiconductor film. The p-channel TFT has a second semiconductor film and a second conductive film formed on the second semiconductor film, and the first semiconductor film is subjected to a tensile stress. The second
The semiconductor film is subjected to a compressive stress, and the first conductive film and the second conductive film are characterized in that an impurity element is introduced.

In each of the above configurations, the impurity element is not particularly limited, but it is preferable that the impurity element is one or more elements selected from an impurity element imparting n-type, an impurity element imparting p-type, and a rare gas element . The impurity element imparting n-type or the impurity element imparting p-type is an impurity element indispensable for forming a source region or a drain region. Therefore, it is economical because it is not necessary to newly prepare other impurity elements. In particular, when an impurity element is introduced into the gate electrode, it can be introduced simultaneously with the step of introducing the impurity element into the source region and the drain region, which is preferable because it can be introduced without increasing the number of steps. Further, since a rare gas element is an inert element, it is preferable because it does not affect the electrical characteristics of the TFT.

In addition, a semiconductor device typified by a liquid crystal display device and a light emitting device is formed using the TFT having the above-described structure.

By adopting the configuration of the present invention, basic significance as shown below can be obtained.
(A) It is a simple method adapted to the conventional preparation process.
(B) It is possible to realize the formation of a wiring having a desired internal stress. Therefore, the stress in other films can also be reduced. In addition, the patterning process of the wiring can be well performed.
(C) In addition to satisfying the above advantages, in the semiconductor device represented by the active matrix liquid crystal display device, the operation characteristics and reliability of the semiconductor device can be improved, and the yield can be improved.

The figure which shows an example of the concept of this invention. The figure which shows an example of the concept of this invention. The figure which shows the example of the variation | change_quantity to the direction of the compressive stress by introduce | transducing an impurity element. The figure which shows the example of the variation | change_quantity to the direction of the tensile stress by heat processing. The figure explaining tensile stress and compression stress. The figure which shows an example of the concept of this invention. The figure which shows an example of the concept of this invention. 7A to 7D are cross-sectional views illustrating steps of manufacturing a pixel TFT and a TFT of a driver circuit. 7A to 7D are cross-sectional views illustrating steps of manufacturing a pixel TFT and a TFT of a driver circuit. 7A to 7D are cross-sectional views illustrating steps of manufacturing a pixel TFT and a TFT of a driver circuit. 7A to 7D are cross-sectional views illustrating steps of manufacturing a pixel TFT and a TFT of a driver circuit. 7A to 7D are cross-sectional views illustrating steps of manufacturing a pixel TFT and a TFT of a driver circuit. FIG. 6 is a top view showing the configuration of a pixel TFT. 7A to 7D are cross-sectional views illustrating steps of manufacturing a pixel TFT and a TFT of a driver circuit. 7A to 7D are cross-sectional views illustrating a manufacturing process of an active matrix liquid crystal display device. FIG. 7 is a cross-sectional view of a driver circuit and a pixel portion of the light emitting device. (A) Top view of light emitting device. (B) A cross-sectional structural view of a driver circuit and a pixel portion of a light-emitting device. FIG. 7 illustrates an example of a semiconductor device. FIG. 7 illustrates an example of a semiconductor device. FIG. 7 illustrates an example of a semiconductor device. FIG. 7 is a cross-sectional view showing the manufacturing process of the MOSFET. FIG. 7 is a cross-sectional view showing the manufacturing process of the MOSFET. FIG. 7 is a cross-sectional view showing the manufacturing process of the MOSFET.

First Embodiment
An embodiment of the present invention will be described with reference to FIG. In the present embodiment, the present invention is applied to the TFT
The case where the present invention is applied to the gate electrode of

First, base insulating film 11 is formed on substrate 10. As the substrate 10, a glass substrate, a quartz substrate, a single crystal silicon substrate, a metal substrate, or a stainless steel substrate on which an insulating film is formed may be used. Alternatively, a plastic substrate having heat resistance that can withstand processing temperatures may be used.

Further, as the base insulating film 11, the base insulating film 11 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed. Although an example in which a single-layer structure is used as the base film 11 is shown here, a structure in which two or more layers of the insulating film are stacked may be used. Base insulating film 1
It is not necessary to form one.

Next, the semiconductor film 12 is formed on the base insulating film 11. The semiconductor film 12 is a publicly known means (a sputtering method, an LPCVD method, a plasma CVD method, etc.) of a semiconductor film having an amorphous structure.
After forming a film by the above method, a known crystallization process (a laser crystallization method, a thermal crystallization method, a thermal crystallization method using a catalyst such as nickel, or the like) is performed to form a crystalline semiconductor film. This semiconductor film 12
Is formed to have a thickness of 25 to 200 nm (preferably 30 to 100 nm). Although there is no limitation on the material of the semiconductor film, it is preferable to use silicon or silicon germanium (SiGe) alloy or the like.

Next, the insulating film 13 is formed on the semiconductor film 12. The insulating film 13 is formed to have a thickness of 40 to 150 nm and a single layer or a stacked structure of an insulating film containing silicon by a plasma CVD method, a sputtering method, or the like. The insulating film 13 is a gate insulating film.

Next, a sputtering method, plasma CVD method or the like is used on the insulating film 13 to a film thickness of 250 to 600.
A conductive film 14 of nm is formed. Although an example in which a single layer structure is used as the conductive film 14 is shown here, a structure in which two or more conductive films are stacked may be used.

However, when the conductive film 14 is formed by the CVD method, the tensile stress 15 may be strong. Therefore, the impurity element is introduced to reduce the internal stress in the conductive film 14 to a desired internal stress. The impurity element may be introduced by a plasma doping method, an ion implantation method, an ion shower doping method, or the like. The impurity element to be introduced is an impurity element imparting n-type conductivity, an impurity element imparting p-type conductivity, and one or more elements selected from rare gas elements, and the acceleration voltage is 30 to 120 keV and the dose amount is The concentration is 1 × 10 ^{12 to} 9 × 10 ¹⁶ / cm ² , and the peak concentration is 1 × 10 ¹⁷ to 1 × 10 ²² / cm ³ .
(FIG. 1 (C)) Of course, the optimum introduction condition of the impurity element also differs depending on the state of the conductive film and the desired internal stress. Further, it is also possible to change the internal stress of only the desired region by introducing the impurity element only to the desired region using a mask made of resist.

The internal stress of the conductive film formed in this manner becomes a desired internal stress, and the stress exerted on the semiconductor film can be reduced. Then, when a TFT is manufactured using such a conductive film, its electrical characteristics become good, and the operating characteristics of the semiconductor device can be significantly improved.

Second Embodiment
An embodiment of the present invention will be described with reference to FIG. In the present embodiment, the case of controlling the internal stress by performing heat treatment after introducing the impurity element will be described.

  First, according to Embodiment 1, the introduction of the impurity element is performed.

Subsequently, heat treatment is performed to increase the internal stress in the conductive film 14 if it is a tensile stress, and relax if it is a compressive stress. The heat treatment may be performed by a known method such as a thermal annealing method using a furnace annealing furnace, a laser annealing method, an RTA method, or the like. For example, if a thermal annealing method using a furnace annealing furnace is performed, it may be exposed to a nitrogen atmosphere at a temperature of about 500 to 1000 ° C. for about 3 minutes to 12 hours. Of course, the optimum heat treatment conditions also depend on the state of the conductive film and the desired internal stress. Further, the heat treatment for a long time can be performed simultaneously with the crystallization of the semiconductor film and the activation of the impurity element in the manufacturing process of the TFT, so that the process can be performed without an additional process, which is efficient.

In addition, if heat treatment is performed only on a desired region by a laser annealing method or the like, it is possible to change the internal stress of only the desired region.

The internal stress of the conductive film formed in this manner becomes a desired internal stress, and the stress exerted on the semiconductor film can be reduced. Then, when a TFT is manufactured using such a conductive film, its electrical characteristics become good, and the operating characteristics of the semiconductor device can be significantly improved.

Third Embodiment
An embodiment of the present invention will be described with reference to FIG. In the present embodiment, the case of controlling the internal stress by performing heat treatment after introducing the impurity element will be described.

  First, in accordance with the first embodiment, formation of the insulating film 13 is performed.

Next, a sputtering method, plasma CVD method or the like is used on the insulating film 13 to a film thickness of 250 to 600.
A conductive film 17 of nm is formed. Although an example in which a single layer structure is used as the conductive film 17 is shown here, a structure in which two or more layers of the conductive film are stacked may be used.

However, the conductive film 17 formed by sputtering may have a strong compressive stress 15. Therefore, heat treatment is performed to change the internal stress in the conductive film 17. The heat treatment is a thermal annealing method using a furnace annealing furnace, an RTA method, a laser annealing method, etc.
A known method may be used. (Figure 2 (B))

Subsequently, when heat treatment is performed, the internal stress in the conductive film 14 is increased if it is a tensile stress, and is relaxed if it is a compressive stress. The heat treatment may be performed by a known method such as a thermal annealing method using a furnace annealing furnace, a laser annealing method, an RTA method, or the like. For example, if a thermal annealing method using a furnace annealing furnace is performed, the temperature 500 to 10
It may be exposed to a nitrogen atmosphere at about 00 ° C. for about 3 minutes to 12 hours. Of course, the optimum heat treatment conditions also depend on the state of the conductive film and the desired internal stress.

Furthermore, the impurity element is introduced to change the internal stress. The impurity element may be introduced by a plasma doping method, an ion implantation method, an ion shower doping method, or the like. The impurity element to be introduced is an impurity element imparting n-type conductivity, an impurity element imparting p-type conductivity, and one or more elements selected from rare gas elements, and acceleration voltage 30 to
The peak concentration is 1 × 1 with a 120 keV dose amount of 1 × 10 ^{12 to} 9 × 10 ¹⁶ / cm ^2.
It is performed so as to be 0 ¹⁷ to 1 × 10 ²² / cm ³ . (FIG. 2D) Further, by introducing an impurity element after heat treatment, channeling can change the internal stress with a small dose and a low acceleration voltage.

The internal stress of the conductive film formed in this manner becomes a desired internal stress, and the stress exerted on the semiconductor film can be reduced. Then, when a TFT is manufactured using such a conductive film, its electrical characteristics become good, and the operating characteristics of the semiconductor device can be significantly improved.

The present invention configured as described above will be described in more detail by the following examples.

Examples of the present invention will be described below, but the present invention is of course not limited to these examples.

An experiment conducted to show the effectiveness of the present invention will be described. Although W (tungsten) is used for the conductive film and Ar is used as the impurity element in this embodiment, the present invention is not particularly limited thereto.

First, W was formed to a film thickness of 300 nm on the synthetic quartz substrate 10 by a sputtering method. Then, a silicon nitride oxide film (composition ratio Si = 32.8%, O = 63.
After forming 7%, H = 3.5%), heat treatment was performed at 950 ° C. for 30 minutes. Then, the silicon nitride oxide film was removed. The silicon nitride oxide film is formed on W in order to prevent W from peeling due to heat treatment. The introduction of the impurity element is performed by an ion shower doping method, and the conditions are shown in Table 1. In addition, the introduction of the impurity element was performed under the three conditions before the heat treatment, after the heat treatment, and after the removal of the silicon nitride oxide film. The results are shown in FIG. Here, when the change in internal stress is an increase in tensile stress, it is positive, and when it is an increase in compressive stress, it is negative.

From FIG. 3, it can be seen that when Ar is introduced, the internal stress changes in the direction of compressive stress under any conditions. When the impurity element is introduced after the heat treatment, the crystallinity is improved by the heat treatment, so that the impurity element can be easily introduced deep into the film, and the internal stress largely changes in the direction of the compressive stress. However, when Ar is introduced through the silicon nitride oxide film, the amount of Ar substantially introduced into W is small, so the change in the direction of compressive stress is also small.

Subsequently, FIG. 4 shows changes in internal stress before and after heat treatment in the above-mentioned experiment. In addition, changes in internal stress were examined also in the case where only heat treatment was performed without introducing an impurity element. As shown in FIG. 4, at an acceleration voltage of 30 keV, the increase in tensile stress is larger than in the case where no impurity element is introduced. This is considered to be because the tensile stress due to the heat treatment is also increased by the increase of the compressive stress due to the introduction of the impurity element. Further, since the change in the direction of tensile stress is small at 80 keV, the impurity element is introduced deep enough in the film when the acceleration voltage is high, so it is considered that the influence of the heat treatment is unlikely to be affected.

Thus, it has been confirmed that the introduction of the impurity element increases the compressive stress of the internal stress, and the heat treatment increases the tensile stress of the internal stress. That is, by performing the introduction of the impurity element or both the introduction of the impurity element and the heat treatment, the internal stress can be controlled, and a conductive film having a desired internal stress can be obtained.

In this embodiment, a case where the present invention is applied to a gate electrode of a TFT will be described with reference to FIG.

First, base insulating film 11 is formed on substrate 10. As the substrate 10, a glass substrate, a quartz substrate, a single crystal silicon substrate, a metal substrate, or a stainless steel substrate on which an insulating film is formed may be used. Alternatively, a plastic substrate having heat resistance that can withstand processing temperatures may be used.

Further, as the base insulating film 11, the base insulating film 11 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed. Although an example in which a single-layer structure is used as the base insulating film 11 is shown here, a structure in which two or more layers of the insulating film are stacked may be used. Note that the base insulating film may not be formed. In the present embodiment, a silicon oxynitride film 11 (film thickness 150 nm)
The composition ratio Si = 32%, O = 27%, N = 24%, H = 17%) is formed.

Next, after forming a semiconductor film on the base insulating film 11, etching is performed to form a semiconductor layer 20,
Get 21 Here, the semiconductor layer 20 is to form an n-channel TFT, and the semiconductor layer 21 is to form a p-channel TFT. The semiconductor film is formed by depositing a semiconductor film having an amorphous structure by a known means (a sputtering method, an LPCVD method, a plasma CVD method or the like), and then a known crystallization treatment (a laser crystallization method, a thermal crystallization method) Or a thermal crystallization method using a catalyst such as nickel, etc.) to form a crystalline semiconductor film. The thickness of this semiconductor film 12 is 2
It is formed at 5 to 200 nm (preferably 30 to 100 nm). Although there is no limitation on the material of the semiconductor film, it is preferable to use silicon or silicon germanium (SiGe) alloy or the like.
In this embodiment, laser light is irradiated to form a semiconductor film having a crystalline structure, and patterning is performed to form semiconductor layers 20 and 21.

Then, an insulating film 22 covering the semiconductor layer 12 is formed. The insulating film 22 is formed to have a thickness of 40 to 150 nm and a single-layer or stacked-layer structure of an insulating film containing silicon by plasma CVD or sputtering. The insulating film 13 is a gate insulating film. In this embodiment, a silicon oxynitride film (composition ratio Si = 32%, O = 59%) with a thickness of 110 nm by plasma CVD.
, N = 7%, H = 2%).

Subsequently, a sputtering method, plasma CVD method, or the like is used on the insulating film 22 to a film thickness of 250 to 600.
A conductive film 23 of nm is formed. Here, an example in which a single-layer structure is used as the conductive film 23 is shown, but a structure in which two or more layers of the conductive film 23 are stacked may be used.
Alternatively, the conductive film may be formed of an element selected from Ta, W, Ti, Mo, Al, Cu, Cr, and Nd, or an alloy material or a compound material containing the above element as a main component. Also,
A semiconductor film typified by a polycrystalline silicon film into which an impurity element such as phosphorus is introduced may be used. Alternatively, an AgPdCu alloy may be used. In the present embodiment, the film thickness is 400 nm by sputtering.
Form a Ta film. In addition, a film formed by sputtering often has compressive stress.

Next, the conductive film 23 is etched by patterning processing using a photolithography method to form a first conductive film 24 and a second conductive film 25. (Fig. 6 (
B))

Then, a first impurity element is introduced to form an impurity region 27 in the semiconductor film. The impurity element may be introduced by plasma doping, ion implantation, ion shower doping, or the like. In this embodiment, As is used as an impurity element imparting n-type.
Further, in the introduction of the first impurity element, the introduction amount in the introduction of the first impurity element is made larger than the amount of the impurity element introduced in the introduction of the second impurity element. By introducing the first impurity element, an impurity region 27 to function as an n-channel TFT is formed.
As is also introduced into the first conductive film 24 and the second conductive film 25, and the compressive stress 15 is increased.

Subsequently, a second impurity element is introduced to form an impurity region 28 in the semiconductor film. At this time, since the semiconductor layer 20 forming the n-channel TFT is covered with the mask 26 b made of resist, the impurity element is not introduced. In this embodiment, B is used as an impurity element imparting p-type. By introducing a second impurity element, a p-channel TFT
As a result, an impurity region 28 to function as B is formed, but B is also introduced into the second conductive film 25 and the compressive stress 15 of the second conductive film 25 is further increased.

Thus, the impurity region is formed, and more impurity element is introduced into the second conductive film 25 than the first conductive film 24.

Subsequently, heat treatment is performed to recover the crystallinity of the semiconductor film and activate the impurity element. Further, the internal stress in the first conductive film 24 and the second conductive film 25 is also changed by the heat treatment. However, since the amounts of impurity elements introduced into the first conductive film 24 and the second conductive film 25 are different, the internal stress after heat treatment is also different. Since the first conductive film 24 has a small amount of impurity element introduced, it is largely changed in the direction 16 of increase in tensile stress by heat treatment, and the internal stress in the first conductive film 24 becomes tensile stress. for that reason,
The stress to which the semiconductor film forming the n-channel TFT is subjected is a tensile stress. Also, the second
Since the conductive film 25 has a large amount of introduced impurity elements, the internal stress does not change so much by heat treatment, and the internal stress in the second conductive film 25 becomes compressive stress. Therefore, the stress to which the semiconductor film forming the n-channel TFT is subjected is compressive stress.

In this way, the internal stress of the conductive film is controlled to make the stress that the semiconductor film forming the n-channel TFT receives a tensile stress, and the stress that the semiconductor film forming the p-channel TFT receives a compressive stress. Can. Then, when a TFT is manufactured using such a semiconductor film, its electrical characteristics become good, and the operating characteristics of the semiconductor device can be significantly improved.

In this embodiment, the case where the present invention is applied to the wiring of a TFT will be described with reference to FIG.

A base insulating film is formed on a substrate, a semiconductor layer is formed on the base insulating film, an insulating film is formed to cover the semiconductor layer, and a conductive layer is formed on the semiconductor layer via the insulating film. After that, an impurity element is introduced into the semiconductor film using the conductive layer as a mask. Also, the method shown in the second embodiment may be followed.

Subsequently, an interlayer insulating film 29 made of an inorganic insulating film material or an organic insulating material is formed. In the present embodiment, the interlayer insulating film 29 has a single-layer structure, but may have a laminated structure of two or more layers.

Then, conductive films electrically connected to the respective impurity regions are formed. The conductive film may have a strong tensile stress. Therefore, an impurity element is introduced to change the internal stress of the conductive film in the direction of increasing the compressive stress. The internal stress can be controlled by such a method, and a conductive film having an internal stress of ± 1 GPa or less can be formed, and patterning is performed to form the wirings 31 to 33.
Prevent the wiring pattern from shifting when forming the

In addition, the internal stress of the conductive layer formed in this manner is ± 1 GPa or less, which makes it possible to reduce the stress exerted on the interlayer insulating film and the semiconductor film.
Then, when a TFT is manufactured using such a conductive layer, its electrical characteristics become good, and the operating characteristics of the semiconductor device can be significantly improved.

In this embodiment, the case where the present invention is applied to the gate electrode of a TFT having a structure different from that of the embodiment 2 will be described with reference to FIG.

First, the conductive film 35 is formed on the substrate 10. As the substrate 10, a glass substrate, a quartz substrate, a single crystal silicon substrate, a metal substrate, or a stainless steel substrate on which an insulating film is formed may be used. Alternatively, a plastic substrate having heat resistance that can withstand processing temperatures may be used.

The conductive film 35 may be formed by sputtering, plasma CVD, etc.
After the conductive film 20 of 00 nm is formed, patterning is performed by photolithography to form the conductive film 20. Here, an example in which a single-layer structure is used as the conductive film 35 is shown, but a structure in which two or more conductive films are stacked may be used. Moreover, as a conductive film, Ta, W, Ti, Mo,
It may be formed of an element selected from Al, Cu, Cr, Nd, or an alloy material or a compound material containing the above element as a main component.
Alternatively, a semiconductor film typified by a polycrystalline silicon film into which an impurity element such as phosphorus is introduced may be used. Alternatively, an AgPdCu alloy may be used. In the present embodiment, the film thickness is 40 by sputtering.
An Al-Ti film of 0 nm is formed.

Subsequently, an impurity element is introduced to increase the internal stress in the conductive film in the direction of increase in compressive stress.
Change to This is a process that is performed in advance to reduce the internal stress because the internal stress in the conductive film changes in the direction of the increase in the tensile stress due to the heat treatment in the subsequent step.

Then, an insulating film 36 covering the conductive film 35 is formed. The insulating film 36 is formed to have a thickness of 40 to 150 nm and a single-layer or stacked-layer structure of an insulating film containing silicon by plasma CVD or sputtering. The insulating film 36 is a gate insulating film. In this embodiment, a silicon oxynitride film (composition ratio Si = 32%, O = 59%, 110 nm thick) by plasma CVD.
It forms by N = 7%, H = 2%).

Next, the semiconductor film 37 is formed on the insulating film 36. The semiconductor film 37 is formed by depositing a semiconductor film having an amorphous structure by a known means (a sputtering method, an LPCVD method, a plasma CVD method or the like), and then a known crystallization treatment (a laser crystallization method, a thermal crystallization) A crystalline semiconductor film is formed by a method or a thermal crystallization method using a catalyst such as nickel. The thickness of the semiconductor film 37 is 25 to 200 nm (preferably 30 to 100 nm). Although there is no limitation on the material of the semiconductor film, it is preferable to use silicon or silicon germanium (SiGe) alloy or the like. In this embodiment, after forming a 55 nm amorphous silicon film by plasma CVD,
A solution containing nickel is retained on the amorphous silicon film. The amorphous silicon film is dehydrogenated (50
After 0 ° C., 1 hour), thermal crystallization (550 ° C., 4 hours) is performed. By the heat treatment, the semiconductor film 37 becomes a semiconductor film having a crystal structure. Further, since the impurity element is introduced in advance, the amount of change in internal stress in the conductive film 35 can be small.

The internal stress of the conductive film formed in this manner becomes a desired internal stress, and the stress exerted on the semiconductor film can be reduced. Then, when a TFT is manufactured using such a conductive film, its electrical characteristics become good, and the operating characteristics of the semiconductor device can be significantly improved.

In the present embodiment, the present invention is applied to an insulated gate field effect transistor (MOSFET or IG
An example of the case where a CMOS circuit is configured by applying to FET) will be described with reference to FIGS.

First, a single crystal silicon substrate 401 is prepared, and an impurity element is implanted to form a P-type well 402,
An N-type well 403 is formed. The single crystal silicon substrate may be P-type or N-type. Such a configuration is a so-called twin-tab structure, and is formed at a well concentration of 1 × 10 ¹⁸ / cm ³ or less (typically 1 × 10 ^{16 to} 5 × 10 ¹⁷ / cm ³ ).

Next, after selective oxidation is performed by a known LOCOS method or the like to form field oxide film 404, a 30 nm thick oxide film (later gate insulating film) 4 is formed on the silicon surface by a thermal oxidation process
Form 05. (FIG. 21 (A))

Next, the first gate electrode 406 and the second gate electrode 407 are formed. In the present embodiment, a silicon film having conductivity is used as a material for forming the gate electrode.
An element selected from W, Ti, Mo, Al, Cu, Cr, Nd, or an alloy material or a compound material containing the above element as a main component can be used.

After the formation of the first gate electrode 406 and the second gate electrode 407, a region (right side in the drawing) to be a p-channel MOSFET is covered with a resist mask 408, and n-type relative to the single crystal silicon substrate 401. Introduce the impurity element to be added. (FIG. 21 (B)) The method of introducing the impurity element is any of laser doping, plasma doping, ion implantation and ion shower doping, and the concentration is 5 × 10 ¹⁸ to 1 × 10.
Introduce so that it becomes ¹⁹ / cm ³ . In this embodiment, As as an impurity element imparting n-type, As
Use Part of the impurity regions 410 and 411 formed in this manner (ends in contact with the channel formation region) later function as LDD regions of the n-channel MOSFET.

Next, a region to be an n-channel MOSFET is covered with a resist mask 412.
Then, an impurity element imparting p-type conductivity to the single crystal silicon substrate 401 is introduced. (FIG. 21C) In the present embodiment, B (boron) is used as an impurity element imparting n-type.
In this manner, impurity regions 414 and 415 which later function as LDD regions of the p-channel MOSFET are formed.

After the state shown in FIG. 21C is obtained, a silicon oxide film (not shown) is deposited and etched back to form sidewalls 416 and 417. (FIG. 22 (A)
)

Next, a region to be a p-channel MOSFET is covered again with a resist mask 418, and an impurity element imparting n-type conductivity is introduced at a concentration of 1 × 10 ²⁰ / cm ³ . Thus source region 41
9, the drain region 420 is formed, and the LDD region 421 is formed under the sidewall 416. (FIG. 22 (B))

Similarly, a region to be an n-channel MOSFET is covered with a resist mask 422, and an impurity element imparting p-type conductivity is introduced at a concentration of 1 × 10 ²⁰ / cm ³ . Thus, drain region 42
3. The source region 424 is formed, and the LDD region 425 is formed under the sidewall 417. (FIG. 22C) Furthermore, while covered with the resist mask 422, one or more elements selected from rare gas elements are introduced. Thus, the second gate electrode 40
The impurity element is introduced in a larger amount than the first gate electrode 406 in FIG. Thereby, the second
The compressive stress of the gate electrode 407 of the p-channel type M is stronger than that of the first gate electrode 406.
The compressive stress experienced by the channel formation region in the OSFET is also stronger than the stress experienced by the channel formation region in the n-channel MOSFET.

After the state of FIG. 22C is obtained, the first heat treatment is performed to activate the introduced impurity element.

Subsequently, a titanium film is formed and second heat treatment is performed to form a titanium silicide layer 426 on the surfaces of the source region, the drain region, and the gate electrode. Of course, metal silicides using other metal films can also be formed. After forming the silicide layer, the titanium film is removed.

The first gate electrode 406 and the second gate electrode are formed by the first heat treatment and the second heat treatment.
The internal stress of the gate electrode 407 also changes, but the second gate electrode 407 has a larger amount of impurity element introduced than the first gate electrode 406, so the change in internal stress is small. Therefore, the second
Compressive stress of the gate electrode 407 is stronger than that of the first gate electrode 406, and
The compressive stress experienced by the channel formation region in the FET is also stronger than the stress experienced by the channel formation region in the n-channel MOSFET.

Next, an interlayer insulating film 427 is formed, contact holes are opened, and source electrodes 428 and 42 are formed.
9, form a drain electrode 430. Of course, it is also effective to carry out hydrogenation after electrode formation.

By the steps as described above, a CMOS circuit as shown in FIG. 23 can be obtained. The electrical characteristics of the CMOS circuit in which the internal stress of the gate electrode is controlled can be improved, and the operating characteristics of the semiconductor device can be significantly improved.

In this embodiment, a method for manufacturing an active matrix substrate will be described with reference to FIGS. In this specification, a substrate on which a CMOS circuit, a driver circuit, and a pixel portion having a pixel TFT and a storage capacitor are formed on the same substrate is referred to as an active matrix substrate for convenience.

First, in this embodiment, a substrate 501 made of glass such as barium borosilicate glass represented by Corning's # 7059 glass or # 1737 glass, or aluminoborosilicate glass is used. Note that as the substrate 501, a quartz substrate, a single crystal silicon substrate, a metal substrate, or a stainless steel substrate on which an insulating film is formed may be used. Alternatively, a plastic substrate having heat resistance that can withstand the processing temperature of this embodiment may be used. In this embodiment, a synthetic quartz glass substrate is used.

Next, a lower light shielding film is formed on the quartz substrate 501. First, a film thickness of 10 to 150 nm (preferably 50 to 10) comprising an insulating film such as a silicon oxide film, a silicon nitride film or a silicon oxynitride film
An underlayer of 0 nm) is formed. And, Ta, W, Cr, which can withstand the processing temperature of this embodiment
The lower light shielding film is formed with a film thickness of about 300 nm by a conductive material such as Mo and a laminated structure thereof. The lower light shielding film also has a function as a gate wiring. In this embodiment, a crystalline silicon film having a thickness of 75 nm is formed, and then WSix (x = 2.0 to 2.8) having a thickness of 150 nm is formed, and then unnecessary portions are etched to form a lower light shielding film. Form 503. In the present embodiment,
Although a single-layer structure is used as the lower light shielding film 503, a structure in which two or more insulating films are stacked may be used.

Then, a base film 504 having a thickness of 10 to 650 nm (preferably 50 to 600 nm) made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed on the substrate 501 and the lower light shielding film 503. Although a single-layer structure is used as the base film 504 in this embodiment, a structure in which two or more insulating films are stacked may be used. In this embodiment, the base film 504 is formed by plasma CVD using SiH ₄ , NH ₃ , and N ₂ O as reaction gases.
80 nm silicon oxynitride film 504 (composition ratio Si = 32%, O = 27%, N = 24%, H =
17%) at 350 ° C.

Next, a semiconductor film 505 is formed over the base film 504. The semiconductor film 505 is formed to have a thickness of 25 to 80 nm (preferably 30 to 60 nm) by a known method (a sputtering method, an LPCVD method, a plasma CVD method, or the like). Although there is no limitation on the material of the semiconductor film, it is preferable to use silicon or silicon germanium (SiGe) alloy or the like.

Then, a thermal crystallization method using a catalyst such as nickel is performed to crystallize the semiconductor film. In addition to the thermal crystallization method using a catalyst such as nickel, known crystallization treatments (laser crystallization method, thermal crystallization method, etc.) may be performed in combination. In this example, a nickel acetate solution (10 ppm by weight conversion, 5 ml volume) is applied on the entire surface by spin coating to form the metal-containing layer 405, and is exposed to a nitrogen atmosphere at a temperature of 600 degrees for 12 hours.

When the laser crystallization method is also applied, a pulse oscillation type or continuous emission type excimer laser, YAG laser, YVO ₄ laser, or the like can be used. When these lasers are used, it is preferable to use a method in which a laser beam emitted from a laser oscillator is linearly condensed by an optical system to irradiate the semiconductor film. The conditions for crystallization are appropriately selected by the practitioner. When using an excimer laser, the pulse oscillation frequency is 300 Hz, and the laser energy density is 100 to 800 mJ / cm ² (typically 200 to 700 mJ / cm ^2). And). When a YAG laser is used, it is preferable to set the pulse oscillation frequency to 1 to 300 Hz by using the second harmonic and to set the laser energy density to 300 to 1000 mJ / cm ² (typically 350 to 800 mJ / cm ² ). Then, a laser beam condensed linearly in a width of 100 to 1000 μm, for example 400 μm, is irradiated over the entire surface of the substrate, and the overlapping ratio of the linear laser beam at this time is 50 to 98%. It is also good.

Subsequently, gettering is performed to remove or reduce a metal element used to promote crystallization from the semiconductor layer to be an active region. Japanese Patent Laid-Open No. 10-27 describes gettering.
The method disclosed in Japanese Patent Application Publication No. 0363 may be applied. In this embodiment, a silicon oxide film having a thickness of 50 nm is formed as a mask, and patterning is performed to form a silicon oxide film 50 having a desired shape.
6a to 506d are obtained. Then, an element belonging to group 15 selectively to the semiconductor film (typically, P
By introducing (phosphorus) and performing heat treatment, the metal element can be removed from the semiconductor layer or reduced to an extent not affecting the semiconductor characteristics. The TFT having the active region manufactured in this manner has a low off current value and good crystallinity, so high field effect mobility can be obtained.
Good properties can be achieved.

Then, the crystalline semiconductor film is etched to form semiconductor layers 507 a to 510 a. (Fig. 9 (D))

Next, heat treatment is preferably performed to thermally oxidize the upper portion of the semiconductor layer by removing the masks 506 a to 506 d and newly forming the insulating film 511 to improve the crystallinity of the semiconductor film. In this embodiment, after a silicon oxide film of 20 nm is formed by a low pressure CVD apparatus, heat treatment is performed by a furnace annealing furnace. By this treatment, upper portions of the semiconductor layers 507 a to 510 a are oxidized. Then, when the oxidized portions of the silicon oxide film and the semiconductor layer are etched, semiconductor layers 507 b to 510 b with improved crystallinity can be obtained.

After forming the semiconductor layers 507 b to 510 b, a slight amount of impurity element (boron or phosphorus) may be introduced to control the threshold value of the TFT.

Next, a first gate insulating film 511 which covers the semiconductor layers 507 b to 510 b is formed. The first gate insulating film 511 is formed to have a thickness of 20 to 15 by plasma CVD or sputtering.
It is formed of an insulating film containing silicon as 0 nm. In this embodiment, the plasma CVD method 35
Silicon oxynitride film with a thickness of nm (composition ratio Si = 32%, O = 59%, N = 7%, H = 2%)
Formed. Of course, the gate insulating film is not limited to the silicon oxynitride film, and another insulating film containing silicon may be used.

When a silicon oxide film is used, TEOS (Tetraethyl Ortho) is used by plasma CVD.
Silicate) and O ₂ are mixed, reaction pressure is 40 Pa, substrate temperature is 300 to 400 ° C., and high frequency (13.56 MHz) power density can be formed by discharging at 0.5 to 0.8 W / cm ² . The silicon oxide film thus produced can obtain good characteristics as a gate insulating film by thermal annealing at 400 to 500 ° C. thereafter.

Then, the gate insulating film is partially etched to expose the semiconductor layer 510a which is one of the electrodes of the storage capacitor, and an impurity element is introduced into the semiconductor layer 510a. (Figure 10 (B
)) At this time, the resist 513 is formed in the other region, and the impurity element is not introduced. In this embodiment, P (phosphorus) is used as the impurity element, and the impurity element is introduced at an acceleration voltage of 10 keV and a dose of 5 × 10 ¹⁴ / cm ² .

Subsequently, a second gate insulating film 512 is formed. The second gate insulating film 512 is formed of an insulating film containing silicon with a thickness of 20 to 150 nm by plasma CVD or sputtering. In this embodiment, a silicon oxynitride film (composition ratio Si = 32%, O = 59%, N = 7%, H = 2%) having a thickness of 50 nm by plasma CVD.
Formed. Of course, the gate insulating film is not limited to the silicon oxynitride film, and another insulating film containing silicon may be used.

Then, after forming a contact to be connected to the lower light shielding film, the first film having a thickness of 20 to 100 nm is formed.
And a second conductive film 516 a with a thickness of 100 to 400 nm.
In this embodiment, the first conductive film 515 made of a TaN film having a film thickness of 30 nm and the film thickness of 370 nm
A second conductive film 516a made of a W film is laminated. The TaN film is formed by sputtering,
Sputtering was performed using a Ta target in an atmosphere containing nitrogen. Further, the W film is formed by a sputtering method using a W target. In addition, it can also be formed by thermal CVD using tungsten hexafluoride (WF ₆ ). In any case, in order to use as a gate electrode, it is necessary to reduce the resistance, and it is desirable that the resistivity of the W film be 20 μΩcm or less.

Although the first conductive film 515 is TaN and the second conductive film 516a is W in this embodiment, the present invention is not particularly limited, and any of Ta, W, Ti, Mo, Al, Cu, Cr, Nd is used. It may be formed of an element selected from or an alloy material or compound material containing the above element as a main component. Alternatively, a semiconductor film typified by a crystalline silicon film into which an impurity element such as phosphorus is introduced may be used. Alternatively, an AgPdCu alloy may be used. In addition, the first conductive film is made of tantalum (Ta
And the second conductive film is a W film, and the first conductive film is titanium nitride (Ti
N) combination of a second conductive film as a W film, and a first conductive film made of tantalum nitride (N)
Alternatively, a combination of a TaN film and a second conductive film as an Al film, a first conductive film of a tantalum nitride (TaN) film, and a second conductive film as a Cu film may be used.

Here, in order to make the internal stress in the second conductive film 516 a desired, a third impurity element is introduced. The impurity element may be introduced by plasma doping, ion implantation, or ion shower doping. Thus, the second conductive film 516b having a desired internal stress can be formed, which changes in the direction of increase in compressive stress. (Fig. 10 (
D) In the present embodiment, the accelerating voltage is 70 keV, and Ar is used to introduce an impurity element.

Next, a mask (not shown) made of a resist is formed by photolithography.
An etching process is performed to form an electrode and a wiring. In this embodiment, an ICP (Inductively Coupled Plasma) etching method is used as an etching condition.
Using CF ₄ , Cl ₂ and O _{2 as} etching gases, the gas flow ratio of each is 25/25 /
At 10 (sccm), 500 W RF (13.56 MHz) power was applied to the coil-type electrode at a pressure of 1 Pa to generate plasma for etching. 150 on the substrate side (sample stage)
Apply RF power (13.56 MHz) of W and apply a substantially negative self bias voltage.

Then, a fourth impurity element is introduced to introduce an impurity element imparting n-type conductivity to the semiconductor layer. (FIG. 11A) The conditions for introducing the impurity element are 1 × 10 ^{13 to} 5 × 10 ¹⁴ / cm ^2.
The acceleration voltage is 30 to 80 keV. In the present embodiment, the dose amount is 1.5 × 10 ¹³
/ Cm ² and then, the acceleration voltage is 60 keV. As an impurity element imparting n-type, an element belonging to group 15 is used, typically phosphorus (P) or arsenic (As).
Use). In this case, the conductive layers 517 to 521 serve as masks for the impurity element imparting n-type conductivity, and low concentration impurity regions 523 to 524 are formed in a self-aligned manner. An impurity element imparting n-type conductivity is added to the low concentration impurity regions 523 to 524 in a concentration range of 1 × 10 ¹⁸ to 1 × 10 ²⁰ / cm ³ . Here, a mask 522 made of resist is formed in the semiconductor layer forming the p-channel TFT, and an impurity element imparting n-type is not introduced.

Next, the mask made of resist is removed, a new mask is formed, and as shown in FIG. 11B, the fifth impurity element is introduced. The conditions for introducing the impurity element are a dose of 1 × 10 ¹³ to 1 × 10 ¹⁵ / cm ² and an acceleration voltage of 30 to 120 keV. At this time, a mask 525b is formed in order to prevent the introduction of an impurity element imparting n-type to the semiconductor layer forming the p-channel TFT, and high concentration is selectively formed in the semiconductor layer for forming the n-channel TFT. Masks 525a and 525c are formed to form impurity regions. In this example, the dose amount was 2 × 10 ¹⁵ / cm ² and the acceleration voltage was 50 keV. Thus, high concentration impurity regions 526 and 529 are formed.

Next, after removing the resist mask, a new resist mask 532 is formed.
Then, as shown in FIG. 11C, the sixth impurity element is introduced. By the introduction of the sixth impurity element, an impurity region 533 to which an impurity element imparting the opposite conductivity type to the one conductivity type is added is formed in the semiconductor layer to be the active layer of the p-channel TFT. The second conductive layer 518 is used as a mask for the impurity element, and an impurity element imparting p-type is added to form an impurity region in a self-aligned manner. In the present embodiment, the impurity region 533 is
Is formed by ion shower doping using diborane (B ₂ H ₆ ). The conditions for the ion shower doping method are a dose of 1 × 10 ¹³ to 1 × 10 ¹⁴ / cm ² and an acceleration voltage of 30 to 1
It does as 20 keV. At the introduction of the sixth impurity element, the semiconductor layer forming the n-channel TFT is covered with masks 532 a and 532 b made of resist.

Next, the mask made of resist is removed, a new mask is formed, and as shown in FIG. 12A, the seventh impurity element is introduced. The conditions for introducing the impurity element are a dose of 1 × 10 ¹³ to 1 × 10 ¹⁵ / cm ² and an acceleration voltage of 20 to 120 keV. At this time, masks 534a and 534c are formed in order to prevent the introduction of an impurity element imparting p-type conductivity to the semiconductor layer forming the n-channel TFT, and selective to the semiconductor layer for forming the p-channel TFT A mask 534 b is formed to form a high concentration impurity region. In this embodiment, the dose amount is 1 × 10 ¹⁵ / cm ² and the acceleration voltage is 40 keV. Thus, the high concentration impurity region 535 is formed.

Through the above steps, the high concentration impurity region and the low concentration impurity region are formed in each semiconductor layer.

Next, the mask 534 made of resist is removed to form a first interlayer insulating film 538. As the first interlayer insulating film 538, an insulating film containing silicon is formed to have a thickness of 100 to 200 nm by plasma CVD or sputtering.
In this embodiment, a silicon oxynitride film having a thickness of 150 nm is formed by plasma CVD. Of course, the first interlayer insulating film 538 is not limited to a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.

Next, as shown in FIG. 12B, heat treatment is performed to recover the crystallinity of the semiconductor layers and to activate the impurity elements added to the respective semiconductor layers. This heat treatment is performed by a thermal annealing method using a furnace annealing furnace. As the thermal annealing method, the temperature is 400 to 700 ° C. in a nitrogen atmosphere with an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less, typically 500 to 55.
The heat treatment may be performed at 0 ° C., and in this example, the activation treatment was performed by heat treatment at 550 ° C. for 4 hours. In addition to the thermal annealing method, a laser annealing method or a rapid thermal annealing method (RTA)
Law) can be applied.

Further, heat treatment may be performed before forming the first interlayer insulating film. However, if the wiring material used is weak to heat, heat treatment is performed after an interlayer insulating film (an insulating film mainly composed of silicon, for example, a silicon nitride film) is formed to protect the wiring etc. as in this embodiment. It is preferable to

Then, hydrogenation can be performed by heat treatment (heat treatment at 300 to 550 ° C. for 1 to 12 hours). This step is a step of terminating the dangling bond of the semiconductor layer by hydrogen contained in the first interlayer insulating film 461. Of course, the semiconductor layer can also be hydrogenated regardless of the presence of the first interlayer insulating film. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) or 300 to 450 in an atmosphere containing 3 to 100% hydrogen.
Heat treatment may be performed at 1 ° C for 1 to 12 hours.

Next, a second interlayer insulating film 539 made of an inorganic insulating film material or an organic insulating material is formed on the first interlayer insulating film 538. In this embodiment, a silicon nitride oxide film having a thickness of 1 μm is formed.

Then, in the driver circuit 555, wirings 54 electrically connected to the respective impurity regions are provided.
Form 0-542. In the pixel portion 556, source wirings 543 and 545 and a drain electrode 544 are formed. Note that these wires consist of a 50 nm Ti film and a 5
A laminated film of an alloy film of 00 nm (alloy film of Al and Ti) is patterned and formed.

The top view of the state produced so far in FIG. 13 is shown. In addition, the same code | symbol is used for the part corresponding to FIGS. 9-12. The dashed-dotted line AA 'in FIG. 12C corresponds to the cross-sectional view taken along the dashed line AA' in FIG. Further, the dashed-dotted line BB 'in FIG. 12C corresponds to the cross-sectional view taken along the dashed line BB' in FIG.

Next, a third interlayer insulating film 560 made of an inorganic insulating film material or an organic insulating material is formed on the second interlayer insulating film 539. In this embodiment, a silicon nitride oxide film having a thickness of 1.8 μm is formed.

A light shielding film 561 or 562 is formed on the third interlayer insulating film 539 by patterning a film having high light shielding properties such as Al, Ti, W, Cr, or a black resin into a desired shape. This light shielding film 5
61 and 562 are arranged in a mesh shape so as to shield light other than the opening of the pixel. Further, a fourth interlayer insulating film 563 is formed of an inorganic insulating material so as to cover the light shielding film 117.

Then, a contact hole communicating with the connection wiring 544 is formed, and a transparent conductive film such as ITO is used.
The pixel electrodes 564 and 565 are formed by forming a 00 nm thick film and patterning it to a desired shape.

As described above, an active matrix substrate is completed in which the driver circuit 555 having the n-channel TFT 551 and the p-channel TFT 552, the pixel TFT 553 and the pixel portion 556 having the storage capacitor 554 are formed on the same substrate.

The internal stress of the gate electrode thus formed becomes a desired internal stress, and the stress exerted on the semiconductor film can be reduced. Then, when a TFT is manufactured using such a gate electrode, its electrical characteristics become good, and the operating characteristics of the semiconductor device can be significantly improved.

Note that this embodiment can be freely combined with Embodiment 2 or Embodiment 3.
Of course, it is also possible to manufacture an active matrix substrate using the TFT formed in the fourth embodiment and the MOSFET formed in the fifth embodiment.

In this embodiment, steps of manufacturing a reflective liquid crystal display device from the active matrix substrate manufactured in Embodiment 6 will be described below. FIG. 15 is used for the explanation.

First, after obtaining the active matrix substrate in the state of FIG. 14B according to the sixth embodiment, an alignment film 567 is formed on at least the pixel electrodes 564 and 565 on the active matrix substrate and rubbing treatment is performed. In this embodiment, before forming the alignment film 567, the organic resin film such as an acrylic resin film is patterned to form a columnar spacer 572 for holding the distance between the substrates at a desired position. Also, spherical spacers may be dispersed over the entire surface of the substrate instead of the columnar spacers.

Next, an opposing substrate 569 is prepared. Next, a coloring layer 570 and a planarization film 573 are formed over the counter substrate 569.

Next, an opposing electrode 576 made of a transparent conductive film was formed at least in the pixel portion on the planarizing film 573, an alignment film 574 was formed on the entire surface of the opposing substrate, and rubbing was performed.

Then, the active matrix substrate in which the pixel portion and the driver circuit are formed and the counter substrate are attached to each other with a sealant 568. A filler is mixed in the sealing material 568, and the two substrates are bonded together at uniform intervals by the filler and the columnar spacer. after that,
A liquid crystal material 575 is injected between the two substrates and completely sealed by a sealant (not shown). A known liquid crystal material may be used for the liquid crystal material 575. Thus, the reflective liquid crystal display device shown in FIG. 15 is completed. Then, if necessary, the active matrix substrate or the counter substrate is divided into a desired shape. Furthermore, a polarizing plate (not shown) was attached only to the opposite substrate. And FPC was stuck using the well-known technique.

In the liquid crystal display device manufactured as described above, since the internal stress of the gate electrode is controlled to a desired one, it is also possible to reduce the stress exerted on the semiconductor film, and the operation characteristics of the liquid crystal display device Can also be significantly improved. Such a liquid crystal display device can be used as a display portion of various electronic devices.

Note that this embodiment can be freely combined with Embodiment 2, Embodiment 3, or Embodiment 6.

In this embodiment, an example in which a light emitting device is manufactured using the present invention will be described. In this specification, a light emitting device means a display panel in which a light emitting element formed on a substrate is sealed between the substrate and a cover material, and a display module in which an IC (Integrated Circuit) is mounted on the display panel. It is a generic term. Note that the light emitting element has a layer (light emitting layer) containing an organic compound capable of obtaining luminescence (Electro Luminescence) generated by applying an electric field, an anode layer, and a cathode layer. Further, for luminescence in organic compounds, light emission (fluorescent light) when returning from the singlet excited state to the ground state and light emission (phosphorescence) when returning from the triplet excited state to the ground state
And include one or both of these emissions.

FIG. 16 is a cross-sectional view of the light emitting device of this embodiment. In FIG. 16, a driver circuit provided over a substrate 700 is formed using the CMOS circuit of FIG. Therefore, although the description of the structure may be referred to the description of the n-channel TFT 551 and the p-channel TFT 552, the internal stress is controlled by introducing Ar to the gate electrodes of the n-channel TFT 551 and the p-channel TFT 552. And stress applied to the semiconductor film. Therefore, it is possible to improve the electrical characteristics of the TFT. Although a single gate structure is used in this embodiment, a double gate structure or a triple gate structure may be used.

The switching TFT 603 provided on the substrate 700 is the n-channel type T shown in FIG.
It is formed using FT551. Therefore, although the description of the structure may be referred to the description of the n-channel TFT 551, the internal stress is controlled by introducing Ar to the gate electrode of the n-channel TFT 551 to reduce the stress applied to the semiconductor film. is there. Therefore, it is possible to improve the electrical characteristics of the TFT.

In this embodiment, a double gate structure in which two channel formation regions are formed is employed, but a single gate structure in which one channel formation region is formed or a triple gate structure in which three channel formation regions are formed may be employed.

The wirings 701 and 703 function as a source wiring of the CMOS circuit, and 702 functions as a drain wiring. The wire 704 functions as a wire electrically connecting a source wire (not shown) to the source region of the switching TFT, and the wire 705 electrically connects a drain wire (not shown) to the drain region of the switching TFT. Act as a wire to connect to

Note that the current control TFT 604 is formed using the p-channel TFT 552 of FIG. Therefore, for the description of the structure, the description of the p-channel TFT 552 may be referred to.
The internal stress is controlled by introducing Ar to the gate electrode of the channel TFT 552,
Stress applied to the semiconductor film is reduced. Therefore, it is possible to improve the electrical characteristics of the TFT. Although a single gate structure is used in this embodiment, a double gate structure or a triple gate structure may be used.

Further, a wiring 706 is a source wiring (corresponding to a current supply line) of the current control TFT, and is an electrode electrically connected to the pixel electrode 711.

Reference numeral 711 denotes a pixel electrode (anode of a light emitting element) formed of a transparent conductive film. As the transparent conductive film, a compound of indium oxide and tin oxide, a compound of indium oxide and zinc oxide, zinc oxide, tin oxide or indium oxide can be used. Moreover, you may use what added the gallium to the said transparent conductive film. The pixel electrode 711 is formed on the flat interlayer insulating film 710 before forming the wiring. In the present embodiment, the flattening film 7 made of resin is used.
It is very important to flatten the step due to the TFT by using. Since the light emitting layer to be formed later is very thin, the presence of the step may cause light emission failure. Therefore, it is desirable to planarize the light emitting layer before forming the pixel electrode so that the light emitting layer can be formed as flat as possible.

After forming the wirings 701 to 707, a bank 712 is formed as shown in FIG.
The bank 712 may be formed by patterning an insulating film or an organic resin film containing silicon of 100 to 400 nm.

Note that, since the bank 712 is an insulating film, attention must be paid to electrostatic breakdown of elements during film formation. In this embodiment, carbon particles or metal particles are added to the insulating film which is the material of the bank 712 to lower the resistivity, thereby suppressing the generation of static electricity. At this time, the resistivity is 1 × 10 ⁶ to 1 × 1.
The addition amount of the carbon particles or the metal particles may be adjusted to be 0 ¹² Ωm (preferably 1 × 10 ⁸ to 1 × 10 ¹⁰ Ωm).

A light emitting layer 713 is formed on the pixel electrode 711. Although only one pixel is illustrated in FIG. 16, in this embodiment, light emitting layers corresponding to the respective colors of R (red), G (green), and B (blue) are separately formed. In the present embodiment, a low molecular weight organic light emitting material is formed by vapor deposition.
Specifically, a 20 nm thick copper phthalocyanine (CuPc) film is provided as a hole injection layer, and a 70 nm thick tris-8-quinolinolato aluminum complex (Alq ₃ ) is formed thereon as a light emitting layer.
) A laminated structure provided with a film.
Quinacridone Alq _3, it is possible to control the luminescent color by adding a fluorescent dye such as perylene or DCM1.

However, the above examples are examples of the organic light emitting material that can be used as the light emitting layer, and it is not necessary to limit to this at all. A light emitting layer, a charge transporting layer, or a charge injecting layer may be freely combined to form a light emitting layer (a layer for emitting light and moving a carrier therefor). For example, although a low molecular weight organic light emitting material is used as a light emitting layer in this embodiment, a high molecular weight organic light emitting material may be used. In addition, it is also possible to use an inorganic material such as silicon carbide as the charge transport layer or the charge injection layer.
Known materials can be used as these organic light emitting materials and inorganic materials.

Next, on the light emitting layer 713, a cathode 714 formed of a conductive film is provided. In the case of this embodiment, an alloy film of aluminum and lithium is used as the conductive film. Of course, known MgAg films (
An alloy film of magnesium and silver may be used. As a cathode material, a conductive film made of an element belonging to group 1 or 2 of the periodic table or a conductive film to which such an element is added may be used.

When the cathode 714 is formed, the light emitting element 715 is completed. Note that the light-emitting element 715 mentioned here indicates a diode formed of the pixel electrode (anode) 711, the light-emitting layer 713, and the cathode 714.

It is effective to provide the passivation film 716 so as to completely cover the light emitting element 715. The passivation film 716 is formed of an insulating film including a carbon film, a silicon nitride film, or a silicon nitride oxide film, and the insulating film is used as a single layer or a stacked layer.

At this time, it is preferable to use a film with good coverage as a passivation film, and it is effective to use a carbon film, in particular, a DLC (diamond like carbon) film. Since the DLC film can be formed in a temperature range from room temperature to 100 ° C. or less, the DLC film can be easily formed above the light-emitting layer 713 having low heat resistance. In addition, the DLC film has a high blocking effect on oxygen, and can suppress the oxidation of the light emitting layer 713. Therefore, it is possible to prevent the problem that the light emitting layer 713 is oxidized during the subsequent sealing process.

Further, a sealing material 717 is provided over the passivation film 716 and a cover material 718 is attached. An ultraviolet curing resin may be used as the sealing material 717, and it is effective to provide a substance having a hygroscopic effect or a substance having an antioxidant effect inside. In the present embodiment, the cover material 718 is formed by forming a carbon film (preferably, a diamond-like carbon film) on both surfaces of a glass substrate, a quartz substrate, and a plastic substrate (including a plastic film).

Thus, a light emitting device having a structure as shown in FIG. 16 is completed. After forming the bank 712, it is effective to continuously process the steps up to the formation of the passivation film 716 using a multi-chamber (or in-line) film forming apparatus without releasing the air. . Further, it is possible to process continuously up to the step of further developing and bonding the cover material 718 without releasing the air.

Further, although only the configuration of the pixel portion and the drive circuit is shown in this embodiment, according to the manufacturing process of this embodiment, other logic circuits such as a signal dividing circuit, a D / A converter, an operational amplifier, and a γ correction circuit May be formed on the same insulator, and may further form a memory or a microprocessor.

Furthermore, the light emitting device of this example after the sealing (or sealing) step for protecting the light emitting element is described with reference to FIG. In addition, the code | symbol used in FIG. 16 is quoted as needed.

FIG. 17A is a top view showing a state in which the light emitting element is sealed up, and FIG.
It is sectional drawing which cut | disconnected 7 (A) by CC '. Reference numeral 801 indicated by a dotted line is a source side drive circuit, 806 is a pixel portion, and 807 is a gate side drive circuit. In addition, 901 is a cover material, 902
A first sealing member 903 is a second sealing member 903, and a sealing member 907 is provided on the inside surrounded by the first sealing member 902.

Note that reference numeral 904 denotes a wiring for transmitting signals input to the source side drive circuit 801 and the gate side drive circuit 807, and receives video signals and clock signals from an FPC (flexible printed circuit) 905 serving as an external input terminal. Although only the FPC is illustrated here, a printed wiring board (PWB) may be attached to the FPC. The light emitting device in this specification includes not only the light emitting device main body but also the FPC or P
It also includes the state in which the WB is attached.

Next, the cross-sectional structure will be described with reference to FIG. A pixel portion 806 and a gate driver circuit 807 are formed above the substrate 700, and the pixel portion 806 is a current control TFT 60.
4 and a plurality of pixels including a pixel electrode 711 electrically connected to the drain thereof. In addition, the gate driver circuit 807 includes an n-channel TFT 601 and a p-channel TFT 6
It is formed by using a CMOS circuit (see FIG. 16) in combination with “02”.

The pixel electrode 711 functions as an anode of the light emitting element. In addition, banks 712 are formed at both ends of the pixel electrode 711, and the light emitting layer 713 and the cathode 714 of the light emitting element are formed on the pixel electrode 711.
Is formed.

The cathode 714 also functions as a wiring common to all pixels, and is connected to the FPC 9 through the connection wiring 904.
It is electrically connected to 05. Further, elements included in the pixel portion 806 and the gate driver circuit 807 are all covered with the cathode 714 and the passivation film 567.

In addition, the cover material 901 is attached by the first sealing material 902. Note that a spacer made of a resin film may be provided in order to secure a distance between the cover member 901 and the light emitting element.
A sealing material 907 is filled inside the first sealing material 902. As the first sealing material 902 and the sealing material 907, an epoxy resin is preferably used. Further, it is desirable that the first sealing material 902 be a material which transmits as little moisture and oxygen as possible. further,
A substance having a hygroscopic effect or a substance having an antioxidant effect may be contained in the inside of the sealant 907.

A sealing material 907 provided to cover the light emitting element also functions as an adhesive for bonding the cover material 901. Further, in the present embodiment, FRP (Fiberglass-Reinforced Plastics), PVF (polyvinyl fluoride), Mylar, polyester or acrylic can be used as the material of the plastic substrate 901a constituting the cover material 901.

Further, after the cover material 901 is attached using the sealing material 907, the second sealing material 903 is provided so as to cover the side surface (exposed surface) of the sealing material 907. The second seal member 903 is a first seal member 90.
The same material as 2 can be used.

By sealing the light emitting element in the sealing material 907 with the above structure, the light emitting element can be completely shut off from the outside, and a substance that promotes deterioration due to oxidation of the light emitting layer such as water or oxygen penetrates from the outside. You can prevent it. Therefore, a highly reliable light emitting device can be obtained.

In the light emitting device manufactured as described above, since the internal stress of the gate electrode is controlled to a desired one, it is also possible to reduce the stress exerted on the semiconductor film, and the operating characteristics of the light emitting device are also greatly reduced. Improve. Such a light emitting device can be used as a display portion of various electronic devices.

Note that this embodiment can be freely combined with Embodiment 2, Embodiment 3, or Embodiment 6.

The CMOS circuit and the pixel portion formed by applying the present invention can be used for various electro-optical devices (active matrix liquid crystal display device, active matrix EC display device, active matrix light emitting device). That is, the present invention can be applied to all electronic devices in which the electro-optical devices are incorporated in the display unit.

As such electronic devices, video cameras, digital cameras, projectors, head mounted displays (goggle type displays), car navigation, car stereos, personal computers, personal digital assistants (mobile computers, mobile phones, electronic books, etc.), etc. It can be mentioned. Examples of these are shown in FIGS. 18, 19 and 20.

FIG. 18A shows a personal computer, which is a main body 3001, an image input unit 3002,
The display unit 3003 includes a keyboard 3004 and the like. The present invention can be applied to the display portion 3003.

FIG. 18B shows a video camera, which has a main body 3101, a display portion 3102, an audio input portion 31.
03, an operation switch 3104, a battery 3105, an image receiving unit 3106 and the like. The present invention can be applied to the display portion 3102.

FIG. 18C shows a mobile computer (mobile computer), which is a main body 3201.
, A camera unit 3202, an image receiving unit 3203, an operation switch 3204, a display unit 3205, and the like. The present invention can be applied to the display portion 3205.

FIG. 18D shows a goggle type display, which includes a main body 3301, a display portion 3302, an arm portion 3303 and the like. The present invention can be applied to the display portion 3302.

FIG. 18E shows a player using a recording medium storing a program (hereinafter referred to as a recording medium), and a main body 3401, a display portion 3402, a speaker portion 3403 and a recording medium 3404.
, The operation switch 3405 and the like. Note that this player uses a DVD (Di
It is possible to perform music appreciation, movie appreciation, games and the Internet using a gtial Versatile Disc), a CD and the like. The present invention can be applied to the display portion 3402.

FIG. 18F shows a digital camera, which is a main body 3501, a display portion 3502, and an eyepiece portion 350.
3 includes an operation switch 3504 and an image receiving unit (not shown). The present invention can be applied to the display portion 3502.

FIG. 19A shows a front type projector, which has a projection device 3601 and a screen 36.
Includes 02 grade. The present invention can be applied to a liquid crystal display device 3808 which forms a part of the projection device 3601 and other drive circuits.

FIG. 19B shows a rear type projector, which includes a main body 3701, a projection device 3702, a mirror 3703, a screen 3704 and the like. The present invention can be applied to a liquid crystal display device 3808 which constitutes a part of the projection device 2702 and other drive circuits.

19C shows the projection device 3601 in FIGS. 19A and 19B.
It is a figure showing an example of the structure of 3702. The projection devices 3601 and 3702 have a light source optical system 3.
A mirror 801, mirrors 3802 and 3804 to 3806, a dichroic mirror 3803, a prism 3807, a liquid crystal display 3808, a retardation plate 3809, and a projection optical system 3810. The projection optical system 2810 is configured of an optical system including a projection lens. Although the present embodiment shows an example of the three-plate type, it is not particularly limited, and may be, for example, a single-plate type. In addition, a practitioner may appropriately use an optical lens, a film having a polarization function, or the like in an optical path indicated by an arrow in FIG.
You may provide optical systems, such as a film for adjusting a phase difference, and IR film.

FIG. 19D is a view showing an example of the structure of the light source optical system 3801 in FIG. 19C. In the present embodiment, the light source optical system 3801 comprises a reflector 3811 and a light source 38.
12, a lens array 3813, 3814, a polarization conversion element 3815, and a condenser lens 3816. The light source optical system shown in FIG. 19D is an example and is not particularly limited.
For example, the operator may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting retardation, or an IR film to the light source optical system.

However, the projector shown in FIG. 19 shows a case where a transmission type electro-optical device is used, and an application example of the reflection type electro-optical device and the light emitting device is not shown.

FIG. 20A shows a mobile phone, which has a main body 3901, an audio output portion 3902, and an audio input portion 39.
And 03, a display unit 3904, an operation switch 3905, an antenna 3906, and the like. The present invention can be applied to the display portion 3904.

FIG. 20B illustrates a portable book (electronic book), which includes a main body 4001, display portions 4002, and 400.
3 includes a storage medium 4004, an operation switch 4005, an antenna 4006 and the like. The present invention can be applied to the display portions 4002 and 4003.

FIG. 20C shows a display, which is a main body 4101, a support 4102, a display portion 4103.
Etc. The present invention can be applied to the display portion 4103. The display of the present invention is particularly advantageous when the screen is enlarged, and is advantageous for displays with a diagonal of 10 inches or more (particularly, 30 inches or more).

As described above, the scope of application of the present invention is so wide that it can be applied to electronic devices in various fields. In addition, the electronic device of this embodiment can be realized by using the configuration of any combination of Embodiments 2 to 7. Moreover, it is also possible to apply Example 8 to the electronic device in FIG. 18 and FIG.

Claims (3)

A crystalline semiconductor film,
A gate electrode on the crystalline semiconductor film;
A first insulating film on the gate electrode;
A drain electrode electrically connected to the impurity region of the crystalline semiconductor film through the first contact hole of the first insulating film;
A second insulating film on the drain electrode;
A wire having aluminum on the second insulating film;
A third insulating film on the wiring;
A pixel electrode electrically connected to the drain electrode through a second contact hole of the second insulating film and a third contact hole of the third insulating film;
The wiring has a light shielding property,
The wires are arranged in a mesh,
The first contact hole is offset from the second contact hole;
The semiconductor device according to claim 1, wherein the first contact hole is offset from the third contact hole. A crystalline semiconductor film,
A gate electrode on the crystalline semiconductor film;
A first insulating film on the gate electrode;
A drain electrode electrically connected to the impurity region of the crystalline semiconductor film through the first contact hole of the first insulating film;
A second insulating film on the drain electrode;
A wire having aluminum on the second insulating film;
A third insulating film on the wiring;
A pixel electrode electrically connected to the drain electrode through a second contact hole of the second insulating film and a third contact hole of the third insulating film;
The wiring has a light shielding property,
The wiring is arranged in a mesh shape so as to have an opening.
The pixel electrode, the first to third contact holes, the drain electrode, the gate electrode, and the channel formation region are provided at positions overlapping the opening.
The first contact hole is offset from the second contact hole;
The semiconductor device according to claim 1, wherein the first contact hole is offset from the third contact hole. A crystalline semiconductor film,
A gate electrode on the crystalline semiconductor film;
A first insulating film on the gate electrode;
A drain electrode electrically connected to the impurity region of the crystalline semiconductor film through the first contact hole of the first insulating film;
A second insulating film on the drain electrode;
A wire having aluminum on the second insulating film;
A third insulating film on the wiring;
A pixel electrode electrically connected to the drain electrode through a second contact hole of the second insulating film and a third contact hole of the third insulating film;
The wiring has a light shielding property,
The wiring is arranged in a mesh shape so as to overlap with the source line and to have an opening.
The pixel electrode, the first to third contact holes, the drain electrode, the gate electrode, and the channel formation region are provided at positions overlapping the opening.
The first contact hole is offset from the second contact hole;
The semiconductor device according to claim 1, wherein the first contact hole is offset from the third contact hole.

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