JP2017162130A - Hardware/software cooperative verification device and hardware/software cooperative verification method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow a HDL simulation to conduct hardware/software cooperative verification without requiring expensive logic emulators.SOLUTION: A hardware/software cooperative verification device comprises: an HDL simulator 10 that has a CPU model 15, and FPGA model 16 and HW model 17 simulating debag object hardware described in a test bench 14 of the HDL simulator 10, and displays a simulated result of the test bench 14 on a waveform viewer 101; a PC→source file retrieval function unit 19 that retrieves an address in which a value (value indicative of an execution address of the CPU model 15) of a programmable counter of an arbitrary part in waveform data 18 on the displayed simulation result coincides with an address in debag information 132, and outputs a source file name and line number corresponding to the coincided address; and a general-purpose text editor 20 that displays the corresponding source file at a part of the corresponding line number.SELECTED DRAWING: Figure 1

Description

  The present invention relates to co-simulation of digital circuits and software in a digital system (embedded system) in the embedded field.

  A digital system in the embedded field includes a hardware circuit including a CPU and software executed by the CPU. For shortening the development period and improving the quality of digital systems in the embedded field, hardware / software co-verification is effective, in which a hardware circuit including a CPU and software executed by the CPU are debugged before the actual machine is manufactured.

  There are two types of collaborative verification: collaborative simulation using an HDL (Hardware Description Language) simulator and collaborative emulation using a logic emulator.

  In the co-simulation using the HDL simulator, all the hardware circuits including the CPU are taken into the HDL simulator for debugging. On the other hand, co-emulation using a logic emulator takes a hardware circuit into the logic emulator and performs debugging.

  An example of cooperative emulation using a logic emulator is described in Patent Document 1.

  A technique for analyzing a character string of an assembler instruction word described in execution software used in the present invention is described in Patent Document 2.

Japanese Patent No. 5120103 JP 2014-78087 A

  The co-emulation using a logic emulator has the advantage that the operation is faster than the co-simulation using an HDL simulator, but has the disadvantage that the logic emulator is very expensive.

  Japanese Patent Application Laid-Open No. 2005-228561 is a cooperative emulation method in which all hardware circuits including a CPU are incorporated in a logic emulator. However, since the CPU uses the same RTL (Register Transfer Level) level as the actual machine, it contributes to a decrease in the operation speed.

  Hardware / software co-verification literally performs debugging by coordinating hardware and software operations. Each coordinated operation can be observed with the waveform viewer, but the execution source software source cannot be seen.

  As a solution to this problem, the above-described Patent Document 1 has a mechanism for specifying a software source execution location from the value of a programmable counter (PC) of a CPU model that executes software and displaying the software source at the specific location.

  However, in Patent Document 1, acquisition of the value of the programmable counter is limited at the time of an event such as a breakpoint, so that source display at an arbitrary location cannot be performed.

  Conversely, there is no mechanism for identifying and displaying an operation waveform in which hardware operation and software operation are coordinated from a software source.

  The present invention solves the above-described problems, and an object of the present invention is to provide an apparatus and method that can perform hardware / software co-verification using an HDL simulator without requiring an expensive logic emulator.

The hardware / software co-verification apparatus according to claim 1 for solving the above-described problem simulates a CPU model described as a simulation environment and equivalent to a real machine that simulates the operation of the CPU, and hardware to be debugged. Waveform display that displays the hardware model and simulation result waveform data of the observation signal group set in advance, and records the value of the programmable counter specified for the observation signal group and indicating the execution address of the CPU model during the entire simulation period An HDL simulator having a functional unit,
The CPU model executes the execution software generated from the software source group to simulate the software of the actual machine, the HDL simulator simulates the operation of the hardware to be debugged, and displays the simulation result on the waveform display function unit.
Acquires and acquires the debug information generated from the software source group, including the instruction address, the corresponding source file name and line number, and the value of the programmable counter at any location in the displayed simulation result waveform data. A first search function unit that searches for an address that matches the address of the programmable counter and the address in the debug information, and outputs the source file name and line number corresponding to the matched address;
And a first text editor function unit that is activated by the output of the first search function unit and displays the corresponding source file at the corresponding line number location.

  The hardware / software co-verification device according to claim 2 is characterized in that, in claim 1, the first search function unit and the first text editor function unit are provided in the HDL simulator. It is said.

The hardware / software co-verification device according to claim 3 is a simulation model described as a CPU model equivalent to a real machine that simulates the operation of a CPU, a hardware model that simulates hardware to be debugged, A waveform display function unit for displaying the simulation result waveform data of the observation signal group set in advance, and recording the value of the programmable counter designated for the observation signal group and indicating the execution address of the CPU model during the entire simulation period; An HDL simulator with
The CPU model executes the execution software generated from the software source group to simulate the software of the actual machine, the HDL simulator simulates the operation of the hardware to be debugged, and displays the simulation result on the waveform display function unit.
A second text editor function unit for displaying an arbitrary software source in the software source group and acquiring the displayed source file name and cursor line number;
Debug information generated from the software source group, which includes an instruction address and a corresponding source file name and line number, is acquired, and the source file name and line number in the acquired debug information and the second text A second search function unit that searches for a location where the source file name and the cursor line number acquired by the editor function unit match and outputs the address of the match location;
The waveform display function unit displays a simulation result waveform at a location where the value of the programmable counter corresponding to the address output by the second search function unit matches the value of the programmable counter recorded in the waveform display function unit. It is characterized by that.

  According to a fourth aspect of the present invention, there is provided the hardware / software co-verification device according to the third aspect, wherein the second search function unit and the second text editor function unit are provided in the HDL simulator. It is said.

  The hardware / software co-verification device according to claim 5 is the hardware / software co-verification device according to any one of claims 1 to 4, wherein the execution software is described by a character string of an assembler instruction word, and the CPU model is an assembler instruction A character string analysis function unit that analyzes a character string of a word is provided, and an assembler instruction analyzed by the character string analysis function unit is executed.

A hardware / software co-verification method according to claim 6 is a hardware / software co-verification method including an HDL simulator,
The HDL simulator includes a CPU model that is described as a simulation environment and that is equivalent to a real machine that simulates the operation of the CPU, a hardware model that simulates the hardware to be debugged, and simulation result waveform data of a preset observation signal group. A waveform display function unit for displaying and recording a value of a programmable counter indicating an execution address of a CPU model specified in the observation signal group during the entire simulation period,
The HDL simulator executes the execution software generated from the software source group using the CPU model to simulate the actual software, and simulates the operation of the hardware to be debugged;
The waveform display function unit displaying the simulation result;
The first search function unit of the hardware / software co-verification apparatus generates debug information including a combination of an instruction address, a corresponding source file name, and a line number generated from the software source group, and the displayed simulation result Acquires the value of the programmable counter at any location in the waveform data, searches for an address that matches the acquired programmable counter value and the address in the debug information, and outputs the source file name and line number corresponding to the matched address Steps,
The first text editor function unit of the hardware / software co-verification apparatus is activated by the output of the first search function unit, and includes the step of displaying the corresponding source file at the corresponding line number location. It is characterized by.

A hardware / software co-verification method according to claim 7 is a hardware / software co-verification method including an HDL simulator,
The HDL simulator includes a CPU model that is described as a simulation environment and that is equivalent to a real machine that simulates the operation of the CPU, a hardware model that simulates the hardware to be debugged, and simulation result waveform data of a preset observation signal group. A waveform display function unit for displaying and recording a value of a programmable counter indicating an execution address of a CPU model specified in the observation signal group during the entire simulation period,
The HDL simulator executes the execution software generated from the software source group using the CPU model to simulate the actual software, and simulates the operation of the hardware to be debugged;
A second text editor function unit of the hardware / software co-verification apparatus displaying an arbitrary software source in the software source group and acquiring the displayed source file name and cursor line number;
The second search function unit of the hardware / software co-verification apparatus acquires debug information generated from the software source group and including the instruction address, the corresponding source file name and the line number, and the acquired debug Searching for a location where the source file name and line number in the information match the source file name and cursor line number acquired by the second text editor function unit, and outputting the address of the matching location;
The waveform display function unit displays a simulation result waveform at a location where the programmable counter value corresponding to the address output by the second search function unit matches the programmable counter value recorded in the waveform display function unit. And a step.

  The hardware / software co-verification method according to claim 8 is the hardware / software co-verification method according to claim 6, wherein the execution software is described by a character string of an assembler instruction word, and the character string analysis function unit of the CPU model The method includes a step of analyzing a character string of an assembler instruction word, and a step of executing a assembler instruction analyzed by the CPU model.

  According to the above configuration, the CPU model and the hardware model as the simulation environment (test bench) are described in the HDL simulator, and the CPU model executes the execution software generated from the software source group and simulates the actual software. Since the HDL simulator is configured to simulate the operation of the hardware to be debugged, hardware / software co-verification can be performed with the HDL simulator without requiring an expensive logic emulator.

  Moreover, according to the structure of Claim 1, 2, 6, the location of the arbitrary simulation result waveform currently displayed on the waveform display function part by operation | movement of a 1st search function part and a 1st text editor function part. The software source corresponding to the value of the programmable counter can be displayed.

  According to the third, fourth, and seventh aspects, the simulation result waveform corresponding to an arbitrary location of the software source is specified and displayed by the operations of the second search function unit and the second text editor function unit. be able to.

  According to claim 2, it is possible to complete in the HDL simulator from designation of an arbitrary location in the simulation result waveform data displayed in the waveform display function to display of the source file.

  According to claim 4, it is possible to complete in the HDL simulator from the designation of the cursor line of an arbitrary software source being displayed to the display of the simulation result waveform.

  According to the fifth and eighth aspects of the present invention, since the CPU model execution software is executed by analyzing the character string of the assembler instruction word, the operation speed is improved.

(1) According to the first to eighth aspects of the invention, hardware / software co-verification can be performed with an HDL simulator without requiring an expensive logic emulator.
(2) According to the invention described in claims 1, 2, and 6, the software source corresponding to the value of the programmable counter at the location of the arbitrary simulation result waveform displayed in the waveform display function unit is displayed. Can do.
(3) Moreover, according to the invention of Claim 3, 4, 7, the simulation result waveform applicable to the arbitrary locations of a software source can be specified and displayed.
(4) According to the invention described in claim 2, from the designation of an arbitrary position in the simulation result waveform data displayed in the waveform display function to the display of the source file can be completed in the HDL simulator. .
(5) According to the invention described in claim 4, from the designation of the cursor line of an arbitrary software source being displayed to the display of the simulation result waveform can be completed within the HDL simulator.
(6) According to the inventions described in claims 5 and 8, the operation speed can be improved.

BRIEF DESCRIPTION OF THE DRAWINGS The block diagram which shows the whole Example 1 of this invention. Explanatory drawing which shows the debug information in the Example of this invention. Explanatory drawing which shows the principal part structure of Example 1 of this invention. Explanatory drawing which shows the modification of Example 1 of this invention. The block diagram which shows the whole Example 2 of this invention. Explanatory drawing which shows the principal part structure of Example 2 of this invention.

  The hardware / software co-verification of the present invention is based on a co-simulation using an HDL simulator. Examples of the present invention will be described below with reference to the drawings, but the present invention is not limited to the following examples.

  FIG. 1 shows the configuration of a hardware / software co-verification apparatus 200 according to the first embodiment of the present invention. A software source group 11 described in a C language or an assembler language (also referred to as an assembly language) is built with a compiler / linker 12 (a program for executing compiling and linking) to generate an object file 13. The object file 13 includes two elements, an execution code 131 (execution software) and debug information 132.

  In the HDL simulator 10, a CPU model 15, an FPGA (Field Programmable Gate Array) model 16 and an HW (hardware) model 17 that are hardware to be debugged are described as a test bench 14 (simulation environment for verification). ing.

  A bus model 25 connects the CPU model 15, the FPGA model 16, and the HW model 17.

  The CPU model 15 is a model equivalent to a real machine that simulates the operation of the CPU, and executes the execution code 131 (execution software) to simulate the software of the real machine. The HDL simulator uses the hardware to be debugged (FPGA model 16, HW). The operation of model 17) is simulated. The CPU model 15 employs a behavior model having a higher abstraction level than the RTL model.

  The FPGA model 16 is a model that simulates a rewritable logic element, and the HW model 17 is a model that simulates hardware.

  The CPU model 15 uses the technique described in Patent Document 2, for example, to improve the operation speed. That is, when the execution code 131 (execution software) of the object file 13 is generated, it is created not as an object code but as an assembler program (described by a character string of an assembler instruction word), and the CPU model 15 stores characters of the assembler instruction word. A character string analysis function unit for analyzing a string is provided, and an assembler instruction analyzed by the character string analysis function unit is executed.

  By configuring in this way, the character string analysis of the assembler instruction word can be realized on a small scale as compared with the conventional bit pattern analysis, so that the processing speed of the CPU model can be expected to be improved.

  The simulation result of the test bench 14 is an operation result in which the software operation of the CPU 15 and the operation of the hardware to be debugged (FPGA model 16 and HW model 17) cooperate, and the waveform viewer 101 (waveform display function unit) is obtained as simulation result waveform data 18. Is displayed.

  In the waveform viewer 101, a signal group to be observed is designated before the simulation. For the signal group to be observed, a programmable counter (PC) indicating the execution address of the CPU model 15 is always specified, and all programmable counters (values) within the simulation period are recorded.

  The value of the programmable counter at an arbitrary position in the simulation (the position where the cursor of the waveform viewer 101 is placed) is acquired from the simulation result waveform data 18 by the function of the HDL simulator 10 and is stored in the PC → source file search function unit 19 together with the debug information 132. Input to (first search function unit).

  As shown in FIG. 2, the debug information 132 is composed of a set of each instruction address for all instructions, and a corresponding source file name and line number.

  As shown in FIG. 3, the PC → source file search function unit 19 searches for an address that matches the value of the programmable counter (acquired PC) acquired from the simulation result waveform data 18 and the address in the debug information 132, and matches the address. Output the source file name and line number corresponding to.

  For example, in the example of FIG. 3, since the value “1010” of the programmable counter (acquired PC) acquired from the simulation result waveform data 18 matches the address “1010” in the debug information 132, the source file name of the matched address “D: ¥ WORK ¥ AAA.C” and line number “35” are output.

  When the general-purpose text editor 20 (first text editor function unit) is activated using the source file name and line number obtained in this way as activation options, the corresponding source file is displayed at the corresponding line number (line where the cursor is). can do.

  The hardware / software co-verification apparatus 200 configured as described above is configured by, for example, a computer, and hardware resources of a normal computer, for example, ROM, RAM, CPU, input device, output device, communication interface, hard disk, recording A medium and its driving device are provided.

  As a result of the cooperation between the hardware resource and the software resource (OS, application, etc.), the hardware / software co-verification apparatus 200 has a compiler / linker 12, an HDL simulator 10, a PC → source file as shown in FIG. A search function unit 19 and a general-purpose text editor 20 are installed.

  Next, the operation of the hardware / software co-verification apparatus 200 configured as described above will be described.

  The HDL simulator 10 simulates the test bench 14 and displays the simulation result on the built-in waveform viewer 101 as simulation result waveform data 18.

  A desired operation location is selected with the cursor, and the value (PC value) of the programmable counter is acquired using the function of acquiring the signal state at the cursor position provided in the waveform viewer 101.

  The simulation result waveform data 18 includes not only normal software execution but also interrupt operation and direct memory access (DMA) operation that are essential in an embedded system, and the software execution time of the CPU varies depending on the interrupt and direct memory access. Of course, the update timing of the programmable counter is also linked. Interrupt operations and direct memory access operations occur depending on the hardware state, and can be realized by including the CPU model 15, FPGA model 16, and HW model 17 in the test bench 14. Since the value of the programmable counter at any location such as when an interrupt occurs or during DMA operation can be acquired, it is effective for debugging both hardware and software of an embedded system.

  The acquired programmable counter value is input to the PC → source file search function unit 19 together with the debug information 132. For example, as shown in FIG. 3, the PC → source file search function unit 19 searches for an address that matches the acquired programmable counter value (PC value) and the address in the debug information 132, and the source file corresponding to the matched address. Print name and line number. When the general-purpose text editor 20 is activated using the obtained source file name and line number as activation options, the corresponding source file can be displayed at the corresponding line number (line where the cursor is).

  Furthermore, after displaying the software source corresponding to the value of the programmable counter at the desired location in the simulation result waveform data 18, the cursor is moved to the next change point of the programmable counter (PC) using the function provided in the waveform viewer 101. The new source file name and line number are acquired by the function for acquiring the signal state at the cursor position and the PC → file search function unit 19 and restarted as a startup option of the general-purpose text editor 20. The display position (cursor position) can be updated. That is, the cursor movement of the waveform viewer 101 and the display location of the software source can be linked.

  A series of operation examples is shown in FIG. In FIG. 4, when the cursor of the waveform viewer 101 is moved from the change point (1) (address 1000) of the programmable counter (PC) to the change point (2) (address 1002), the general-purpose text editor 20 is linked with it. The cursor moves from the source location at address 1000 to the source location at address 1002.

  Note that the PC → source file search function unit 19 and the general-purpose text editor 20 may be provided in the HDL simulator 10. As a good example, if the text editor function incorporated in the HDL simulator 10 is used for the general-purpose text editor 20, the process from the cursor position designation in the waveform viewer 101 to the software source display in the text editor can be completed in the HDL simulator 10. .

  As described above, an expensive logic emulator is not required, and the software source corresponding to the value of the programmable counter at an arbitrary position of the simulation result waveform data 18 can be displayed.

  In the second embodiment, hardware / software co-verification can be performed with an HDL simulator without requiring an expensive logic emulator. In contrast to the first embodiment, a simulation corresponding to an arbitrary location from a software source is possible. The result waveform can be specified and displayed.

  FIG. 5 shows the configuration of the hardware / software co-verification apparatus 300 according to the second embodiment, and the same parts as those in FIG.

  5 differs from FIG. 1 in that the file name and cursor of the display source file obtained from the general-purpose text editor 20 (second text editor function unit) instead of the PC → source file search function unit 19 in FIG. Using the line number and the file name and line number information in the debug information 132 as input, the file name and line number in the debug information 132 and the file name and cursor line number of the display source file obtained from the general-purpose text editor 20 A source file → PC search function unit 30 (second search function unit) that searches for a location that matches and outputs an address of the match location is provided.

  The address output from the source file → PC search function unit 30 corresponds to the cursor position of the source file displayed in the general-purpose text editor 20, and is the value of the programmable counter designated in the simulation result waveform data 18 of the waveform viewer 101. (Corresponding PC value).

  In the waveform viewer 101, the search function provided in itself is used to set the cursor of the waveform viewer 101 to the programmable counter value indicated by the value of the programmable counter in the simulation result waveform data 18 and the output address of the source file → PC search function unit 30. The simulation result waveform is displayed by moving to a location where the value of the value matches. Thereby, it is possible to identify and display a simulation result waveform corresponding to the arbitrary location from the software source.

  In FIG. 5, the other parts are the same as those in FIG. That is, the software source group 11 is built by the compiler / linker 12 (a program for executing compilation and linking), and is composed of two elements: an execution code 131 (execution software) and debug information 132 shown in FIG. An object file 13 is generated.

  In the HDL simulator 10, a CPU model 15 as a test bench 14, and an FPGA model 16 and an HW model 17 as hardware to be debugged are described. The CPU model 15 executes an execution code 131 to simulate actual software. The HDL simulator simulates the operation of the hardware to be debugged (FPGA model 16 and HW model 17), and the simulation result is an operation result in which the software operation and the operation of the hardware to be debugged cooperate with each other. Displayed on the viewer 101.

  In the waveform viewer 101, a programmable counter (PC) indicating the execution address of the CPU model 15 is designated as a signal group to be observed, and the values of all the programmable counters during the simulation period are recorded.

  As in the first embodiment, the CPU model 15 uses the technique described in Patent Document 2, for example, to improve the operation speed. That is, when the execution code 131 (execution software) of the object file 13 is generated, it is created as an assembler program (described in the character string of the assembler instruction word), and the CPU model 15 analyzes the character string of the assembler instruction word. A character string analysis function unit is provided, and an assembler instruction analyzed by the character string analysis function unit is executed.

  By configuring in this way, the character string analysis of the assembler instruction word can be realized on a small scale as compared with the conventional bit pattern analysis, so that the processing speed of the CPU model can be expected to be improved.

  The hardware / software co-verification apparatus 300 configured as described above is configured by, for example, a computer, and hardware resources of a normal computer, for example, ROM, RAM, CPU, input device, output device, communication interface, hard disk, recording A medium and its driving device are provided.

  As a result of the cooperation between the hardware resource and the software resource (OS, application, etc.), the hardware / software co-verification apparatus 300 has a compiler / linker 12, an HDL simulator 10, a general-purpose text editor 20 as shown in FIG. The source file → PC search function unit 30 is implemented.

  Further, the general-purpose text editor 20 and the source file → PC search function unit 30 may be provided in the HDL simulator 10. As a good example, if the text editor function built in the HDL simulator 10 is used for the general-purpose text editor 20, the process from the cursor position designation in the text editor to the waveform display of the corresponding part in the waveform viewer 101 is completed in the HDL simulator 10. Can do.

  As described above, it is possible to display the simulation result waveform in the waveform viewer 101 corresponding to the software source at an arbitrary position displayed by the general-purpose text editor 20 without requiring an expensive logic emulator.

DESCRIPTION OF SYMBOLS 10 ... HDL simulator 11 ... Software source group 12 ... Compiler / linker 13 ... Object file 14 ... Test bench 15 ... CPU model 16 ... FPGA model 17 ... HW model 18 ... Simulation result waveform data 19 ... PC-> source file search function part 20 ... General-purpose text editor 30 ... Source file → PC search function unit 101 ... Waveform viewer 131 ... Execution code 132 ... Debug information 200, 300 ... Hardware / software co-verification device

Claims (8)

Display the CPU model equivalent to the actual machine that simulates the operation of the CPU described as the simulation environment, the hardware model that simulates the hardware to be debugged, and the simulation result waveform data of the preset observation signal group, and the observation A HDL simulator comprising a waveform display function unit that records a programmable counter value designated as a signal group and indicating an execution address of a CPU model during the entire simulation period;
The CPU model executes the execution software generated from the software source group to simulate the software of the actual machine, the HDL simulator simulates the operation of the hardware to be debugged, and displays the simulation result on the waveform display function unit.
Acquires and acquires the debug information generated from the software source group, including the instruction address, the corresponding source file name and line number, and the value of the programmable counter at any location in the displayed simulation result waveform data. A first search function unit that searches for an address that matches the address of the programmable counter and the address in the debug information, and outputs the source file name and line number corresponding to the matched address;
A first text editor function unit that is activated by the output of the first search function unit and displays the corresponding source file at the corresponding line number;
A hardware / software co-verification apparatus comprising:   2. The hardware / software co-verification apparatus according to claim 1, wherein the first search function unit and the first text editor function unit are provided in the HDL simulator. Display the CPU model equivalent to the actual machine that simulates the operation of the CPU described as the simulation environment, the hardware model that simulates the hardware to be debugged, and the simulation result waveform data of the preset observation signal group, and the observation A HDL simulator comprising a waveform display function unit that records a programmable counter value designated as a signal group and indicating an execution address of a CPU model during the entire simulation period;
The CPU model executes the execution software generated from the software source group to simulate the software of the actual machine, the HDL simulator simulates the operation of the hardware to be debugged, and displays the simulation result on the waveform display function unit.
A second text editor function unit for displaying an arbitrary software source in the software source group and acquiring the displayed source file name and cursor line number;
Debug information generated from the software source group, which includes an instruction address and a corresponding source file name and line number, is acquired, and the source file name and line number in the acquired debug information and the second text A second search function unit that searches for a location where the source file name and the cursor line number acquired by the editor function unit match and outputs the address of the match location;
The waveform display function unit displays a simulation result waveform at a location where the value of the programmable counter corresponding to the address output by the second search function unit matches the value of the programmable counter recorded in the waveform display function unit. A hardware / software co-verification apparatus characterized by the above.   The hardware / software co-verification apparatus according to claim 3, wherein the second search function unit and the second text editor function unit are provided in the HDL simulator. The execution software is described by a character string of an assembler instruction word,
5. The CPU model according to claim 1, wherein the CPU model includes a character string analysis function unit that analyzes a character string of an assembler instruction word, and executes the assembler instruction analyzed by the character string analysis function unit. 2. The hardware / software co-verification apparatus according to item 1. A hardware / software co-verification method equipped with an HDL simulator,
The HDL simulator includes a CPU model that is described as a simulation environment and that is equivalent to a real machine that simulates the operation of the CPU, a hardware model that simulates the hardware to be debugged, and simulation result waveform data of a preset observation signal group. A waveform display function unit for displaying and recording a value of a programmable counter indicating an execution address of a CPU model specified in the observation signal group during the entire simulation period,
The HDL simulator executes the execution software generated from the software source group using the CPU model to simulate the actual software, and simulates the operation of the hardware to be debugged;
The waveform display function unit displaying the simulation result;
The first search function unit of the hardware / software co-verification apparatus generates debug information including a combination of an instruction address, a corresponding source file name, and a line number generated from the software source group, and the displayed simulation result Acquires the value of the programmable counter at any location in the waveform data, searches for an address that matches the acquired programmable counter value and the address in the debug information, and outputs the source file name and line number corresponding to the matched address Steps,
The first text editor function unit of the hardware / software co-verification device is activated by the output of the first search function unit and displays the corresponding source file at the corresponding line number;
A hardware / software co-verification method characterized by comprising: A hardware / software co-verification method equipped with an HDL simulator,
The HDL simulator includes a CPU model that is described as a simulation environment and that is equivalent to a real machine that simulates the operation of the CPU, a hardware model that simulates the hardware to be debugged, and simulation result waveform data of a preset observation signal group. A waveform display function unit for displaying and recording a value of a programmable counter indicating an execution address of a CPU model specified in the observation signal group during the entire simulation period,
The HDL simulator executes the execution software generated from the software source group using the CPU model to simulate the actual software, and simulates the operation of the hardware to be debugged;
A second text editor function unit of the hardware / software co-verification apparatus displaying an arbitrary software source in the software source group and acquiring the displayed source file name and cursor line number;
The second search function unit of the hardware / software co-verification apparatus acquires debug information generated from the software source group and including the instruction address, the corresponding source file name and the line number, and the acquired debug Searching for a location where the source file name and line number in the information match the source file name and cursor line number acquired by the second text editor function unit, and outputting the address of the matching location;
The waveform display function unit displays a simulation result waveform at a location where the programmable counter value corresponding to the address output by the second search function unit matches the programmable counter value recorded in the waveform display function unit. Steps,
A hardware / software co-verification method characterized by comprising: The execution software is described by a character string of an assembler instruction word,
A step of analyzing a character string of the assembler instruction word by a character string analysis function unit of the CPU model;
A CPU model executing the analyzed assembler instruction;
The hardware / software co-verification method according to claim 6 or 7, further comprising:

Images