JP6763153B2 - Hardware / software co-verification device and hardware / software co-verification method - Google Patents

Description

The present invention relates to co-simulation of digital circuits and software in a digital system (embedded system; Embedded System) in the field of embedded systems.

Digital systems in the embedded field consist of a hardware circuit including a CPU and software executed by the CPU. In order to shorten the development period and improve the quality of digital systems in the embedded field, it is effective to perform hardware / software cooperative verification in which the hardware circuit including the CPU and the software executed by the CPU are coordinated and debugged before the actual machine is manufactured.

There are two types of collaborative verification: collaborative simulation using a HDL (Hardware Description Language) simulator and collaborative emulation using a logical emulator.

In the collaborative simulation using the HDL simulator, all the hardware circuits including the CPU are incorporated into the HDL simulator for debugging. On the other hand, in collaborative emulation using a logic emulator, the hardware circuit is incorporated into the logic emulator for debugging.

As an example of cooperative emulation using a logic emulator, there is one described in Patent Document 1.

Further, a technique for analyzing a character string of an assembler instruction word described in execution software used in the present invention is described in Patent Document 2.

Japanese Patent No. 5120103 Japanese Unexamined Patent Publication No. 2014-78087

Cooperative emulation using a logic emulator has the advantage of faster operation than collaborative simulation using an HDL simulator, but has the disadvantage that the logic emulator is very expensive.

Patent Document 1 is a method of cooperative emulation in which all hardware circuits including a CPU are incorporated into a logic emulator. However, since the CPU uses the same RTL (Register Transfer Level) level as the actual machine, it contributes to a decrease in operating speed.

Hardware / software co-verification literally coordinates the operation of hardware and software for debugging. Each coordinated operation can be observed with the waveform viewer, but the software source of the execution location cannot be seen.

As a solution to this problem, Patent Document 1 described above has a mechanism for specifying the execution location of the software source from the value of the programmable counter (PC) of the CPU model that executes the software and displaying the software source at the specific location.

However, in Patent Document 1, since the acquisition of the value of the programmable counter is limited to the event such as a breakpoint, the source cannot be displayed at any place.

On the contrary, it does not have a mechanism to identify and display the coordinated operation waveform of the hardware operation and the software operation from the software source.

The present invention solves the above problems, and an object of the present invention is to provide a device and a method capable of performing hardware / software co-verification by an HDL simulator without requiring an expensive logic emulator.

The hardware / software co-verification device according to claim 1 for solving the above problems simulates a CPU model equivalent to an actual machine that simulates CPU operation described as a simulation environment and hardware to be debugged. A waveform display that displays the simulation result waveform data of the hardware model and the preset observation signal group, and records the value of the programmable counter that indicates the execution address of the CPU model specified in the observation signal group during the entire simulation period. It has a functional unit and an HDL simulator equipped with
The CPU model executes the execution software generated from the software source group to simulate the software of the actual machine, the HDL simulator simulates the operation of the hardware to be debugged, and the simulation result is displayed on the waveform display function unit.
Acquires and acquires the debug information generated from the software source group, which is a set of the instruction address and the corresponding source file name and line number, and the value of the programmable counter at an arbitrary location in the displayed simulation result waveform data. The first search function unit that searches for an address that matches the value of the programmable counter and the address in the debug information and outputs the source file name and line number corresponding to the matched address.
It is provided with a first text editor function unit that is activated by the output of the first search function unit and displays the corresponding source file at the corresponding line number location .
The execution software is described by a character string of assembler instruction words.
The CPU model includes a character string analysis function unit that analyzes a character string of an assembler instruction word, and is characterized in that the assembler instruction analyzed by the character string analysis function unit is executed .

The hardware / software co-verification device according to claim 2 is characterized in that, in claim 1, the first search function unit and the first text editor function unit are provided in the HDL simulator. It is supposed to be.

Further, the hardware / software co-verification device according to claim 3 includes a CPU model that is described as a simulation environment and is equivalent to an actual machine that simulates the operation of the CPU, and a hardware model that simulates the hardware to be debugged. A waveform display function unit that displays the simulation result waveform data of the preset observation signal group and records the value of the programmable counter that indicates the execution address of the CPU model specified in the observation signal group during the entire simulation period. Has a HDL simulator equipped
The CPU model executes the execution software generated from the software source group to simulate the software of the actual machine, the HDL simulator simulates the operation of the hardware to be debugged, and the simulation result is displayed on the waveform display function unit.
A second text editor function unit that displays any software source in the software source group and acquires the displayed source file name and cursor line number,
Acquire debug information that is a set of instruction address and corresponding source file name and line number generated from software source group, and the source file name and line number in the acquired debug information and the second text. It is equipped with a second search function unit that searches for a location that matches the source file name and cursor line number acquired by the editor function unit and outputs the address of the matching location.
The execution software is described by a character string of assembler instruction words.
The CPU model includes a character string analysis function unit that analyzes a character string of an assembler instruction word, executes an assembler instruction analyzed by the character string analysis function unit, and executes the assembler instruction.
The waveform display function unit displays a simulation result waveform at a location where the value of the programmable counter corresponding to the address output by the second search function unit and the value of the programmable counter recorded in the waveform display function unit match. It is characterized by that.

The hardware / software co-verification device according to claim 4 is characterized in that, in claim 3, the second search function unit and the second text editor function unit are provided in the HDL simulator. It is supposed to be.

Further, the hardware / software co-verification method according to claim 5 is a hardware / software co-verification method provided with an HDL simulator.
The HDL simulator creates a CPU model equivalent to an actual machine that simulates the operation of the CPU, a hardware model that simulates the hardware to be debugged, and simulation result waveform data of a preset observation signal group, which is described as a simulation environment. It is equipped with a waveform display function unit that displays and records the value of the programmable counter that indicates the execution address of the CPU model specified in the observation signal group during the entire simulation period.
The HDL simulator executes the execution software generated from the software source group by the CPU model to simulate the software of the actual machine, and also simulates the operation of the hardware to be debugged.
A step in which the waveform display function unit displays the simulation result,
The first search function unit of the hardware / software co-verification device performs debug information generated from the software source group as a set of the instruction address and the corresponding source file name and line number, and the displayed simulation result. Acquires the value of the programmable counter at any location in the waveform data, searches for an address that matches the acquired programmable counter value and the address in the debug information, and outputs the source file name and line number corresponding to the matched address. Steps and
The first text editor function unit of the hardware / software co-verification device is activated by the output of the first search function unit, and includes a step of displaying the corresponding source file at the corresponding line number .
The execution software is described by a character string of assembler instruction words.
A step in which the character string analysis function unit of the CPU model analyzes the character string of the assembler instruction word,
The step in which the CPU model executes the parsed assembler instruction,
It is characterized by comprising a.

Further, the hardware / software co-verification method according to claim 6 is a hardware / software co-verification method including an HDL simulator.
The HDL simulator creates a CPU model equivalent to an actual machine that simulates the operation of the CPU, a hardware model that simulates the hardware to be debugged, and simulation result waveform data of a preset observation signal group, which is described as a simulation environment. It is equipped with a waveform display function unit that displays and records the value of the programmable counter that indicates the execution address of the CPU model specified in the observation signal group during the entire simulation period.
The HDL simulator executes the execution software generated from the software source group by the CPU model to simulate the software of the actual machine, and also simulates the operation of the hardware to be debugged.
The step that the second text editor function part of the hardware / software co-verification device displays any software source in the software source group and acquires the displayed source file name and cursor line number,
The second search function unit of the hardware / software co-verification device acquires the debug information generated from the software source group, which is a set of the instruction address and the corresponding source file name and line number, and the acquired debug. A step of searching for a location where the source file name and line number in the information match the source file name and cursor line number acquired by the second text editor function unit, and outputting the address of the matching location.
The waveform display function unit displays a simulation result waveform at a location where the value of the programmable counter corresponding to the address output by the second search function unit and the value of the programmable counter recorded in the waveform display function unit match. With steps ,
The execution software is described by a character string of assembler instruction words.
A step in which the character string analysis function unit of the CPU model analyzes the character string of the assembler instruction word,
The step in which the CPU model executes the parsed assembler instruction,
It is characterized by comprising a.

According to the above configuration, the CPU model and the hardware model as the simulation environment (test bench) are described in the HDL simulator, and the CPU model executes the execution software generated from the software source group to simulate the software of the actual machine. Since the HDL simulator is configured to simulate the operation of the hardware to be debugged, hardware / software co-verification can be performed with the HDL simulator without the need for an expensive logic emulator.
Further, since the execution software of the CPU model analyzes and executes the character string of the assembler instruction word, the operation speed is improved.

Further, according to the configurations of claims 1, 2 and 5 , the part of the arbitrary simulation result waveform displayed in the waveform display function unit by the operation of the first search function unit and the first text editor function unit. The software source corresponding to the value of the programmable counter can be displayed.

Further, according to the configurations of claims 3, 4, and 6, the simulation result waveform corresponding to an arbitrary part of the software source is specified and displayed by the operation of the second search function unit and the second text editor function unit. be able to.

Further, according to claim 2, the process from the designation of an arbitrary part in the simulation result waveform data displayed by the waveform display function to the display of the source file can be completed in the HDL simulator.

Further, according to claim 4, the process from the designation of the cursor line of any software source to be displayed to the display of the simulation result waveform can be completed in the HDL simulator.

(1) According to the inventions of claims 1 to 6 , hardware / software co-verification can be performed with an HDL simulator without the need for an expensive logic emulator. In addition, the operating speed can be improved.
(2) Further, according to the invention of claims 1, 2 and 5, the software source corresponding to the value of the programmable counter at the place of the arbitrary simulation result waveform displayed on the waveform display function unit is displayed. Can be done.
(3) Further, according to the inventions of claims 3, 4 and 6, it is possible to identify and display the simulation result waveform corresponding to any part of the software source.
(4) Further, according to the invention of claim 2, it is possible to complete from the designation of an arbitrary part in the simulation result waveform data displayed in the waveform display function to the display of the source file in the HDL simulator. ..
(5) Further, according to the invention of claim 4, the process from the designation of the cursor line of any software source to be displayed to the display of the simulation result waveform can be completed in the HDL simulator .

The block diagram which shows the whole of Example 1 of this invention. The explanatory view which shows the debug information in the Example of this invention. Explanatory drawing which shows the main part structure of Example 1 of this invention. Explanatory drawing which shows the modification of Example 1 of this invention. The block diagram which shows the whole of Example 2 of this invention. Explanatory drawing which shows the main part structure of Example 2 of this invention.

The hardware / software co-verification of the present invention is based on a co-simulation using an HDL simulator. Hereinafter, examples of the present invention will be described with reference to the drawings, but the present invention is not limited to the following examples.

FIG. 1 shows the configuration of the hardware / software cooperative verification device 200 according to the first embodiment of the present invention. A software source group 11 described in C language or assembler language (also referred to as assembly language) is built by a compiler / linker 12 (a program that executes compilation and linking), and an object file 13 is generated. The object file 13 is composed of two elements, an execution code 131 (execution software) and debug information 132.

In the HDL simulator 10, a CPU model 15, an FPGA (Field Programmable Gate Array) model 16 and an HW (hardware) model 17, which are hardware to be debugged, are described as a test bench 14 (simulation environment for verification). ing.

Reference numeral 25 denotes a bus model that connects the CPU model 15, the FPGA model 16, and the HW model 17.

The CPU model 15 is a model equivalent to an actual machine that simulates the operation of the CPU, executes the execution code 131 (execution software) to simulate the software of the actual machine, and the HDL simulator is the hardware to be debugged (FPGA model 16, HW). The operation of model 17) is simulated. The CPU model 15 adopts a behavior model having a higher degree of abstraction than the RTL model.

The FPGA model 16 is a model simulating a rewritable logic element, and the HW model 17 is a model simulating hardware.

The CPU model 15 aims to improve the operating speed by using, for example, the technique described in Patent Document 2. That is, when the execution code 131 (execution software) of the object file 13 is generated, it is created as an assembler program instead of the object code (described by the character string of the assembler instruction word), and the characters of the assembler instruction word are described in the CPU model 15. A character string analysis function unit that analyzes a column is provided, and an assembler instruction analyzed by the character string analysis function unit is executed.

With this configuration, the character string analysis of the assembler instruction word can be realized on a smaller scale than the conventional bit pattern analysis, so that the processing speed of the CPU model can be expected to be improved.

The simulation result of the test bench 14 is an operation result in which the software operation of the CPU 15 and the operation of the hardware to be debugged (FPGA model 16 and HW model 17) are coordinated, and the waveform viewer 101 (waveform display function unit) is used as the simulation result waveform data 18. Is displayed in.

In the waveform viewer 101, a signal group to be observed is specified before the simulation. A programmable counter (PC) indicating the execution address of the CPU model 15 is always specified for the signal group to be observed, and all programmable counters (values) within the simulation period are recorded.

The value of the programmable counter at an arbitrary place during the simulation (the place where the cursor of the waveform viewer 101 is placed) is acquired from the simulation result waveform data 18 by the function of the HDL simulator 10, and the debug information 132 and the PC → source file search function unit 19 Enter in (1st search function unit).

As shown in FIG. 2, the debug information 132 is composed of each instruction address for all instructions and a set of a source file name and a line number corresponding thereto.

PC → The source file search function unit 19 searches for an address that matches the value of the programmable counter (acquired PC) acquired from the simulation result waveform data 18 and the address in the debug information 132, as shown in FIG. 3, and matches the address. Output the source file name and line number corresponding to.

For example, in the example of FIG. 3, the value "1010" of the programmable counter (acquired PC) acquired from the simulation result waveform data 18 matches the address "1010" in the debug information 132, so that the source file name of the matched address "D: \ WORK \ AAA.C" and the line number "35" are output.

When the general-purpose text editor 20 (first text editor function unit) is started with the source file name and line number obtained in this way as startup options, the corresponding source file is displayed at the corresponding line number (the line where the cursor is). can do.

The hardware / software co-verification device 200 configured as described above is composed of, for example, a computer, and has hardware resources of a normal computer, such as ROM, RAM, CPU, input device, output device, communication interface, hard disk, and recording. It includes a medium and its drive device.

As a result of the collaboration between the hardware resource and the software resource (OS, application, etc.), the hardware / software co-verification device 200 has the compiler / linker 12, the HDL simulator 10, the PC → the source file, as shown in FIG. The search function unit 19 and the general-purpose text editor 20 are implemented.

Next, the operation of the hardware / software co-verification device 200 configured as described above will be described.

The HDL simulator 10 simulates the test bench 14 and displays the simulation result as the simulation result waveform data 18 on the built-in waveform viewer 101.

A desired operation location is selected with a cursor, and the value (PC value) of the programmable counter is acquired by using the function of acquiring the signal state of the cursor position provided in the waveform viewer 101.

The simulation result waveform data 18 includes not only normal software execution but also interrupt operation and direct memory access (DMA) operation which are indispensable in the embedded system, and the software execution time of the CPU varies depending on the interrupt and direct memory access. Of course, the update timing of the programmable counter is also linked. The interrupt operation and the direct memory access operation are generated depending on the hardware state, and can be realized by including the CPU model 15, FPGA model 16, and HW model 17 in the test bench 14. Since it is possible to acquire the value of the programmable counter at any location such as when an interrupt occurs or during DMA operation, it is effective for debugging both hardware and software of the embedded system.

The acquired programmable counter value is input to the PC → source file search function unit 19 together with the debug information 132. The PC → source file search function unit 19 searches for an address that matches the acquired programmable counter value (PC value) and the address in the debug information 132, as shown in FIG. 3, and the source file corresponding to the matched address. Output the first name and line number. When the general-purpose text editor 20 is started with the obtained source file name and line number as start options, the corresponding source file can be displayed at the corresponding line number (the line where the cursor is).

Further, when the software source corresponding to the value of the programmable counter at the desired location of the simulation result waveform data 18 is displayed and then the cursor is moved to the next change point of the programmable counter (PC) using the function provided in the waveform viewer 101. By using the above-mentioned function to acquire the signal status of the cursor position and the PC → file search function unit 19, a new corresponding source file name and line number are acquired, and the general-purpose text editor 20 is restarted as a start option. , The display position (cursor position) can be updated. That is, the cursor movement of the waveform viewer 101 and the display location of the software source can be linked.

A series of operation examples is shown in FIG. In FIG. 4, when the cursor of the waveform viewer 101 is moved from the change point (1) (1000 address) of the programmable counter (PC) to the change point (2) (1002 address), the general-purpose text editor 20 is linked accordingly. The cursor moves from the source location at address 1000 to the source location at address 1002.

The PC → source file search function unit 19 and the general-purpose text editor 20 may be provided in the HDL simulator 10. As a good example, if the text editor function built into the HDL simulator 10 is used in the general-purpose text editor 20, the process from specifying the cursor position in the waveform viewer 101 to displaying the software source in the text editor can be completed in the HDL simulator 10. ..

As described above, it is possible to display the software source corresponding to the value of the programmable counter at any place of the simulation result waveform data 18 without requiring an expensive logic emulator.

In the second embodiment, hardware / software co-verification can be performed with the HDL simulator without the need for an expensive logic emulator, and contrary to the first embodiment, a simulation corresponding to any part thereof can be performed from the software source. The result waveform can be specified and displayed.

FIG. 5 shows the configuration of the hardware / software cooperative verification device 300 according to the second embodiment, and the same parts as those in FIG. 1 are indicated by the same reference numerals.

The difference from FIG. 1 in FIG. 5 is that the file name and cursor of the display source file acquired from the general-purpose text editor 20 (second text editor function unit) instead of the PC → source file search function unit 19 in FIG. Enter the line number and the file name and line number information in the debug information 132, and enter the file name and line number in the debug information 132 and the file name and cursor line number of the display source file obtained from the general-purpose text editor 20. A source file that searches for a location that matches with and outputs the address of the matching location → A PC search function unit 30 (second search function unit) is provided.

The address output from this source file → PC search function unit 30 is the value of the programmable counter specified in the simulation result waveform data 18 of the waveform viewer 101 corresponding to the cursor position of the source file displayed on the general-purpose text editor 20. (Corresponding PC value) is shown.

The waveform viewer 101 uses its own search function to move the cursor of the waveform viewer 101 to the programmable counter indicated by the value of the programmable counter in the simulation result waveform data 18 and the output address of the source file → PC search function unit 30. Move to the place where the value of is matched, and display the simulation result waveform. This makes it possible to identify and display the simulation result waveform corresponding to the arbitrary portion from the software source.

In FIG. 5, the parts other than the above are configured in the same manner as in FIG. That is, the software source group 11 is built by the compiler / linker 12 (the program that executes compilation and linking), and is composed of two elements: the execution code 131 (execution software) and the debug information 132 shown in FIG. The object file 13 is generated.

In the HDL simulator 10, the CPU model 15 and the hardware to be debugged, the FPGA model 16 and the HW model 17, are described as the test bench 14, and the CPU model 15 executes the execution code 131 to simulate the software of the actual machine. , The HDL simulator simulates the operation of the hardware to be debugged (FPGA model 16 and HW model 17), and the simulation result becomes the operation result in which the software operation and the operation of the hardware to be debugged are coordinated, and the simulation result waveform data 18 is used as the waveform. It is displayed on the viewer 101.

In the waveform viewer 101, a programmable counter (PC) indicating the execution address of the CPU model 15 is designated for the signal group to be observed, and the values of all the programmable counters during the simulation period are recorded.

Further, similarly to the first embodiment, the CPU model 15 aims to improve the operating speed by using, for example, the technique described in Patent Document 2. That is, when the execution code 131 (execution software) of the object file 13 is generated, it is created as an assembler program (described by the character string of the assembler instruction word), and the CPU model 15 analyzes the character string of the assembler instruction word. A character string analysis function unit is provided, and the assembler instruction analyzed by the character string analysis function unit is executed.

With this configuration, the character string analysis of the assembler instruction word can be realized on a smaller scale than the conventional bit pattern analysis, so that the processing speed of the CPU model can be expected to be improved.

The hardware / software co-verification device 300 configured as described above is composed of, for example, a computer, and has hardware resources of a normal computer, such as ROM, RAM, CPU, input device, output device, communication interface, hard disk, and recording. It includes a medium and its drive device.

As a result of the collaboration between the hardware resource and the software resource (OS, application, etc.), the hardware / software co-verification device 300 includes the compiler / linker 12, the HDL simulator 10, and the general-purpose text editor 20 as shown in FIG. , Source file → Implement the PC search function unit 30.

Further, the general-purpose text editor 20 and the source file → PC search function unit 30 may be provided in the HDL simulator 10. As a good example, if the text editor function built into the HDL simulator 10 is used in the general-purpose text editor 20, the process from specifying the cursor position in the text editor to displaying the waveform of the corresponding part in the waveform viewer 101 can be completed in the HDL simulator 10. Can be done.

As described above, it is possible to display the simulation result waveform in the waveform viewer 101 corresponding to the software source at any position displayed by the general-purpose text editor 20 without the need for an expensive logic emulator.

10 ... HDL simulator 11 ... Software source group 12 ... Compiler / linker 13 ... Object file 14 ... Test bench 15 ... CPU model 16 ... FPGA model 17 ... HW model 18 ... Simulation result waveform data 19 ... PC → Source file search function 20 … General-purpose text editor 30… Source file → PC search function 101… Waveform viewer 131… Execution code 132… Debugging information 200, 300… Hardware / software co-verification device

Claims (6)

A CPU model equivalent to an actual machine that simulates the operation of the CPU described as a simulation environment, a hardware model that simulates the hardware to be debugged, and simulation result waveform data of a preset observation signal group are displayed, and the observation is performed. It has an HDL simulator provided with a waveform display function unit that records the value of a programmable counter that indicates the execution address of the CPU model specified in the signal group during the entire simulation period.
The CPU model executes the execution software generated from the software source group to simulate the software of the actual machine, the HDL simulator simulates the operation of the hardware to be debugged, and the simulation result is displayed on the waveform display function unit.
Acquires and acquires the debug information generated from the software source group, which is a set of the instruction address and the corresponding source file name and line number, and the value of the programmable counter at an arbitrary location in the displayed simulation result waveform data. The first search function unit that searches for an address that matches the value of the programmable counter and the address in the debug information and outputs the source file name and line number corresponding to the matched address.
It is provided with a first text editor function unit that is activated by the output of the first search function unit and displays the corresponding source file at the corresponding line number location .
The execution software is described by a character string of assembler instruction words.
The CPU model is a hardware / software cooperative verification device including a character string analysis function unit that analyzes a character string of an assembler instruction word, and executes an assembler instruction analyzed by the character string analysis function unit . The hardware / software cooperative verification device according to claim 1, wherein the first search function unit and the first text editor function unit are provided in the HDL simulator. A CPU model equivalent to an actual machine that simulates the operation of the CPU described as a simulation environment, a hardware model that simulates the hardware to be debugged, and simulation result waveform data of a preset observation signal group are displayed, and the observation is performed. It has an HDL simulator provided with a waveform display function unit that records the value of a programmable counter that indicates the execution address of the CPU model specified in the signal group during the entire simulation period.
The CPU model executes the execution software generated from the software source group to simulate the software of the actual machine, the HDL simulator simulates the operation of the hardware to be debugged, and the simulation result is displayed on the waveform display function unit.
A second text editor function unit that displays any software source in the software source group and acquires the displayed source file name and cursor line number,
Acquire debug information that is a set of instruction address and corresponding source file name and line number generated from software source group, and the source file name and line number in the acquired debug information and the second text. It is equipped with a second search function unit that searches for a location that matches the source file name and cursor line number acquired by the editor function unit and outputs the address of the matching location.
The execution software is described by a character string of assembler instruction words.
The CPU model includes a character string analysis function unit that analyzes a character string of an assembler instruction word, executes an assembler instruction analyzed by the character string analysis function unit, and executes the assembler instruction.
The waveform display function unit displays a simulation result waveform at a location where the value of the programmable counter corresponding to the address output by the second search function unit and the value of the programmable counter recorded in the waveform display function unit match. A hardware / software co-verification device characterized by this. The hardware / software cooperative verification device according to claim 3, wherein the second search function unit and the second text editor function unit are provided in the HDL simulator. A hardware / software co-verification method equipped with an HDL simulator.
The HDL simulator creates a CPU model equivalent to an actual machine that simulates the operation of the CPU, a hardware model that simulates the hardware to be debugged, and simulation result waveform data of a preset observation signal group, which is described as a simulation environment. It is equipped with a waveform display function unit that displays and records the value of the programmable counter that indicates the execution address of the CPU model specified in the observation signal group during the entire simulation period.
The HDL simulator executes the execution software generated from the software source group by the CPU model to simulate the software of the actual machine, and also simulates the operation of the hardware to be debugged.
A step in which the waveform display function unit displays the simulation result,
The first search function unit of the hardware / software co-verification device performs debug information generated from the software source group as a set of the instruction address and the corresponding source file name and line number, and the displayed simulation result. Acquires the value of the programmable counter at any location in the waveform data, searches for the address that matches the acquired programmable counter value and the address in the debug information, and outputs the source file name and line number corresponding to the matched address. Steps and
The first text editor function unit of the hardware / software co-verification device is activated by the output of the first search function unit, and includes a step of displaying the corresponding source file at the corresponding line number .
The execution software is described by a character string of assembler instruction words.
A step in which the character string analysis function unit of the CPU model analyzes the character string of the assembler instruction word,
The step in which the CPU model executes the parsed assembler instruction,
A hardware / software co-verification method characterized by being equipped with . A hardware / software co-verification method equipped with an HDL simulator.
The HDL simulator creates a CPU model equivalent to an actual machine that simulates the operation of the CPU, a hardware model that simulates the hardware to be debugged, and simulation result waveform data of a preset observation signal group, which is described as a simulation environment. It is equipped with a waveform display function unit that displays and records the value of the programmable counter that indicates the execution address of the CPU model specified in the observation signal group during the entire simulation period.
The HDL simulator executes the execution software generated from the software source group by the CPU model to simulate the software of the actual machine, and also simulates the operation of the hardware to be debugged.
The step that the second text editor function part of the hardware / software co-verification device displays any software source in the software source group and acquires the displayed source file name and cursor line number,
The second search function unit of the hardware / software co-verification device acquires the debug information generated from the software source group, which is a set of the instruction address and the corresponding source file name and line number, and the acquired debug. A step of searching for a location where the source file name and line number in the information match the source file name and cursor line number acquired by the second text editor function unit, and outputting the address of the matching location.
The waveform display function unit displays a simulation result waveform at a location where the value of the programmable counter corresponding to the address output by the second search function unit and the value of the programmable counter recorded in the waveform display function unit match. With steps ,
The execution software is described by a character string of assembler instruction words.
A step in which the character string analysis function unit of the CPU model analyzes the character string of the assembler instruction word,
The step in which the CPU model executes the parsed assembler instruction,
A hardware / software co-verification method characterized by being equipped with .

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