CN111950212A - Efficient multi-mode verification platform and method - Google Patents
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Abstract
The invention provides an efficient multi-mode verification platform and a method, which comprises the following steps: step 1, inputting test excitation into a multi-mode verification platform, and calling library and IP respectively by the multi-mode verification platform to perform software simulation verification; step 2, finding errors in the software simulation verification process, returning to a DUT directory, and modifying a chip design file; and 3, performing prototype verification of the FPGA hardware system without errors in the software simulation verification process. The invention is compatible with software simulation verification and FPGA hardware system prototype verification under the FPGA development condition, the software simulation verification supports single testcase or multiple testcase parallel simulation, each testcase simulation result has respective space storage and cannot be covered, the multi-mode verification platform supports automatic reading and real-time refreshing of design files, can support automatic full compilation and manual step compilation, effectively avoids the difficulty of engineering file management, and reduces the complicated operation of engineering compilation and online debugging.
Description
Technical Field
The invention relates to the technical field of digital integrated circuit design and verification, in particular to a high-efficiency multi-mode verification platform and a method.
Background
The well-known moore's law indicates that the number of transistors that a chip of an integrated circuit can accommodate is doubled every 18 months, and the performance is also doubled, which makes the complexity of the chip higher and higher, and brings a serious challenge to the verification work of the digital integrated circuit.
Software simulation verification is based on verification methodologies (UVM, VMM and the like) and is performed by establishing test excitation in a language programming mode, the verification mode is complex in environment, heavy in programming, simulation and debugging work, and difficult to take full consideration of the actual application scene of a chip.
The core of the prototype verification of the hardware system is to utilize an FPGA chip to realize the function of a designed digital integrated circuit and directly verify the correctness of the chip on board-level hardware, wherein the FPGA (field Programmable Gate array) is a field Programmable device, the actual chip production of the integrated circuit is not needed, and the application of simulating various integrated circuits can be quickly realized by a programming mode. Currently, most FPGA chips have huge logic, storage and IP resources, so that a system-level hardware verification platform can be built by using the FPGA in chip design front-end verification, and all or part of functions of the whole chip can be completed on the FPGA. Through FPGA board level debugging, can verify the bug of hiding in the chip design fast, can directly perceivedly experience the effect of chip design, discover the defect of system design or the limitation of using. Thereby reducing the verification period of the chip design.
Disclosure of Invention
The invention provides an efficient multi-mode verification platform and a method, and aims to solve the problems that the traditional verification platform is low in verification efficiency, poor in quality and difficult to maintain.
To achieve the above object, an embodiment of the present invention provides an efficient multi-modal verification platform, including:
the system comprises an asic module, a chip module and a control module, wherein the asic module comprises a software simulation platform of chip design and a configuration file;
a config module that includes a global profile for the multimodal authentication platform;
the system comprises an FPga module, wherein the FPga module comprises an FPGA system prototype verification platform and a configuration file.
Wherein, the asic module includes:
an analog unit, the analog unit comprising an analog integrated circuit IP model;
a bin unit comprising a common file processing script;
a config unit including DUT.f, DUT _ fpga.f, MODEL.f, TB.f, TESTLIST and configuration files required by software simulation of chip design;
the doc unit is used for storing record files in the chip research and development process;
the lib unit is used for storing a chip design process library and a soft core IP;
the device comprises a modules unit, a monitoring unit and a control unit, wherein the modules unit comprises a peripheral device model and a software simulation monitor which are actually applied by a chip;
the system comprises a sim unit, a software integration unit and a software integration unit, wherein the sim unit is provided with two subdirectory spaces task and run, the task comprises a testcase library, and the run is a simulation result storage space;
a tb unit, which is a test stimulus for chip verification;
a verilog directory comprising the entire chip design file.
Wherein the fpga module comprises:
a design input file including an fpga _ edif unit, and an fpga _ hdl unit;
a mem _ init unit, the mem _ init unit including initialization data of a memory;
the reports unit comprises an FPGA compiling report output storage space;
the result unit comprises an FPGA compiling result output storage space;
a run unit, which is a space for FPGA to execute compilation;
and the tcl unit comprises configuration and script files for the FPGA to execute compiling and system prototype verification.
The embodiment of the invention also provides an efficient multi-mode verification method, which comprises the following steps:
and 4, finding errors in the process of executing the prototype verification of the FPGA hardware system, returning to the DUT directory, modifying the chip design file, and re-performing software simulation verification and the prototype verification of the FPGA hardware system.
Wherein, the step 1 specifically comprises:
simulation verification of a single testcase is performed:
step 1.1.1, adding a new testcase in the multi-mode verification platform, and inputting a simulation instruction;
step 1.1.2, the multi-mode verification platform analyzes the simulation instruction, and the method comprises the steps of searching for testcase definition, searching for testcase required files, summarizing simulated compiling macro definition and compiling instructions, running a setting script before simulation, caching a result detection script when simulation is finished, and establishing a storage directory of simulation results;
step 1.1.3, reading each file of the DUT and a related configuration file;
step 1.1.4, starting software simulation verification, and automatically running a software simulation verification result detection script after the software simulation verification is finished;
step 1.1.5, checking a software simulation verification result, wherein the software simulation verification result comprises a simulation information recording file and a report file for running a script to detect result data;
and step 1.1.6, finding that errors exist in the software simulation verification process, returning to a DUT directory, modifying a chip design file, re-executing the software simulation verification of the current testcase, adding a new testcase if no errors exist in the software simulation verification process, and circulating the operation until all functions of the chip design are covered.
Wherein, the step 1 further comprises:
and (3) performing parallel simulation verification of a plurality of testcases during regression simulation:
step 1.2.1, setting a testcase list, and adding the testcase list to the multi-mode verification platform;
step 1.2.2, the multi-mode verification platform analyzes the simulation instruction, and the method comprises the steps of searching for the definition of each testcase, searching for the file required by each testcase, summarizing the compiling macro definition and the compiling quality of each testcase simulation, running a setting script before each testcase simulation and caching a result detection script when each testcase simulation is finished;
step 1.2.3, reading each file of the DUT and a related configuration file;
step 1.2.4, software simulation verification is started, and a software simulation verification result detection script is automatically run after the simulation verification of each testcase software is finished;
step 1.2.5, summarizing software simulation verification results;
and step 1.2.6, checking a regression simulation report, wherein the regression simulation report comprises whether the simulation verification of each testcase software is finished correctly and the code coverage rate of the simulation.
Wherein, the step 4 specifically comprises:
performing FPGA full compilation and system prototype verification:
step 4.1.1, the multi-mode verification platform analyzes the input instruction, and the multi-mode verification platform comprises the steps of setting relevant variable values in the FPGA full compiling process, judging an operation mode and executing a setting script before FPGA compiling;
step 4.1.2, starting Vivado software, if the FPGA project is not established currently, automatically establishing the FPGA project, otherwise, automatically loading the FPGA project;
step 4.13, performing the comprehensive and the time sequence analysis after the comprehensive, outputting a comprehensive result and a time sequence analysis report, and saving the output comprehensive result and the time sequence analysis report by taking the date of the day as a version number;
step 4.1.4, executing the back end PR, outputting a result and a report of the back end PR, and saving the output result and the output report of the back end PR by taking the date of the day as a version number;
step 4.1.5, downloading the burning file of the FPGA, and performing board-level debugging and verification;
and 4.1.6, detecting the verification result of the FPGA, modifying the FPGA configuration file when the verification result of the FPGA has a problem, recompiling the FPGA, modifying the DUT design file if a design error is found, returning to the software simulation verification of the chip design again, and finishing the verification if the verification result of the FPGA passes.
Wherein, the step 4 further comprises:
performing FPGA manual step compiling:
step 4.2.1, the multi-mode verification platform analyzes the input instruction, and the multi-mode verification platform comprises the steps of setting relevant variable values in the FPGA full compiling process, judging an operation mode and executing a setting script before FPGA compiling;
step 4.2.2, starting Vivado software, if the FPGA project is not established currently, automatically establishing the FPGA project, otherwise, automatically loading the FPGA project;
step 4.2.3, performing FPGA compiling step analyzed by the instruction;
step 4.2.4, outputting results and reports after the current compiling step of the FPGA is finished, and saving the output results and reports by taking the date of the day as a version number;
and 4.2.5, analyzing the result and the report.
The scheme of the invention has the following beneficial effects:
the efficient multi-mode verification platform and the method provided by the embodiment of the invention are compatible with software simulation verification and FPGA hardware system prototype verification under the FPGA development condition, the software simulation verification supports single testcase or multiple testcase parallel simulation, each testcase simulation result has respective space storage and cannot be covered, the multi-mode verification platform supports automatic reading and real-time refreshing of design files, can support automatic full compilation and manual step compilation, effectively avoid the difficulty in engineering file management, and reduce the complicated operations of engineering compilation and online debugging.
Drawings
FIG. 1 is a schematic diagram of the general structure of the present invention;
FIG. 2 is a schematic diagram of the detailed structure of the asic module according to the present invention;
FIG. 3 is a schematic diagram of an embodiment of an fpga module of the present invention;
FIG. 4 is a flow chart of the present invention;
FIG. 5 is a schematic overall verification process according to the present invention;
FIG. 6 is a flow chart of simulation verification of a single testcase of the present invention;
FIG. 7 is a flow chart of a multi-testcase concurrent simulation verification method according to the present invention;
FIG. 8 is a flow chart of the FPGA full compilation and system prototype verification of the present invention;
FIG. 9 is a flow chart of the FPGA manual step-by-step compilation of the present invention.
Detailed Description
In order to make the technical problems, technical solutions and advantages of the present invention more apparent, the following detailed description is given with reference to the accompanying drawings and specific embodiments.
The invention provides a high-efficiency multi-mode verification platform and a method aiming at the problems of low verification efficiency, poor quality and difficult maintenance of the existing verification platform.
As shown in FIG. 1, embodiments of the present invention provide an efficient multi-modal authentication platform, comprising: the system comprises an asic module, a chip module and a control module, wherein the asic module comprises a software simulation platform of chip design and a configuration file; a config module that includes a global profile for the multimodal authentication platform; the system comprises an FPga module, wherein the FPga module comprises an FPGA system prototype verification platform and a configuration file.
As shown in fig. 2, the asic module includes: an analog unit, the analog unit comprising an analog integrated circuit IP model; a bin unit comprising a common file processing script; a config unit including DUT.f, DUT _ fpga.f, MODEL.f, TB.f, TESTLIST and configuration files required by software simulation of chip design; the doc unit is used for storing record files in the chip research and development process; the lib unit is used for storing a chip design process library and a soft core IP; the device comprises a modules unit, a monitoring unit and a control unit, wherein the modules unit comprises a peripheral device model and a software simulation monitor which are actually applied by a chip; the system comprises a sim unit, a software integration unit and a software integration unit, wherein the sim unit is provided with two subdirectory spaces task and run, the task comprises a testcase library, and the run is a simulation result storage space; a tb unit, which is a test stimulus for chip verification; a verilog directory comprising the entire chip design file.
As shown in fig. 3, the fpga module includes: a design input file including an fpga _ edif unit, and an fpga _ hdl unit; a mem _ init unit, the mem _ init unit including initialization data of a memory; the reports unit comprises an FPGA compiling report output storage space; the result unit comprises an FPGA compiling result output storage space; a run unit, which is a space for FPGA to execute compilation; and the tcl unit comprises configuration and script files for the FPGA to execute compiling and system prototype verification.
As shown in fig. 4 to 5, an embodiment of the present invention further provides an efficient multi-mode authentication method, including: step 1, inputting test excitation into a multi-mode verification platform, and calling library and IP respectively by the multi-mode verification platform to perform software simulation verification; step 2, finding errors in the software simulation verification process, returning to a DUT directory, and modifying a chip design file; step 3, no error occurs in the software simulation verification process, and the prototype verification of the FPGA hardware system is executed; and 4, finding errors in the process of executing the prototype verification of the FPGA hardware system, returning to the DUT directory, modifying the chip design file, and re-performing software simulation verification and the prototype verification of the FPGA hardware system.
The efficient multi-mode verification platform and the efficient multi-mode verification method comprise software simulation verification and FPGA hardware system prototype verification, wherein the software simulation verification comprises simulation verification under a chip design condition and simulation verification under an FPGA development condition, the software simulation verification and the FPGA hardware system prototype verification are different in that library and IP called in a simulation process are different, a DUT (device under test) and a Testbench (test stimulus) are the same, and simulated testcases are also the same. If bugs are found in the software simulation flow, returning to the DUT, modifying the design file until no bugs appear in the software simulation, and executing the prototype verification flow of the FPGA hardware system; and if the bug is found by the prototype verification of the FPGA hardware system, returning to the DUT, modifying the design file, and performing the software simulation verification process and the prototype verification process of the FPGA hardware system again.
As shown in fig. 6, the step 1 specifically includes: simulation verification of a single testcase is performed: step 1.1.1, adding a new testcase in the multi-mode verification platform, and inputting a simulation instruction; step 1.1.2, the multi-mode verification platform analyzes the simulation instruction, and the method comprises the steps of searching for testcase definition, searching for testcase required files, summarizing simulated compiling macro definition and compiling instructions, running a setting script before simulation, caching a result detection script when simulation is finished, and establishing a storage directory of simulation results; step 1.1.3, reading each file of the DUT and a related configuration file; step 1.1.4, starting software simulation verification, and automatically running a software simulation verification result detection script after the software simulation verification is finished; step 1.1.5, checking a software simulation verification result, wherein the software simulation verification result comprises a simulation information recording file and a report file for running a script to detect result data; and step 1.1.6, finding that errors exist in the software simulation verification process, returning to a DUT directory, modifying a chip design file, re-executing the software simulation verification of the current testcase, adding a new testcase if no errors exist in the software simulation verification process, and circulating the operation until all functions of the chip design are covered.
In the efficient multi-mode verification platform and method according to the embodiments of the present invention, the simulation verification process of a single testcase of software simulation verification is as follows: step one, adding a new testcase and inputting a simulation instruction; secondly, the high-efficiency multi-mode verification platform analyzes the simulation instruction, and comprises the steps of searching for the definition of testcase, searching for files required by testcase, summarizing the compilation macro definition and the compilation instruction of simulation, running a set script before simulation, caching a result detection script when the simulation is finished, and establishing a storage directory of the simulation result; reading each file of the DUT and related configuration files; fourthly, starting software simulation, and automatically running a simulation result detection script after the simulation is finished; fifthly, checking a simulation result, wherein the simulation result comprises a simulation information recording file and a report file for running a script to detect result data; and sixthly, if the simulation finds that the bug exists, returning to the DUT directory, modifying the chip design file, re-executing the simulation verification of the testcase, and if the bug does not exist, adding another testcase, and repeating the steps until all functions of the chip design are covered.
As shown in fig. 7, step 1 further includes: and (3) performing parallel simulation verification of a plurality of testcases during regression simulation: step 1.2.1, setting a testcase list, and adding the testcase list to the multi-mode verification platform; step 1.2.2, the multi-mode verification platform analyzes the simulation instruction, and the method comprises the steps of searching for the definition of each testcase, searching for the file required by each testcase, summarizing the compiling macro definition and the compiling quality of each testcase simulation, running a setting script before each testcase simulation and caching a result detection script when each testcase simulation is finished; step 1.2.3, reading each file of the DUT and a related configuration file; step 1.2.4, software simulation verification is started, and a software simulation verification result detection script is automatically run after the simulation verification of each testcase software is finished; step 1.2.5, summarizing software simulation verification results; and step 1.2.6, checking a regression simulation report, wherein the regression simulation report comprises whether the simulation verification of each testcase software is finished correctly and the code coverage rate of the simulation.
In the efficient multi-mode verification platform and method of the embodiments of the present invention, the parallel simulation verification process of multiple testcases during the regression simulation of software simulation verification is as follows: firstly, setting a testcase list; secondly, the efficient multi-mode verification platform analyzes the simulation instruction, and comprises the steps of searching for the definition of each testcase, searching for the file required by each testcase, summarizing the compiling macro definition and the compiling quality of each testcase simulation, running a setting script before each testcase simulation, and caching a result detection script when each testcase simulation is finished; reading each file of the DUT and related configuration files; fourthly, software simulation is started, and a simulation result detection script is automatically run after the simulation of each testcase is finished; fifthly, summarizing simulation results; and sixthly, checking a regression simulation report, wherein the regression simulation report comprises whether each testcase simulation is correctly finished and the code coverage rate of the simulation.
As shown in fig. 8, the step 4 specifically includes: performing FPGA full compilation and system prototype verification: step 4.1.1, the multi-mode verification platform analyzes the input instruction, and the multi-mode verification platform comprises the steps of setting relevant variable values in the FPGA full compiling process, judging an operation mode and executing a setting script before FPGA compiling; step 4.1.2, starting Vivado software, if the FPGA project is not established currently, automatically establishing the FPGA project, otherwise, automatically loading the FPGA project; step 4.13, performing the comprehensive and the time sequence analysis after the comprehensive, outputting a comprehensive result and a time sequence analysis report, and saving the output comprehensive result and the time sequence analysis report by taking the date of the day as a version number; step 4.1.4, executing the back end PR, outputting a result and a report of the back end PR, and saving the output result and the output report of the back end PR by taking the date of the day as a version number; step 4.1.5, downloading the burning file of the FPGA, and performing board-level debugging and verification; and 4.1.6, detecting the verification result of the FPGA, modifying the FPGA configuration file when the verification result of the FPGA has a problem, recompiling the FPGA, modifying the DUT design file if a design error is found, returning to the software simulation verification of the chip design again, and finishing the verification if the verification result of the FPGA passes.
In the efficient multi-mode verification platform and method of the embodiments of the present invention, the FPGA full compilation and system prototype verification process of the FPGA hardware system prototype verification is as follows: analyzing an input instruction, wherein the input instruction comprises setting relevant variable values in the FPGA full compiling process, judging an operation mode and executing a setting script before FPGA compiling; secondly, starting Vivado software, automatically building an FPGA project if the FPGA project is not built currently, and otherwise, automatically loading the FPGA project; thirdly, performing the comprehensive and the time sequence analysis after the comprehensive, outputting a comprehensive result and a time sequence analysis report, and storing the comprehensive result and the time sequence analysis report by taking the date of the day as a version number; fourthly, executing the back end PR, outputting a result and a report of the back end PR, and saving the result and the report of the back end PR by taking the date of the day as a version number; fifthly, downloading a burning file of the FPGA, and performing board-level debugging and verification; and sixthly, detecting the FPGA verification result, modifying the FPGA configuration file if the FPGA verification result has a problem, then re-compiling the FPGA, modifying the DUT design file if the bug on the design is found, then returning to the software simulation verification process of the chip design, and ending the verification if the verification passes.
As shown in fig. 9, the step 4 further includes: performing FPGA manual step compiling: step 4.2.1, the multi-mode verification platform analyzes the input instruction, and the multi-mode verification platform comprises the steps of setting relevant variable values in the FPGA full compiling process, judging an operation mode and executing a setting script before FPGA compiling; step 4.2.2, starting Vivado software, if the FPGA project is not established currently, automatically establishing the FPGA project, otherwise, automatically loading the FPGA project; step 4.2.3, performing FPGA compiling step analyzed by the instruction; step 4.2.4, outputting results and reports after the current compiling step of the FPGA is finished, and saving the output results and reports by taking the date of the day as a version number; and 4.2.5, analyzing the result and the report.
In the efficient multi-mode verification platform and method of the embodiments of the present invention, the manual step-by-step compilation process of the FPGA for prototype verification of the FPGA hardware system is as follows: analyzing an input instruction, wherein the input instruction comprises setting relevant variable values in the FPGA full compiling process, judging an operation mode and executing a setting script before FPGA compiling; secondly, starting Vivado software, automatically building an FPGA project if the FPGA project is not built currently, and otherwise, automatically loading the FPGA project; thirdly, executing FPGA compiling steps analyzed by the instruction; fourthly, the FPGA finishes the current compiling step, outputs a result and a report, and saves the result and the report by taking the date of the day as a version number; and fifthly, analyzing results and reporting.
After the development project is set up, the high-efficiency multi-mode verification platform and the method of the embodiment of the invention use the instruction to create the verification environment architecture of the development project, as shown in fig. 1, fig. 2 and fig. 3, perform the programming design of the DUT in the Verilog directory in fig. 2, and after the programming of the DUT is completed, start the verification of the DUT, and the overall verification flow of the high-efficiency multi-mode verification platform and the method is as shown in fig. 5, and first perform the verification of software simulation, and then perform the prototype verification of the FPGA hardware system. Software simulation verification firstly executes simulation verification of a single testcase, a method adds a new testcase and inputs a simulation instruction according to a figure 6, the high-efficiency multi-mode verification platform analyzes the simulation instruction and comprises the steps of searching for testcase definitions, searching for testcase required files, summarizing simulated compiling macro definitions and compiling instructions, running a setting script before simulation, caching a result detection script when the simulation is finished, establishing a storage directory of simulation results, automatically reading each file and related configuration files of a DUT by the high-efficiency multi-mode verification platform, starting software simulation, automatically running the simulation result detection script after the simulation is finished, checking the simulation results, and reporting files containing simulation log files and running scripts for result data detection, if the simulation finds bugs exist, returning to the DUT directory, modifying chip design files, re-executing the simulation verification of the testcase, and if no bugs exist, another testcase is added and the loop is repeated until all the functions of the chip design are covered. After the software simulation verification is executed at a certain stage, the prototype verification of the FPGA hardware system can be started, the steps are shown in fig. 8 and 9, and fig. 9 is a manual step-by-step compiling flow, which is used for performing the compiling and debugging of the FPGA engineering, the timing sequence repair and the like during the early stage of the FPGA compiling. FIG. 8 is a flow of performing prototype verification of an FPGA hardware system by automatic full compilation, analyzing an input instruction, including setting a variable value related to the FPGA full compilation process, determining an operation mode, executing a setting script before FPGA compilation, starting Vivado software, automatically building an FPGA project if the FPGA project is not currently built, otherwise, automatically loading the FPGA project, executing comprehensive and comprehensive timing analysis, outputting a comprehensive result and a timing analysis report, saving the date of the day as a version number, executing a rear-end PR, outputting a result and a report of the rear-end PR, saving the date of the day as a version number, downloading a burning file of the FPGA, performing board-level debugging and verification, detecting an FPGA verification result, if a problem exists, modifying an FPGA configuration file, then re-performing FPGA compilation, and if the verification passes, ending the verification. If errors exist in the DUT in the prototype verification process of the FPGA hardware system or the later process of chip design, the DUT needs to be returned to a DUT directory, a design file is modified, then regression simulation and simulation verification of a plurality of testcases parallel software shown in FIG. 7 are executed, a testcase list is set, the efficient multi-mode verification platform analyzes a simulation instruction, the definition of each testcase is searched, a file required by each testcase is searched, the compiling macro definition and compiling quality of each testcase simulation are summarized, the set script before each testcase simulation is run, the result detection script when each testcase simulation is finished is cached, each file of the DUT and related configuration files are read, software simulation verification is started, the simulation result detection script is automatically run after each testcase simulation is finished, the simulation result is summarized, a regression simulation report is checked, and whether each testcase simulation is correctly finished or not is included. And under necessary conditions, after the software simulation is finished, the prototype verification process of the FPGA hardware system needs to be carried out again.
The high-efficiency multi-mode verification platform and the method of the invention can automatically create a verification environment framework of a research and development project by inputting instructions, the high-efficiency multi-mode verification platform and the method are compatible with software simulation verification and FPGA hardware system prototype verification, the software simulation verification supports two types of software simulation under the chip design condition and software simulation under the FPGA development condition, supports single verification of one testcase and parallel verification of a plurality of testcases, the verification results are mutually independent and have respective space storage, the FPGA hardware system prototype verification adopts an Xilinx FPGA chip and a Vivado design platform, supports automatic reading and real-time refreshing of design files, can automatically and manually compile in steps, has simple and fast operation commands, automatically stores FPGA compilation results and reports, and stores the work of each day into different versions by taking the date of the day as a version number, the verification efficiency and quality are improved, the verification platform is simple to maintain, and the method can be quickly transplanted to different research and development projects.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (8)
1. An efficient multi-modal authentication platform, comprising:
the system comprises an asic module, a chip module and a control module, wherein the asic module comprises a software simulation platform of chip design and a configuration file;
a config module that includes a global profile for the multimodal authentication platform;
the system comprises an FPga module, wherein the FPga module comprises an FPGA system prototype verification platform and a configuration file.
2. The efficient multimodal authentication platform as recited in claim 1, wherein the asic module comprises:
an analog unit, the analog unit comprising an analog integrated circuit IP model;
a bin unit comprising a common file processing script;
a config unit including DUT.f, DUT _ fpga.f, MODEL.f, TB.f, TESTLIST and configuration files required by software simulation of chip design;
the doc unit is used for storing record files in the chip research and development process;
the lib unit is used for storing a chip design process library and a soft core IP;
the device comprises a modules unit, a monitoring unit and a control unit, wherein the modules unit comprises a peripheral device model and a software simulation monitor which are actually applied by a chip;
the system comprises a sim unit, a software integration unit and a software integration unit, wherein the sim unit is provided with two subdirectory spaces task and run, the task comprises a testcase library, and the run is a simulation result storage space;
a tb unit, which is a test stimulus for chip verification;
a verilog directory comprising the entire chip design file.
3. The efficient multi-modal authentication platform of claim 1, wherein the fpga module comprises:
a design input file including an fpga _ edif unit, and an fpga _ hdl unit;
a mem _ init unit, the mem _ init unit including initialization data of a memory;
the reports unit comprises an FPGA compiling report output storage space;
the result unit comprises an FPGA compiling result output storage space;
a run unit, which is a space for FPGA to execute compilation;
and the tcl unit comprises configuration and script files for the FPGA to execute compiling and system prototype verification.
4. An efficient multimodal authentication method applied to an efficient multimodal authentication platform according to any one of claims 1-3, comprising:
step 1, inputting test excitation into a multi-mode verification platform, and calling library and IP respectively by the multi-mode verification platform to perform software simulation verification;
step 2, finding errors in the software simulation verification process, returning to a DUT directory, and modifying a chip design file;
step 3, no error occurs in the software simulation verification process, and the prototype verification of the FPGA hardware system is executed;
and 4, finding errors in the process of executing the prototype verification of the FPGA hardware system, returning to the DUT directory, modifying the chip design file, and re-performing software simulation verification and the prototype verification of the FPGA hardware system.
5. The efficient multi-modal authentication method of claim 4, wherein the step 1 specifically comprises:
simulation verification of a single testcase is performed:
step 1.1.1, adding a new testcase in the multi-mode verification platform, and inputting a simulation instruction;
step 1.1.2, the multi-mode verification platform analyzes the simulation instruction, and the method comprises the steps of searching for testcase definition, searching for testcase required files, summarizing simulated compiling macro definition and compiling instructions, running a setting script before simulation, caching a result detection script when simulation is finished, and establishing a storage directory of simulation results;
step 1.1.3, reading each file of the DUT and a related configuration file;
step 1.1.4, starting software simulation verification, and automatically running a software simulation verification result detection script after the software simulation verification is finished;
step 1.1.5, checking a software simulation verification result, wherein the software simulation verification result comprises a simulation information recording file and a report file for running a script to detect result data;
and step 1.1.6, finding that errors exist in the software simulation verification process, returning to a DUT directory, modifying a chip design file, re-executing the software simulation verification of the current testcase, adding a new testcase if no errors exist in the software simulation verification process, and circulating the operation until all functions of the chip design are covered.
6. An efficient multi-modal authentication method as recited in claim 4, wherein the step 1 further comprises:
and (3) performing parallel simulation verification of a plurality of testcases during regression simulation:
step 1.2.1, setting a testcase list, and adding the testcase list to the multi-mode verification platform;
step 1.2.2, the multi-mode verification platform analyzes the simulation instruction, and the method comprises the steps of searching for the definition of each testcase, searching for the file required by each testcase, summarizing the compiling macro definition and the compiling quality of each testcase simulation, running a setting script before each testcase simulation and caching a result detection script when each testcase simulation is finished;
step 1.2.3, reading each file of the DUT and a related configuration file;
step 1.2.4, software simulation verification is started, and a software simulation verification result detection script is automatically run after the simulation verification of each testcase software is finished;
step 1.2.5, summarizing software simulation verification results;
and step 1.2.6, checking a regression simulation report, wherein the regression simulation report comprises whether the simulation verification of each testcase software is finished correctly and the code coverage rate of the simulation.
7. The efficient multi-modal authentication method of claim 4, wherein the step 4 specifically comprises:
performing FPGA full compilation and system prototype verification:
step 4.1.1, the multi-mode verification platform analyzes the input instruction, and the multi-mode verification platform comprises the steps of setting relevant variable values in the FPGA full compiling process, judging an operation mode and executing a setting script before FPGA compiling;
step 4.1.2, starting Vivado software, if the FPGA project is not established currently, automatically establishing the FPGA project, otherwise, automatically loading the FPGA project;
step 4.13, performing the comprehensive and the time sequence analysis after the comprehensive, outputting a comprehensive result and a time sequence analysis report, and saving the output comprehensive result and the time sequence analysis report by taking the date of the day as a version number;
step 4.1.4, executing the back end PR, outputting a result and a report of the back end PR, and saving the output result and the output report of the back end PR by taking the date of the day as a version number;
step 4.1.5, downloading the burning file of the FPGA, and performing board-level debugging and verification;
and 4.1.6, detecting the verification result of the FPGA, modifying the FPGA configuration file when the verification result of the FPGA has a problem, recompiling the FPGA, modifying the DUT design file if a design error is found, returning to the software simulation verification of the chip design again, and finishing the verification if the verification result of the FPGA passes.
8. An efficient multi-modal authentication method as recited in claim 4, wherein the step 4 further comprises:
performing FPGA manual step compiling:
step 4.2.1, the multi-mode verification platform analyzes the input instruction, and the multi-mode verification platform comprises the steps of setting relevant variable values in the FPGA full compiling process, judging an operation mode and executing a setting script before FPGA compiling;
step 4.2.2, starting Vivado software, if the FPGA project is not established currently, automatically establishing the FPGA project, otherwise, automatically loading the FPGA project;
step 4.2.3, performing FPGA compiling step analyzed by the instruction;
step 4.2.4, outputting results and reports after the current compiling step of the FPGA is finished, and saving the output results and reports by taking the date of the day as a version number;
and 4.2.5, analyzing the result and the report.
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