JP2017116484A - Gate driver, data selector and pressure sensitive sensor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a pressure sensitive sensor that is high in a design freedom degree at low costs without restricting flexibility even if the number of wiring formed in a matrix form is many.SOLUTION: A gate driver comprises a plurality of stages. In each stage, the gate driver includes: a first thin film transistor in which a gate to be input to the stage and one of a source or drain are diode-connected; a second thin film transistor in which a charge node between other of the source or drain of the first thin film transistor and an output of the stage is a gate input, and between a clock input and the output of the stage is connected between the drain and source; a third thin film transistor in which between the charge node and a power source is connected between the drain and source; and a fourth thin film transistor in which between the power source and the output of the stage is connected between the drain and source, and the gate is connected to the output of the stage.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a pressure-sensitive sensor that measures pressure.

  A pressure-sensitive sensor is known in which a plurality of row / column electrodes coated with a conductive layer intersect each other (passive matrix structure) between two flexible film substrates. (For example, refer to Patent Document 1). In this type of pressure-sensitive sensor, when pressure is applied, conductive layers arranged in an intersecting manner come into contact with each other, thereby changing the resistance value. Then, by detecting this change in resistance value, the in-plane distribution of the applied pressure can be measured.

  In recent years, thin film transistors (print TFTs) manufactured by a printing process have attracted attention (see, for example, Non-Patent Document 1). Here, the printing process refers to a method for producing a semiconductor element without using a vacuum process by coating or a printing method (inkjet, letterpress, intaglio, planographic, stencil, etc.). In the electronics field, which frequently uses vacuum processes, the printing process is promising as an innovative technology for production systems. In addition, it has been noticed that the printed TFT has a large area, low cost, low environmental load, low temperature formation, and flexibility.

JP 2012-57992 A

Monthly OPTRONICS, May 2011, Volume 30, Volume 353, "Special Feature: Flexible Organic Electronics for Realizing Next Generation Displays"

  In the conventional pressure-sensitive sensor exemplified in Patent Document 1, the drive circuit IC and the detection circuit IC cannot be mounted on the film for reasons of cost and flexibility. Therefore, it was necessary to draw all the row and column electrode wirings formed in a matrix form to the outside of the film and connect them to external circuits (with drive and detection functions), so when designing a sensor with a large number of wires, connection terminals and wiring layout As a result, there is a problem that the space for the sensor becomes enormous and the degree of freedom in sensor design is significantly reduced, which hinders the expansion of applications.

  The present invention has been made in view of the above problems. Even when the number of wirings formed in a matrix is large, a pressure-sensitive sensor that does not limit flexibility and has a high degree of design freedom can be obtained at low cost. The purpose is to provide in.

  In the present invention, the following features are provided alone or in combination as appropriate.

  One aspect of the present invention for achieving the above object includes a first thin film transistor including a plurality of stages, and in each stage, a gate to which an input to the stage is made and one of a source and a drain are diode-connected, A charge node between the other of the source or drain of the first thin film transistor and the output of the stage as a gate input, and a second thin film transistor for connecting the clock input and the output of the stage between the drain and source; A third thin film transistor connecting the voltage source between the drain and source; and a fourth thin film transistor connecting the voltage source and the output of the stage between the drain and source and having a gate connected to the output of the stage. It has a gate driver.

  According to another aspect of the present invention, a plurality of pressure-sensitive sensor cells each having a pressure-sensitive variable resistor and a fifth thin film transistor connected to the pressure-sensitive variable resistor are arranged in a matrix, and gate electrodes of at least some of the transistors are connected to each other. A pressure-sensitive sensor comprising a pressure-sensitive sensor cell array having an active matrix structure including a plurality of gate lines, and the above-described gate driver having a stage connected to each of the gate lines.

  Another aspect of the present invention includes a first thin film transistor including a plurality of stages, each of which has a gate connected to the stage and one of a source and a drain, and a source of the first thin film transistor. A second thin film transistor having a charge node between the other of the drains and the first output of the stage as a gate input and connecting between the clock input and the first output of the stage between the drain and the source; and the charge node and the voltage A third thin film transistor that connects the source and the drain to the source; and a fourth thin film transistor that connects the voltage source and the first output of the stage between the drain and the source and has a gate connected to the first output of the stage. Connection between the drain and source between the thin film transistor and the data line and the second output with the first output as the gate input That a fifth and a thin film transistor, a data selector.

  In another aspect of the present invention, a plurality of pressure-sensitive sensor cells each having a pressure-sensitive variable resistor and a transistor connected to the pressure-sensitive variable resistor are arranged in a matrix, and at least some of the source or drain electrodes of the transistors are connected to each other. A pressure-sensitive sensor cell array including a plurality of data lines and a data selector having the stage connected to each of the data lines.

In addition, the pressure sensor may include both the gate driver and the data selector described above.

  According to the present invention, the number of lead-out wirings to the outside can be reduced, and the space for connection terminals and wiring layout can be reduced. Therefore, it is easy to increase the number of gate lines and data lines, and the pressure sensitivity is high in design freedom. A sensor can be provided.

  In addition, since part of the drive circuit IC and the detection circuit IC that limit the flexibility of the pressure sensor can be omitted, the pressure sensor can be provided in a more flexible form.

  In addition, since a part of the drive circuit IC and the detection circuit IC that tend to be relatively expensive can be omitted, the pressure-sensitive sensor can be manufactured at low cost.

The circuit block diagram of the pressure sensor which concerns on embodiment of this invention Explanatory drawing of the layer structure of the pressure-sensitive sensor cell which concerns on embodiment of this invention Explanatory drawing of reduction of lead wiring according to an embodiment of the present invention Circuit explanatory diagram for one stage of gate driver according to an embodiment of the present invention The figure explaining the phase relation of input signal CK1 ± Circuit explanatory diagram for one stage of data selector according to an embodiment of the present invention The figure explaining the phase relationship of input signal CK2 ± The figure explaining the timing of input signals CK1 ± and CK2 ±

  A pressure-sensitive sensor 100 according to an embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a diagram illustrating a circuit configuration of the pressure-sensitive sensor 100. The pressure sensor 100 includes a pressure sensor cell array 1, a gate driver 2, and a data selector 3. An electrostatic protection element 4 which is a floating gate TFT type protection element is provided in each of the gate driver 2 and the data selector 3. All nodes constituting the sensor circuit are connected to the COM electrode via the TFT.

  The pressure-sensitive sensor cell array 1 is composed of pressure-sensitive sensor cells arranged in a matrix, and each pressure-sensitive sensor cell is a cell TFT 6 which is a p-type printed TFT having a switching function connected to the pressure-sensitive variable resistor 5. With.

  FIG. 2 is a diagram for explaining the layer structure of pressure-sensitive sensor cells constituting the pressure-sensitive sensor cell array 1. This pressure-sensitive sensor cell includes two flexible film base materials 7 and 17, a gate electrode wiring 8, a gate insulating layer 9, a source / drain electrode wiring 10, a semiconductor layer 11, and a semiconductor protective layer. 12, an interlayer insulating layer 13, a cell electrode layer 14, a pressure-sensitive conductive layer 15, and a common electrode (COM electrode) 16. The gate electrode wiring 8, the gate insulating layer 9, the source / drain electrode wiring 10, the semiconductor layer 11, and the semiconductor protective layer 12 constitute a cell TFT 6, a cell electrode layer 14, a pressure-sensitive conductive layer 15, The common electrode (COM electrode) 16 constitutes the pressure sensitive variable resistor 5. The structure of the pressure sensitive sensor cell array 1 is formed using a printing process. All the other TFTs constituting the pressure sensor 100 are also composed of the gate electrode wiring 8, the gate insulating layer 9, the source / drain electrode wiring 10, the semiconductor layer 11, and the semiconductor protective layer 12. The gate electrode wiring 8 of the cell TFT 6 constituting each pressure sensitive sensor cell arranged in the same row of the pressure sensitive sensor cell array 1 is connected to the same gate line. Further, the source / drain electrode wiring 10 which is not connected to the pressure-sensitive variable resistor 5 of the cell TFT 6 constituting each pressure-sensitive sensor cell arranged in the same column is connected to the same data line.

  FIG. 3 is a diagram for explaining the concept of lead-out wiring reduction according to the present embodiment. In the conventional wiring lead configuration shown on the left of FIG. 3, in the case of m rows and n columns, it is necessary to draw m + n wires to the outside.

  In the pressure-sensitive sensor 100 according to the present embodiment shown on the right side of FIG. 3, the number of lead-out wires is nine in the case of the m-row and n-column matrix (three gate drivers 2 and four data selectors 3 are shared). 2 wires). Therefore, the pressure-sensitive sensor 100 becomes more advantageous in reducing the lead wiring as the number of m and n increases.

  The gate driver 2 has a function of sequentially applying a scanning pulse voltage to each gate line of the pressure-sensitive sensor cell array 1 and sequentially selecting the cell TFTs 6 connected to each gate line. The selected cell TFT 6 becomes conductive, and an output current flows from the COM electrode to the data line connected via the pressure-sensitive variable resistor 5 and the cell TFT 6. The pressure sensor 100 measures the pressure distribution by detecting the output current.

  FIG. 4 is a diagram for explaining the configuration and operation of the stage 40 that is a circuit for one stage of the gate driver 2. As shown on the left of FIG. 4, each stage 40 of the gate driver 2 includes an input TFT 18, an output TFT 19, a reset TFT 20, a shunt TFT 21, and holding capacitors 22 and 23. The storage capacitors 22 and 23 are formed using the gate electrode wiring 8, the gate insulating layer 9, and the source / drain electrode wiring 10. Each TFT and the storage capacitor are connected by forming a through hole in the gate insulating layer 9 or the interlayer insulating layer 13 and using the cell electrode layer 14.

  As shown on the right side of FIG. 4, the clock signal CK1 is connected to the output TFT 19 and the high-level constant voltage source VH is connected to the reset TFT 20 in each stage 40 of the gate driver 2, and the input signal at the timing when CK1 is at the high level. When a low level pulse of IN1 is input to the input TFT 18, a low level pulse signal OUT1 delayed from the IN1 by a half cycle of CK1 is output from the output TFT19. Immediately after outputting the OUT1 pulse, it is necessary to input the RST1 pulse to the reset TFT 20 and reset the low level potential held at the node NA1 to the high level.

  The shunt TFT 21 functions to discharge charges leaking from CK1 to OUT1 through the output TFT 19 in the non-conductive state to the high level constant voltage source VH. The shunt TFT 21 is desirably designed to be smaller in size (channel width / channel length) to about 1/10 or less than the output TFT 19.

  The stages 40 of the gate driver 2 shown in FIG. 4 are connected in series as shown in FIG. 1 (the adjacent front stage OUT1 and the rear stage IN1 are connected, the rear stage OUT1 is also connected to the front stage RST1, and the OUT1 of each stage 40 is connected. 5 is connected to each gate line), the clock signals CK1 + and CK1- whose phases are inverted are connected to the odd and even stages, respectively, and the trigger pulse signal is connected to the first stage IN1 and the final stage RST1. A circuit that sequentially applies scanning pulses to each gate line by inputting ST1 (the pulse period needs to be adjusted according to the total number of stages so that the pulse timings of the initial stage IN1 and the final stage RST1 are the same). realizable.

  The gate driver 2 can be formed using a printing process. In a printing process in which wet film formation is a principle, patterning restrictions on fine shapes are severe compared to other semiconductor manufacturing processes using a vacuum process and photolithography. Therefore, it can be said that it is relatively unsuitable to manufacture a circuit in which a large number of TFTs are connected in a complicated manner. In view of this situation, the stage 40 of the gate driver 2 shown in FIG. 4 has a simple circuit configuration in which holding capacitors 22 and 23 are added to the minimum necessary components (input TFT 18, output TFT 19, reset TFT 20, shunt TFT 21). It is said. Further, since the circuit configuration is simple, it is excellent in production yield and can be manufactured at low cost by a printing process.

  The data selector 3 has a function of acquiring outputs sequentially from each data line of the pressure-sensitive sensor cell array 1. An output current flows from the COM electrode to the external detection circuit via the pressure-sensitive variable resistor 5, the cell TFT 6 selected by the gate driver 2, the data line selected by the data selector 3, and the data selector 3. The pressure sensor 100 measures the pressure distribution by detecting the output current.

  FIG. 6 is a diagram for explaining the configuration and operation of a stage 50 which is a circuit for one stage of the data selector 3 according to the present invention. As shown on the left of FIG. 6, each stage 50 of the data selector 3 includes an input TFT 24, a transfer TFT 25, a reset TFT 26, a shunt TFT 27, an output TFT 28, and holding capacitors 29 and 30. The storage capacitors 29 and 30 are formed by using the gate electrode wiring 8, the gate insulating layer 9, and the source / drain electrode wiring 10. Each TFT and the storage capacitor are connected by forming a through hole in the gate insulating layer 9 or the interlayer insulating layer 13 and using the cell electrode layer 14.

  As shown on the right side of FIG. 6, the clock signal CK2 is connected to the transfer TFT 25 and the high-level constant voltage source VH is connected to the reset TFT 26 at each stage 50 of the data selector 3, and the input signal is input at the timing when CK2 is at the high level. When a low level pulse of IN2 is input to the input TFT 24, a low level pulse signal TRN delayed from the IN2 by a half cycle of CK2 is output from the transfer TFT 25. Immediately after outputting the TRN pulse, it is necessary to input the RST2 pulse to the reset TFT 26 and reset the low level potential held at the node NA2 to the high level.

  The shunt TFT 27 functions to discharge the charge leaking from CK2 to TRN through the transfer TFT 25 in the non-conductive state to the high level constant voltage source VH. The shunt TFT 27 is desirably designed to be smaller than the transfer TFT 25 in size (channel width / channel length) by about 1/10 or less.

  The output TFT 28 connected to the data line is turned on by the TRN pulse and functions to pass an output current from the data line to the external detection circuit.

  The stages 50 of the data selector 3 shown in FIG. 6 are connected in series as shown in FIG. 1 (the adjacent front stage TRN and rear stage IN2 are connected, the rear stage TRN is also connected to the front stage RST2, and the data of each stage 50 is The clock signals CK2 + and CK2- whose phases shown in FIG. 7 are inverted are connected to each of the odd and even stages, and the trigger pulse signal ST2 is connected to the first stage IN2 and the final stage RST2. (It is necessary to adjust the pulse period according to the total number of stages so that the pulse timing of the initial stage IN2 and the final stage RST2 is the same), and a circuit that sequentially obtains output from each data line is realized it can.

  The data selector 3 can be formed using a printing process. In a printing process in which wet film formation is a principle, patterning restrictions on fine shapes are severe compared to other semiconductor manufacturing processes using a vacuum process and photolithography. Therefore, it can be said that it is relatively unsuitable to manufacture a circuit in which a large number of TFTs are connected in a complicated manner. In view of this situation, the stage 50 of the data selector 3 shown in FIG. 6 is a simple configuration in which holding capacitors 29 and 30 are added to the minimum necessary components (input TFT 24, transfer TFT 25, reset TFT 26, shunt TFT 27, output TFT 28). Circuit configuration. Further, since the circuit configuration is simple, it is excellent in production yield and can be manufactured at low cost by a printing process.

  FIG. 8 shows the timing of the input signals CK1 ± and CK2 ±.

  As described above, according to the present invention, the number of lead-out wirings to the outside can be reduced, and the space for connection terminals and wiring layout can be reduced. Therefore, the number of gate lines and data lines can be easily increased. A pressure-sensitive sensor with a high degree of design freedom can be provided.

  In addition, since part of the drive circuit IC and the detection circuit IC that limit the flexibility of the pressure sensor can be omitted, the pressure sensor can be provided in a more flexible form.

  In addition, since a part of the drive circuit IC and the detection circuit IC that tend to be relatively expensive can be omitted, the pressure-sensitive sensor can be manufactured at low cost.

  The present invention can be expected to be applied to fields such as electronics, robotics, and mechanical engineering.

1 Pressure-sensitive sensor cell array 2 Gate driver 3 Data selector 4 Static electricity protection element (floating gate TFT type)
5 Pressure sensitive variable resistance 6 Cell TFT
7 Lower film substrate 8 Gate electrode wiring 9 Gate insulating layer 10 Source / drain electrode wiring 11 Semiconductor layer 12 Semiconductor protective layer 13 Interlayer insulating layer 14 Cell electrode layer 15 Pressure sensitive conductive layer 16 Common electrode (COM electrode)
17 Upper film base 18 Input TFT
19 Output TFT
20 Reset TFT
21 Shunt TFT
22 Retention capacity 23 Retention capacity 24 Input TFT
25 Transfer TFT
26 Reset TFT
27 Shunt TFT
28 output TFT
29 Retention Capacity 30 Retention Capacity 40 Gate Driver Stage 50 Data Selector Stage 100 Pressure Sensor

Claims (5)

With multiple stages, each stage
A first thin film transistor in which a gate to be input to the stage and one of a source and a drain are diode-connected;
A second thin film transistor having a charge node between the other of the source or drain of the first thin film transistor and the output of the stage as a gate input and connecting a clock input and the output of the stage between the drain and source;
A third thin film transistor connecting the charge node and the voltage source between the drain and the source;
A gate driver comprising: a fourth thin film transistor having a drain connected to the output between the voltage source and the output of the stage, and a gate connected to the output of the stage. An active device comprising a plurality of pressure-sensitive sensor cells each having a pressure-sensitive variable resistor and a fifth thin film transistor connected to the pressure-sensitive variable resistor, and a plurality of gate lines connecting at least some of the gate electrodes of the transistors. A pressure-sensitive sensor cell array having a matrix structure;
A pressure sensor comprising: the stage according to claim 1, wherein the stage is connected to each of the gate lines. With multiple stages, each stage
A first thin film transistor in which a gate to be input to the stage and one of a source and a drain are diode-connected;
A charge node between the other one of the source and drain of the first thin film transistor and the first output of the stage is used as a gate input, and a clock input and the first output of the stage are connected between the drain and source. A second thin film transistor;
A third thin film transistor connecting the charge node and the voltage source between the drain and the source;
A fourth thin film transistor having a drain-source connection between the voltage source and the first output of the stage and a gate connected to the first output of the stage;
A data selector, comprising: a fifth thin film transistor for connecting the data line and the second output between the drain and the source using the first output as a gate input. A plurality of pressure-sensitive sensor cells each having a pressure-sensitive variable resistor and a transistor connected to the pressure-sensitive variable resistor are arranged in a matrix, and a pressure-sensitive device includes a plurality of data lines connecting at least some of the source or drain electrodes of the transistors A sensor cell array;
A pressure sensor comprising: the data selector according to claim 3, wherein the stage is connected to each of the data lines. The pressure-sensitive sensor cell array includes a plurality of data lines that connect source or drain electrodes of at least some of the thin film transistors,
Including a plurality of stages respectively connected to each of the data lines,
A sixth thin film transistor in which a gate to be input to the stage and one of a source and a drain are diode-connected;
A charging node between the other of the source and drain of the sixth thin film transistor and the first output of the stage is used as a gate input, and a clock input and the first output of the stage are connected between the drain and source. A seventh thin film transistor;
An eighth thin film transistor connecting the charge node and the voltage source between the drain and source;
A ninth thin film transistor having a drain-source connection between the voltage source and the first output of the stage and a gate connected to the first output of the stage;
The pressure-sensitive sensor according to claim 2, further comprising a data selector having a tenth thin film transistor that connects the data line and the second output between drain and source using the first output as a gate input.

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