JP2009231609A - Production method of semiconductor light-emitting element - Google Patents

Production method of semiconductor light-emitting element Download PDF

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JP2009231609A
JP2009231609A JP2008076395A JP2008076395A JP2009231609A JP 2009231609 A JP2009231609 A JP 2009231609A JP 2008076395 A JP2008076395 A JP 2008076395A JP 2008076395 A JP2008076395 A JP 2008076395A JP 2009231609 A JP2009231609 A JP 2009231609A
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Fumitake Nakanishi
文毅 中西
Yusuke Yoshizumi
祐介 善積
Yohei Shioya
陽平 塩谷
Masanori Ueno
昌紀 上野
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Sumitomo Electric Industries Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a production method of a semiconductor light-emitting element, which can enhance the proportion of incorporated In in a step of growing an active layer containing In on a GaN substrate, having a semipolar plane as main surface. <P>SOLUTION: In a step of growing an InGaN well layer 5a on a GaN substrate 15, having a main surface where an off-angle from the c-plane is included in a range of 20° or larger and 28° or smaller; growth temperature is in a range of 600°C or higher and 700°C or lower; mol flow ratio (Q<SB>V</SB>/Q<SB>In</SB>) between an N raw material gas flow Q<SB>V</SB>and In raw material gas flow Q<SB>In</SB>is a value included in a range of 9,000 or larger and 30,000 or smaller; a growth speed of the well layer 5a is set as a speed, included in the range of 0.01 μm/hour or more and 0.1 μm/hour or less, and the thickness for each of the well layers 5a is set at 10 nm or smaller. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、半導体発光素子の製造方法に関するものである。   The present invention relates to a method for manufacturing a semiconductor light emitting device.

近年、III族窒化物系の半導体発光素子として、窒化ガリウム(GaN)基板上に、インジウム(In)を含む活性層が形成されたものがある。このような半導体発光素子において、c面すなわち(0001)面を主面とするGaN基板を用いた場合、Inを含む活性層に比較的大きな歪みが生じてしまう。このため、ピエゾ電界による量子シュタルク効果が生じ電子および正孔が空間分離されて発光効率が低下するといった問題や、或いは電流注入量に応じてピエゾ電界がスクリーニングされ、発光波長が短波長側にシフトするといった問題が生じる。   In recent years, there is a group III nitride semiconductor light emitting device in which an active layer containing indium (In) is formed on a gallium nitride (GaN) substrate. In such a semiconductor light emitting device, when a GaN substrate having a c-plane, that is, a (0001) plane as a main surface is used, a relatively large strain occurs in the active layer containing In. For this reason, the quantum Stark effect due to the piezo electric field is generated, and the emission efficiency is lowered due to the spatial separation of electrons and holes, or the piezo electric field is screened according to the amount of current injection, and the emission wavelength is shifted to the short wavelength side. Problem arises.

そこで、このような半導体発光素子を作製する際には、ピエゾ電界を抑えるために半極性面を主面とするGaN基板が用いられる。例えば、非特許文献1には、半極性面を主面とするGaN基板を用いてLEDを作製する技術が開示されている。この文献では、(11−22)面を主面とするGaN基板上にInGaN活性層を含むLED構造を形成し、緑色のEL(ElectroLuminescence)を実現している。
Mitsuru FUNATO etal., ”Blue, Green, and Amber InGaN/GaN Light-Emitting Diodes on Semipolar {11-22}GaN Bulk Substrates ”, Japanese Journal of Applied Physics Vol.45, No.26, pp.L659-L662,(2006)
Therefore, when manufacturing such a semiconductor light emitting device, a GaN substrate having a semipolar surface as a main surface is used in order to suppress a piezoelectric field. For example, Non-Patent Document 1 discloses a technique for manufacturing an LED using a GaN substrate having a semipolar plane as a main surface. In this document, an LED structure including an InGaN active layer is formed on a GaN substrate having a (11-22) plane as a main surface, and green EL (ElectroLuminescence) is realized.
Mitsuru FUNATO etal., “Blue, Green, and Amber InGaN / GaN Light-Emitting Diodes on Semipolar {11-22} GaN Bulk Substrates”, Japanese Journal of Applied Physics Vol.45, No.26, pp.L659-L662, (2006)

しかしながら、Inを含む活性層がGaN基板上に形成された半導体発光素子を実用化しようとした場合には、次の問題が生じる。すなわち、半極性面を主面とするGaN基板上にInを含む活性層を成長させた場合、c面を主面とするGaN基板上にInを含む活性層を成長させた場合と比較して、活性層においてInが取り込まれる割合が小さくなる。例えば、c面GaN基板上にInGaN層を成長させた場合にInの組成比を20%程度にできる成長条件でもってオフ角18°のGaN基板上にInGaN層を成長させると、Inの組成比は8.3%程度に低下する。更にオフ角を増し、同条件でもってオフ角28°のGaN基板上にInGaN層を成長させると、Inの組成比は5.8%程度まで大きく低下する。したがって、緑色の発光波長を得たいと考えても青紫色の発光波長しか得られないといったように、所望の発光波長を有する半導体発光素子を安定的に得ることが困難となる。   However, when a semiconductor light emitting device in which an active layer containing In is formed on a GaN substrate is to be put into practical use, the following problem occurs. That is, when an active layer containing In is grown on a GaN substrate whose main surface is a semipolar plane, compared to a case where an active layer containing In is grown on a GaN substrate whose main surface is a c-plane The proportion of In taken into the active layer is reduced. For example, when an InGaN layer is grown on a GaN substrate having an off angle of 18 ° under a growth condition that allows the In composition ratio to be about 20% when an InGaN layer is grown on a c-plane GaN substrate, the In composition ratio Decreases to about 8.3%. When the off angle is further increased and an InGaN layer is grown on a GaN substrate having an off angle of 28 ° under the same conditions, the In composition ratio is greatly reduced to about 5.8%. Therefore, it is difficult to stably obtain a semiconductor light emitting device having a desired light emission wavelength such that even if it is desired to obtain a green light emission wavelength, only a blue-violet light emission wavelength can be obtained.

本発明は、上記した問題点を鑑みてなされたものであり、半極性面を主面とするGaN基板上にInを含む活性層を成長させる際に、Inが取り込まれる割合を高めることができる半導体発光素子の製造方法を提供することを目的とする。   The present invention has been made in view of the above-described problems, and can increase the proportion of In taken in when an active layer containing In is grown on a GaN substrate having a semipolar plane as a main surface. An object of the present invention is to provide a method for manufacturing a semiconductor light emitting device.

上記した課題を解決するために、本発明による半導体発光素子の製造方法は、インジウムを含む一又は複数のIII族窒化物半導体層を有する活性層を窒化ガリウム基板上に備える半導体発光素子の製造方法であって、(0001)面からのオフ角が20°以上28°以下の範囲に含まれる主面を有する窒化ガリウム基板上にIII族窒化物半導体層を成長させる工程を備え、工程における成長温度が600℃以上700℃以下の範囲に含まれ、工程におけるV族元素の原料ガスの流量QV[mol/分]とインジウムの原料ガスの流量QIn[mol/分]とのモル流量比(QV/QIn)が9000以上30000以下の範囲に含まれ、工程におけるIII族窒化物半導体層の成長速度が0.01[μm/時]以上0.1[μm/時]以下の範囲に含まれ、III族窒化物半導体層の一層毎の厚さが10nm以下であることを特徴とする。 In order to solve the above problems, a method for manufacturing a semiconductor light emitting device according to the present invention includes a method for manufacturing a semiconductor light emitting device including an active layer having one or more group III nitride semiconductor layers containing indium on a gallium nitride substrate. And a step of growing a group III nitride semiconductor layer on a gallium nitride substrate having a main surface whose off-angle from the (0001) plane is in the range of 20 ° to 28 °, and the growth temperature in the step Is included in the range of 600 ° C. or more and 700 ° C. or less, and the molar flow rate ratio between the flow rate Q V [mol / min] of the group V element source gas and the indium source gas flow rate Q In [mol / min] in the process ( Q V / Q In ) is included in the range of 9000 to 30000, and the growth rate of the group III nitride semiconductor layer in the process is in the range of 0.01 [μm / hour] to 0.1 [μm / hour]. Included, The thickness of each group III nitride semiconductor layer is 10 nm or less.

前述したように、Inを含むIII族窒化物半導体層を半極性面を主面とするGaN基板上に成長させる際、c面上に成長させる場合と比較してInが取り込まれる割合が小さくなってしまう。そこで、本発明者は、Inの原料ガスの供給量を増やすことを考えた。しかし、従来の成長条件を維持したままIn原料ガスの供給量のみ増えると、当該III族窒化物半導体層の結晶性が低下してしまう。この問題に対し、III族窒化物半導体層の成長速度を下げることが解決方法の一つとして挙げられるが、成長速度を下げるとInの離脱が生じて結果的にInの取り込み割合を十分に増やすことができない。   As described above, when a group III nitride semiconductor layer containing In is grown on a GaN substrate having a semipolar plane as a main surface, the proportion of In taken in is smaller than when grown on a c-plane. End up. Therefore, the present inventor considered increasing the supply amount of the In source gas. However, if only the supply amount of the In source gas is increased while maintaining the conventional growth conditions, the crystallinity of the group III nitride semiconductor layer is lowered. One way to solve this problem is to reduce the growth rate of the group III nitride semiconductor layer. However, if the growth rate is reduced, the separation of In occurs, resulting in a sufficiently increased In incorporation rate. I can't.

そこで、本発明者は、半極性基板でも特にc面からのオフ角が20°以上28°以下の範囲に含まれる主面を有するGaN基板を用い、従来の成長条件と比べてIII族窒化物半導体層の成長温度をより低くすることでInの付着率を高めつつ、成長速度も併せて低くすることで、Inの取り込み割合を増加させることに成功した。すなわち、上記した半導体発光素子の製造方法によれば、上記したオフ角を有するGaN基板上にIII族窒化物半導体層を成長させる際に、成長温度を600℃以上700℃以下の範囲とし、V族元素(例えば窒素)の原料ガスの流量QV[mol/分]とインジウムの原料ガスの流量QIn[mol/分]とのモル流量比(QV/QIn)を9000以上30000以下の範囲とし、III族窒化物半導体層の成長速度を0.01[μm/時]以上0.1[μm/時]以下の範囲とすることにより、良好な結晶性を維持したままInの取り込み割合を高めることができる。 Therefore, the present inventor has used a GaN substrate having a main surface that is included in the range of an off angle from the c-plane of 20 ° or more and 28 ° or less even in the case of a semipolar substrate. We succeeded in increasing the In incorporation rate by lowering the growth rate while lowering the growth rate while lowering the growth temperature while lowering the growth temperature of the semiconductor layer. That is, according to the method for manufacturing a semiconductor light emitting device described above, when the group III nitride semiconductor layer is grown on the GaN substrate having the above-described off angle, the growth temperature is set in the range of 600 ° C. to 700 ° C. The molar flow rate ratio (Q V / Q In ) of the group element (eg, nitrogen) source gas flow rate Q V [mol / min] and the indium source gas flow rate Q In [mol / min] is 9000 to 30000 And the growth rate of the group III nitride semiconductor layer is in the range of 0.01 [μm / hour] to 0.1 [μm / hour], and the In incorporation ratio while maintaining good crystallinity. Can be increased.

また、このような成長条件ではInのドロップレットが生じるおそれがあるが、当該III族窒化物半導体層の一層毎の厚さが10nm以下であれば、ドロップレットが生じる前に成長を完了させることができる。   In addition, there is a possibility that In droplets are generated under such growth conditions, but if the thickness of each layer of the group III nitride semiconductor layer is 10 nm or less, the growth must be completed before the droplets are generated. Can do.

本発明による半導体発光素子の製造方法によれば、半極性面を主面とするGaN基板上にInを含む活性層を成長させる際に、Inが取り込まれる割合を高めることができる。   According to the method for manufacturing a semiconductor light emitting device according to the present invention, when an active layer containing In is grown on a GaN substrate having a semipolar plane as a main surface, the proportion of In taken in can be increased.

以下、添付図面を参照しながら本発明による半導体発光素子の製造方法の実施の形態を詳細に説明する。なお、図面の説明において同一の要素には同一の符号を付し、重複する説明を省略する。   Hereinafter, embodiments of a method for manufacturing a semiconductor light emitting device according to the present invention will be described in detail with reference to the accompanying drawings. In the description of the drawings, the same elements are denoted by the same reference numerals, and redundant description is omitted.

図1は、本実施の形態に係る半導体発光素子の製造方法によって製造される半導体発光素子の一例として、半導体発光素子1の構成を概略的に示す側断面図である。半導体発光素子1としては、例えば面発光の発光ダイオードがある。半導体発光素子1は、n型窒化ガリウム系半導体層3と、Inを含む一又は複数のIII族窒化物半導体層を有する活性層5と、p型AlGaN半導体層7と、p型窒化ガリウム系半導体層9と、電極11とを備えている。活性層5は、n型窒化ガリウム系半導体層3上に設けられている。p型AlGaN層7は、活性層5上に設けられている。p型窒化ガリウム系半導体層9は、p型AlGaN層7上に設けられている。電極11は、p型窒化ガリウム系半導体層9に接触しており、例えばアノード電極である。この接触は、好ましくはオーミック接触である。   FIG. 1 is a side sectional view schematically showing a configuration of a semiconductor light emitting device 1 as an example of a semiconductor light emitting device manufactured by the method for manufacturing a semiconductor light emitting device according to the present embodiment. As the semiconductor light emitting element 1, for example, there is a surface emitting light emitting diode. The semiconductor light emitting device 1 includes an n-type gallium nitride semiconductor layer 3, an active layer 5 having one or more group III nitride semiconductor layers containing In, a p-type AlGaN semiconductor layer 7, and a p-type gallium nitride semiconductor. A layer 9 and an electrode 11 are provided. The active layer 5 is provided on the n-type gallium nitride based semiconductor layer 3. The p-type AlGaN layer 7 is provided on the active layer 5. The p-type gallium nitride based semiconductor layer 9 is provided on the p-type AlGaN layer 7. The electrode 11 is in contact with the p-type gallium nitride semiconductor layer 9 and is, for example, an anode electrode. This contact is preferably an ohmic contact.

n型窒化ガリウム系半導体層3は、下部クラッド層として機能する。n型窒化ガリウム系半導体層3の一例としては、厚さ2000[nm]のn型GaN半導体層が好適である。また、p型AlGaN半導体層7は、活性層5からの電子リークを低減して発光効率を高めるための電子ブロック層として機能する。p型AlGaN半導体層7の厚さは、例えば20[nm]である。また、p型窒化ガリウム系半導体層9は、電極11と電気的に導通するためのコンタクト層として機能する。p型窒化ガリウム系半導体層9の一例としては、厚さ50[nm]のp型GaN半導体層が好適である。   The n-type gallium nitride based semiconductor layer 3 functions as a lower cladding layer. As an example of the n-type gallium nitride based semiconductor layer 3, an n-type GaN semiconductor layer having a thickness of 2000 [nm] is suitable. The p-type AlGaN semiconductor layer 7 functions as an electron block layer for reducing electron leakage from the active layer 5 and increasing luminous efficiency. The thickness of the p-type AlGaN semiconductor layer 7 is, for example, 20 [nm]. The p-type gallium nitride based semiconductor layer 9 functions as a contact layer for electrical conduction with the electrode 11. As an example of the p-type gallium nitride based semiconductor layer 9, a p-type GaN semiconductor layer having a thickness of 50 [nm] is suitable.

半導体発光素子1はn型GaN基板15を更に含む。n型GaN基板15は、主面15aを有している。主面15aの(0001)面すなわちc面からのオフ角は、20°以上28°以下の範囲に含まれ、例えば23°である。n型GaN基板15の主面15a上にはn型AlGaN層17が設けられており、またn型GaN基板15の裏面上には電極19(カソード電極)が接触している。n型窒化ガリウム系半導体層3はn型AlGaN層17上に設けられている。n型AlGaN層17の厚さは、例えば20[nm]である。   The semiconductor light emitting device 1 further includes an n-type GaN substrate 15. The n-type GaN substrate 15 has a main surface 15a. The off angle from the (0001) plane, that is, the c-plane of the main surface 15a is included in the range of 20 ° to 28 °, for example, 23 °. An n-type AlGaN layer 17 is provided on the main surface 15 a of the n-type GaN substrate 15, and an electrode 19 (cathode electrode) is in contact with the back surface of the n-type GaN substrate 15. The n-type gallium nitride based semiconductor layer 3 is provided on the n-type AlGaN layer 17. The thickness of the n-type AlGaN layer 17 is, for example, 20 [nm].

活性層5は、例えば量子井戸構造を有することができ、InGaN井戸層5aおよび障壁層5bを含む。井戸層5aは、Inを含むIII族窒化物半導体層であり、例えばInGaNからなることができる。障壁層5bは、窒化ガリウム系半導体からなり、例えば井戸層5aのインジウム組成よりも少ないインジウム組成のInGaNからなることができる。なお、障壁層5bの材料としては、必要な場合にはGaNであることができる。活性層5の構造は、単一または多重の量子井戸構造に限定されることなく、単一のInGaN層からなることもできる。井戸層5aの一層毎の厚さは10[nm]以下であり、例えば5[nm]である。障壁層5bの厚さは井戸層5aより厚いことが好ましく、障壁層5bの一層毎の厚さは例えば15[nm]である。活性層5からの光Lは、電極11を介して出射される。   The active layer 5 can have a quantum well structure, for example, and includes an InGaN well layer 5a and a barrier layer 5b. The well layer 5a is a group III nitride semiconductor layer containing In, and can be made of, for example, InGaN. The barrier layer 5b is made of a gallium nitride-based semiconductor, and can be made of, for example, InGaN having an indium composition smaller than that of the well layer 5a. The material of the barrier layer 5b can be GaN if necessary. The structure of the active layer 5 is not limited to a single or multiple quantum well structure, and may be a single InGaN layer. The thickness of each well layer 5a is 10 [nm] or less, for example, 5 [nm]. The thickness of the barrier layer 5b is preferably thicker than that of the well layer 5a, and the thickness of each barrier layer 5b is, for example, 15 [nm]. Light L from the active layer 5 is emitted through the electrode 11.

半導体発光素子1はn型窒化ガリウム系緩衝層21を更に含む。n型窒化ガリウム系緩衝層21は、n型窒化ガリウム系半導体層3と活性層5との間に設けられている。InGaNからなる井戸層5aのc軸格子定数は、GaNからなるn型窒化ガリウム系半導体層3のc軸格子定数(0.51851nm)よりも大きい。この半導体発光素子1においては、n型窒化ガリウム系半導体層3と活性層5との格子定数の違いを補償するためにn型窒化ガリウム系緩衝層21が用いられる。これにより、活性層5はGaNの影響を受けることなく成長可能である。   The semiconductor light emitting device 1 further includes an n-type gallium nitride buffer layer 21. The n-type gallium nitride buffer layer 21 is provided between the n-type gallium nitride semiconductor layer 3 and the active layer 5. The c-axis lattice constant of the well layer 5a made of InGaN is larger than the c-axis lattice constant (0.51851 nm) of the n-type gallium nitride based semiconductor layer 3 made of GaN. In this semiconductor light emitting device 1, an n-type gallium nitride buffer layer 21 is used to compensate for the difference in lattice constant between the n-type gallium nitride semiconductor layer 3 and the active layer 5. Thereby, the active layer 5 can be grown without being influenced by GaN.

半導体発光素子1では、n型窒化ガリウム系緩衝層21は低温成長InGaNからなることが好ましく、n型窒化ガリウム系緩衝層21の厚さは例えば50[nm]である。低温成長InGaNの成長温度は、例えば800℃以下であることが好ましく、また例えば300℃以上であることが好ましい。   In the semiconductor light emitting device 1, the n-type gallium nitride buffer layer 21 is preferably made of low-temperature grown InGaN, and the thickness of the n-type gallium nitride buffer layer 21 is, for example, 50 [nm]. The growth temperature of the low-temperature grown InGaN is preferably 800 ° C. or lower, for example, and preferably 300 ° C. or higher.

図2は、本実施の形態に係る、半導体発光素子1を製造する方法の主要な工程を示すフローチャートである。また、図3および図4は、図2に示した各工程を説明するための図である。まず、図2の工程S101では、図3(a)に示すように、c面からのオフ角が20°以上28°以下の範囲に含まれる主面40aを有するn型のGaNウェハ40を準備する。次に、工程S103において、エピタキシャルウエハといった基板生産物を製造する。工程S103aでは、図3(b)に示すように、n型GaNウェハ40上にn型AlGaN層41、n型窒化ガリウム系半導体層42、およびn型窒化ガリウム系緩衝層43を主面40a上にエピタキシャル成長させる。これらの各層の厚さは、例えばn型AlGaN層41が20[nm]、n型窒化ガリウム系半導体層42が2000[nm]、n型窒化ガリウム系緩衝層43が50[nm]である。n型窒化ガリウム系半導体層42はGaNであることが好ましく、n型窒化ガリウム系緩衝層43は低温成長InGaNであることが好ましい。   FIG. 2 is a flowchart showing the main steps of the method for manufacturing the semiconductor light emitting device 1 according to the present embodiment. 3 and 4 are diagrams for explaining each process shown in FIG. First, in step S101 of FIG. 2, as shown in FIG. 3A, an n-type GaN wafer 40 having a main surface 40a that includes an off angle from the c-plane in the range of 20 ° to 28 ° is prepared. To do. Next, in step S103, a substrate product such as an epitaxial wafer is manufactured. In step S103a, as shown in FIG. 3B, an n-type AlGaN layer 41, an n-type gallium nitride semiconductor layer 42, and an n-type gallium nitride buffer layer 43 are formed on the main surface 40a on the n-type GaN wafer 40. Epitaxial growth. The thicknesses of these layers are, for example, 20 [nm] for the n-type AlGaN layer 41, 2000 [nm] for the n-type gallium nitride based semiconductor layer 42, and 50 [nm] for the n-type gallium nitride based buffer layer 43. The n-type gallium nitride based semiconductor layer 42 is preferably GaN, and the n-type gallium nitride based buffer layer 43 is preferably low-temperature grown InGaN.

続く工程S103bでは、図4(a)に示すように、Inを含む一又は複数のIII族窒化物半導体層を有する活性層44をn型窒化ガリウム系緩衝層43上に形成する。本実施形態では、活性層44に含まれる井戸層が上記III族窒化物半導体層に相当し、n型窒化ガリウム系緩衝層43上に井戸層および障壁層を交互にエピタキシャル成長させることにより、活性層44を形成する。活性層44の井戸層はInGaNを成長して形成され、活性層44の障壁層はInGaNまたはGaNを成長して形成される。井戸層の一層毎の厚さは10[nm]以下であり、例えば5[nm]である。障壁層の厚さは例えば15[nm]である。なお、厚さ2000[nm]のn型窒化ガリウム系半導体層42上に低温成長InGaNからなるn型窒化ガリウム系緩衝層43を設けているので、活性層44におけるInGaN井戸層の歪みの影響が緩和される。また、前述したように、GaNウェハ40の主面40aのc面からのオフ角は、20°以上28°以下の範囲に含まれる。換言すれば、主面40aの法線は、c軸に対し20°以上28°以下の範囲で傾いている。これにより、ピエゾ電界の影響を低減可能な半導体発光素子を作製できる。   In the subsequent step S103b, as shown in FIG. 4A, an active layer 44 having one or a plurality of group III nitride semiconductor layers containing In is formed on the n-type gallium nitride buffer layer 43. In the present embodiment, the well layer included in the active layer 44 corresponds to the group III nitride semiconductor layer, and the well layer and the barrier layer are alternately epitaxially grown on the n-type gallium nitride-based buffer layer 43, whereby the active layer 44 is formed. The well layer of the active layer 44 is formed by growing InGaN, and the barrier layer of the active layer 44 is formed by growing InGaN or GaN. The thickness of each well layer is 10 [nm] or less, for example, 5 [nm]. The thickness of the barrier layer is, for example, 15 [nm]. In addition, since the n-type gallium nitride buffer layer 43 made of low-temperature grown InGaN is provided on the n-type gallium nitride semiconductor layer 42 having a thickness of 2000 [nm], the influence of the distortion of the InGaN well layer in the active layer 44 is affected. Alleviated. Further, as described above, the off-angle from the c-plane of the main surface 40a of the GaN wafer 40 is included in the range of 20 ° to 28 °. In other words, the normal line of the main surface 40a is inclined in the range of 20 ° to 28 ° with respect to the c-axis. Thereby, a semiconductor light emitting device capable of reducing the influence of the piezoelectric field can be manufactured.

続く工程S103cでは、図4(b)に示すように、p型AlGaN半導体層45およびp型窒化ガリウム系半導体層46を活性層44上にエピタキシャル成長させる。p型AlGaN半導体層45は例えば電子ブロック層であり、p型窒化ガリウム系半導体層46は例えばコンタクト層である。これらの各層の厚さは、例えばp型AlGaN半導体層45が20[nm]、p型窒化ガリウム系半導体層46が50[nm]である。p型窒化ガリウム系半導体層46は例えばGaNを成長して形成される。以上の工程により、エピタキシャルウェハが作製される。   In the subsequent step S103c, as shown in FIG. 4B, the p-type AlGaN semiconductor layer 45 and the p-type gallium nitride semiconductor layer 46 are epitaxially grown on the active layer 44. The p-type AlGaN semiconductor layer 45 is, for example, an electron block layer, and the p-type gallium nitride semiconductor layer 46 is, for example, a contact layer. The thicknesses of these layers are, for example, 20 [nm] for the p-type AlGaN semiconductor layer 45 and 50 [nm] for the p-type gallium nitride based semiconductor layer 46. The p-type gallium nitride based semiconductor layer 46 is formed by growing GaN, for example. Through the above steps, an epitaxial wafer is manufactured.

工程S105では、エピタキシャルウェハのp型窒化ガリウム系半導体層46上に半透明電極(アノード電極)を形成する。更に、GaNウェハ40の裏面上に別の電極(カソード電極)を形成する。最後に、このエピタキシャルウェハをチップ状に分割することにより、本実施形態の半導体発光素子1が完成する。   In step S105, a translucent electrode (anode electrode) is formed on the p-type gallium nitride based semiconductor layer 46 of the epitaxial wafer. Further, another electrode (cathode electrode) is formed on the back surface of the GaN wafer 40. Finally, this epitaxial wafer is divided into chips to complete the semiconductor light emitting device 1 of the present embodiment.

ここで、図5を参照しつつ活性層44の成長方法の具体例について更に詳細に説明する。図5は、活性層44を成長させる際のGaNウェハ40の温度の遷移(図5(a))と、原料ガスの供給/非供給の状態(図5(b))とを示すグラフである。まず、期間T1において井戸層となるInGaN結晶を成長させる。井戸層を成長させる工程においては、井戸層の成長温度を600℃以上700℃以下の範囲に含まれる任意の温度とする。一般的に、InGaN結晶を成長させる温度は十分な結晶性を担保するため780℃程度に設定されることが多く、本実施形態における井戸層の成長温度はこれより低く設定される。なお、好適な成長温度は例えば650℃である。また、ここでいう成長温度は、GaNウェハ40の温度(基板温度)に置き換えることができる。   Here, a specific example of the growth method of the active layer 44 will be described in more detail with reference to FIG. FIG. 5 is a graph showing the temperature transition (FIG. 5A) of the GaN wafer 40 when the active layer 44 is grown, and the supply / non-supply state of the source gas (FIG. 5B). . First, an InGaN crystal that becomes a well layer is grown in a period T1. In the step of growing the well layer, the growth temperature of the well layer is set to an arbitrary temperature within the range of 600 ° C. to 700 ° C. In general, the temperature at which the InGaN crystal is grown is often set to about 780 ° C. to ensure sufficient crystallinity, and the growth temperature of the well layer in this embodiment is set lower than this. A suitable growth temperature is, for example, 650 ° C. The growth temperature here can be replaced with the temperature of the GaN wafer 40 (substrate temperature).

また、井戸層を成長させる工程においては、V族元素の原料ガス(例えばアンモニア)の流量QV[mol/分]とInの原料ガス(例えばトリメチルインジウム)の流量QIn[mol/分]とのモル流量比(QV/QIn)を、9000以上30000以下の範囲に含まれる任意の数値とする。一般的に、InGaN結晶を成長させる際の上記モル流量比は、ドロップレットの発生を防止するため40000程度に設定されることが多く、本実施形態におけるモル流量比はこれより低く(すなわちIn原料ガスが比較的多くなるように)設定される。なお、好適なモル流量比は例えば24000である。 In the step of growing the well layer, the flow rate Q In [mol / min] of the flow rate Q V [mol / min] and the In source gas of the source gas V group element (e.g., ammonia) (e.g. trimethyl indium) and The molar flow rate ratio (Q V / Q In ) is an arbitrary value included in the range of 9000 to 30000. In general, the molar flow rate ratio for growing an InGaN crystal is often set to about 40000 in order to prevent generation of droplets, and the molar flow rate ratio in this embodiment is lower than this (that is, the In raw material). It is set so that the gas is relatively high. A suitable molar flow ratio is, for example, 24000.

また、井戸層を成長させる工程においては、当該井戸層の成長速度を、0.01[μm/時]以上0.1[μm/時]以下の範囲に含まれる任意の速度とする。一般的に、InGaN結晶の成長速度は0.15[μm/時]程度に設定されることが多く、本実施形態における井戸層の成長速度はこれより遅く設定される。なお、好適な成長速度は例えば0.06[μm/時]である。   Further, in the step of growing the well layer, the growth rate of the well layer is set to an arbitrary rate included in the range of 0.01 [μm / hour] to 0.1 [μm / hour]. In general, the growth rate of the InGaN crystal is often set to about 0.15 [μm / hour], and the growth rate of the well layer in this embodiment is set slower than this. A suitable growth rate is, for example, 0.06 [μm / hour].

続いて、期間T2において障壁層となるGaN結晶を成長させる。障壁層を成長させる工程では、Inの原料ガスであるトリメチルインジウムの供給を停止するとともに、GaNウェハ40の温度を例えば820℃に上昇させ、GaN結晶を成長させる。なお、障壁層としてInGaN結晶を成長させる場合には、トリメチルインジウムの供給量を期間T1から低下させつつGaNウェハ40の温度を例えば820℃に上昇させるとよい。   Subsequently, a GaN crystal serving as a barrier layer is grown in the period T2. In the step of growing the barrier layer, the supply of trimethylindium, which is an In source gas, is stopped, and the temperature of the GaN wafer 40 is raised to, for example, 820 ° C. to grow a GaN crystal. In the case where an InGaN crystal is grown as the barrier layer, the temperature of the GaN wafer 40 may be increased to, for example, 820 ° C. while decreasing the supply amount of trimethylindium from the period T1.

活性層44の成長工程では、上記期間T2の後の期間T3〜T6において、活性層および障壁層を交互に成長させる。すなわち、期間T2後の期間T3および期間T5において期間T1と同じ成長条件にて井戸層を成長させ、期間T3後の期間T4、および期間T5後のT6において期間T2と同じ成長条件にて障壁層を成長させる。   In the growth process of the active layer 44, the active layer and the barrier layer are alternately grown in the period T3 to T6 after the period T2. That is, in the period T3 and the period T5 after the period T2, the well layer is grown under the same growth conditions as the period T1, and the barrier layer is grown under the same growth conditions as the period T2 in the period T4 after the period T3 and T6 after the period T5. Grow.

以上に述べた製造方法により得られる作用効果について、本発明者が解決課題を得、その解決に至った過程と併せて説明する。まず、Inを含むIII族窒化物半導体層(例えばInGaN井戸層)を有する活性層において緑色発光が得られる成長条件を決定するため、c面に対するオフ角が異なる複数のGaNウェハを用意し、これらのGaNウェハ上にInGaN結晶を同じ成長条件で成長させた。図6はその結果を示すグラフであり、c面に対するオフ角と、InGaN結晶におけるIn組成比との関係を示している。図6に示すように、オフ角が0°の場合(すなわちc面を主面とするGaNウェハ上にInGaN結晶を成長させた場合)と比較して、オフ角が0°より大きい場合にはIn組成比が小さくなっており、オフ角が大きくなるほどIn組成比がより小さくなることが判明した。例えば、c面を主面とするGaNウェハ上にInGaN結晶を成長温度750℃、成長速度0.15[μm/h]で成長させた場合、青色発光を得ることが可能な20%程度のIn組成比を実現できた。しかし、同じ成長条件でオフ角18°,28°のGaNウェハ上にInGaN結晶を成長させた場合、In組成比はそれぞれ8.3%,5.8%となり、オフ角が大きくなるに従ってIn組成比は減少した。オフ角18°,28°を有するこれらのGaNウェハを用いて従来の方法に従い発光ダイオードを作製したところ、発光波長は410[nm]〜430[nm]の青紫色領域となり、所望の緑色発光は観察されなかった。   The effects obtained by the manufacturing method described above will be described together with the process in which the present inventor obtained a solution problem and reached the solution. First, in order to determine the growth conditions for obtaining green light emission in an active layer having a group III nitride semiconductor layer containing In (for example, an InGaN well layer), a plurality of GaN wafers having different off angles with respect to the c-plane are prepared. InGaN crystal was grown on the same GaN wafer under the same growth conditions. FIG. 6 is a graph showing the results, showing the relationship between the off angle with respect to the c-plane and the In composition ratio in the InGaN crystal. As shown in FIG. 6, when the off angle is larger than 0 ° as compared with the case where the off angle is 0 ° (that is, when the InGaN crystal is grown on the GaN wafer having the c-plane as the main surface). It has been found that the In composition ratio is small, and that the In composition ratio becomes smaller as the off-angle increases. For example, when an InGaN crystal is grown on a GaN wafer having a c-plane as a main surface at a growth temperature of 750 ° C. and a growth rate of 0.15 [μm / h], about 20% of In capable of obtaining blue light emission. The composition ratio could be realized. However, when an InGaN crystal is grown on a GaN wafer having an off angle of 18 ° and 28 ° under the same growth conditions, the In composition ratios are 8.3% and 5.8%, respectively, and the In composition increases as the off angle increases. The ratio has decreased. When these GaN wafers having off angles of 18 ° and 28 ° were used to produce a light emitting diode according to a conventional method, the emission wavelength was in the blue-violet region of 410 [nm] to 430 [nm], and the desired green emission was Not observed.

そこで、本発明者は、オフ角を有するGaNウェハ上に成長したInを含むIII族窒化物半導体層の長波長化を図るべく、In組成比を増大させるための方法を探求した。その結果、従来より一般的に採用されてきた成長条件と比較して当該III族窒化物半導体層の成長温度および成長速度を下げ、In原料ガスのモル流量比を高めることで、上記問題を解決できることを見出した。   Therefore, the present inventors have sought a method for increasing the In composition ratio in order to increase the wavelength of a group III nitride semiconductor layer containing In grown on a GaN wafer having an off angle. As a result, the growth temperature and growth rate of the group III nitride semiconductor layer are lowered and the molar flow rate ratio of the In source gas is increased compared with the growth conditions that have been generally adopted so far, thereby solving the above problem. I found out that I can do it.

すなわち、本発明者は、半極性基板でも特にc面からのオフ角が20°以上28°以下の範囲に含まれる主面を有するGaNウェハを用い、従来の成長条件と比べてIII族窒化物半導体層の成長温度をより低くすることでInの付着率を高めつつ、成長速度も併せて低くすることで、Inの取り込み割合を増加させることに成功した。具体的には、上記オフ角を有するGaNウェハ上にIII族窒化物半導体層を成長させる際に、成長温度を600℃以上700℃以下の範囲とし、V族元素(例えばN)の原料ガスの流量QV[mol/分]とInの原料ガスの流量QIn[mol/分]とのモル流量比(QV/QIn)を9000以上30000以下の範囲とし、III族窒化物半導体層の成長速度を0.01[μm/時]以上0.1[μm/時]以下の範囲とすることにより、良好な結晶性を維持したままInの取り込み割合を高め得ることを見出した。 That is, the present inventor uses a GaN wafer having a main surface that is included in the range of 20 ° or more and 28 ° or less from the c-plane even in the case of a semipolar substrate. We succeeded in increasing the In incorporation rate by lowering the growth rate while lowering the growth rate while lowering the growth temperature while lowering the growth temperature of the semiconductor layer. Specifically, when the group III nitride semiconductor layer is grown on the GaN wafer having the off-angle, the growth temperature is set in the range of 600 ° C. to 700 ° C., and the source gas of the group V element (for example, N) The molar flow rate ratio (Q V / Q In ) between the flow rate Q V [mol / min] and the flow rate Q In [mol / min] of the In source gas is in the range of 9000 to 30000, and the group III nitride semiconductor layer It has been found that by setting the growth rate in the range of 0.01 [μm / hour] to 0.1 [μm / hour], the In incorporation ratio can be increased while maintaining good crystallinity.

ここで、図7は上記実施形態に係る製造方法により得られる半導体発光素子の電流−EL(エレクトロルミネッセンス)特性の一例であり、横軸は供給電流値(mA)を示し、縦軸はEL強度(μW)を示している。また、図8は上記実施形態に係る製造方法により得られる半導体発光素子の発光スペクトルの一例であり、横軸は波長(nm)を示し、縦軸は光強度(分光器の出力、単位はmV)を示している。図8に示されるように、上記実施形態に係る製造方法によって、波長510[nm]の緑色発光を観察することができた。   Here, FIG. 7 is an example of current-EL (electroluminescence) characteristics of the semiconductor light-emitting element obtained by the manufacturing method according to the above embodiment, the horizontal axis indicates the supply current value (mA), and the vertical axis indicates the EL intensity. (ΜW) is shown. FIG. 8 is an example of an emission spectrum of the semiconductor light emitting device obtained by the manufacturing method according to the above embodiment, the horizontal axis indicates the wavelength (nm), and the vertical axis indicates the light intensity (the output of the spectrometer, the unit is mV). ). As shown in FIG. 8, green light emission having a wavelength of 510 [nm] could be observed by the manufacturing method according to the embodiment.

このように、本実施形態に係る半導体発光素子の製造方法によれば、c面を主面とするGaNウェハを使用した場合と比較してピエゾ電界が小さく、且つ高いIn組成を有する活性層においてブルーシフトが抑えられた緑色発光の半導体発光素子を作製できる。   Thus, according to the method for manufacturing a semiconductor light emitting device according to this embodiment, in the active layer having a small piezoelectric field and a high In composition compared to the case of using a GaN wafer having a c-plane as a main surface. A green light-emitting semiconductor light-emitting element in which blue shift is suppressed can be manufactured.

また、本実施形態では活性層44を多重量子井戸構造とし、InGaN井戸層の上に成長するGaN障壁層の成長温度をInGaN井戸層の成長温度より高い820℃としている。これにより、GaN障壁層を成長させる際にInGaN井戸層に対するアニール効果も得ることができる。   In this embodiment, the active layer 44 has a multiple quantum well structure, and the growth temperature of the GaN barrier layer grown on the InGaN well layer is 820 ° C., which is higher than the growth temperature of the InGaN well layer. Thereby, an annealing effect on the InGaN well layer can be obtained when the GaN barrier layer is grown.

また、上記方法により得られるIII族窒化物半導体層のIn組成を調べるため、厚さ50[nm]のInGaN単層を上記方法によりGaNウェハ上に成長させたところ、当該層の表面に直径数10[nm]の粒状物が観察された。この粒状物をX線回折および組成分析により特定した結果、Inドロップレットであることがわかった。しかし、上記方法によりGaNウェハ上に厚さ3[nm]のInGaN井戸層を成長させた場合には、Inドロップレットは生じないことがTEM観察により確認された。すなわち、上記方法により成長させるInGaN層の厚さが極めて薄い(10nm以下)場合には、Inドロップレットが生じる前に成長が完了するものと考えられる。   Further, in order to investigate the In composition of the group III nitride semiconductor layer obtained by the above method, an InGaN single layer having a thickness of 50 [nm] was grown on the GaN wafer by the above method. A granular material of 10 [nm] was observed. As a result of specifying this granular material by X-ray diffraction and composition analysis, it was found to be an In droplet. However, when an InGaN well layer having a thickness of 3 nm was grown on a GaN wafer by the above method, it was confirmed by TEM observation that no In droplet was generated. That is, when the thickness of the InGaN layer grown by the above method is extremely thin (10 nm or less), it is considered that the growth is completed before the In droplet is generated.

このように、上記方法に係る成長条件は、例えば厚さ50[nm]といった厚いInGaN層を形成するとInドロップレットができる程度にIn原料ガスの供給量が多い成長条件である。オフ角が比較的大きいGaNウェハの主面では、表面ステップ密度が大きく且つc面テラス幅が小さいので、In原料ガスの供給量が多いことによりInがサーファクタントとして作用し、ステップ端において取り込まれにくいInの供給量が増え、InGaN結晶中に多く取り込まれるようになったものと考えられる。また、テラス幅が小さいGaNウェハの主面をInがサーファクタントとしてマイグレーションするので、当該InGaN結晶の成長温度が低くても結晶品質の低下が抑制されたものと考えられる。   As described above, the growth condition according to the above method is a growth condition in which the supply amount of In source gas is large enough to produce In droplets when a thick InGaN layer having a thickness of 50 [nm], for example, is formed. On the main surface of a GaN wafer having a relatively large off angle, the surface step density is large and the c-plane terrace width is small, so that In acts as a surfactant due to a large supply amount of In source gas, and is difficult to be taken in at the step end. It is considered that the amount of In supplied has increased, and a large amount of In has been incorporated into the InGaN crystal. Moreover, since In migrates as a surfactant on the main surface of the GaN wafer having a small terrace width, it is considered that the deterioration of the crystal quality is suppressed even when the growth temperature of the InGaN crystal is low.

なお、厚さ50[nm]のInGaN単層を成長させる際、In原料ガスのモル流量比を低下させると、Inドロップレットは次第に観察されなくなったが、In組成比が低下して発光波長が短波化してしまい、緑色発光を実現できなかった。また、比較のためc面を主面とするGaNウェハを用いて上記方法に係る成長条件でInGaN結晶を成長させたところ、Inドロップレットの発生状況は、オフ角を有するGaNウェハを使用した場合と同等となった。しかし、厚膜でInドロップレットが生じない程度にIn原料ガスのモル流量比を低下させたところ、十分な発光は得られなかった。   Note that when the InGaN single layer having a thickness of 50 [nm] is grown, if the molar flow ratio of the In source gas is decreased, In droplets are gradually not observed, but the In composition ratio is decreased and the emission wavelength is decreased. The wavelength was shortened and green light emission could not be realized. For comparison, when an InGaN crystal was grown under the growth conditions according to the above method using a GaN wafer having a c-plane as a main surface, the occurrence of In droplets was determined when a GaN wafer having an off angle was used. It became equivalent. However, when the molar flow rate ratio of the In source gas was lowered to such an extent that no In droplet was formed in the thick film, sufficient light emission was not obtained.

<実施例>
次に、一実施例として、半極性面を主面とするGaNウェハ上に多重量子井戸構造の活性層を成長させた例について説明する。まず、c面に対するオフ角がa軸方向に23°であるGaNウェハを用意した。そして、InGaN井戸層およびGaN障壁層を交互に3層ずつGaNウェハ上に成長させた。InGaN井戸層を成長させる際には、成長温度を650℃とし、Gaの原料ガスであるトリメチルガリウム(TMG)の流量を1.5[sccm(標準立方センチメートル/分)]とし、トリメチルインジウム(TMI)の流量を190[sccm]とし、アンモニア(NH3)の流量を29.6[slm(標準リットル/分)]とした。すなわち、In原料ガスのモル流量QIn[mol/分]とGa原料ガスのモル流量QGa[mol/分]とのモル流量比(QIn/QGa)を0.75とし、N原料ガスのモル流量QV[mol/分]とモル流量QInとのモル流量比(QV/QIn)を24000とした。これにより、このInGaN井戸層を成長させる際の成長速度は0.06[μm/時]となった。なお、InGaN井戸層の厚さを5[nm]とした。
<Example>
Next, as an example, an example in which an active layer having a multiple quantum well structure is grown on a GaN wafer having a semipolar plane as a main surface will be described. First, a GaN wafer having an off angle with respect to the c-plane of 23 ° in the a-axis direction was prepared. Then, three layers of InGaN well layers and GaN barrier layers were alternately grown on the GaN wafer. When the InGaN well layer is grown, the growth temperature is 650 ° C., the flow rate of trimethylgallium (TMG), which is a Ga source gas, is 1.5 [sccm (standard cubic centimeter / min)], and trimethylindium (TMI) Was set to 190 [sccm] and ammonia (NH 3 ) was set to 29.6 [slm (standard liter / min)]. That is, the molar flow rate ratio (Q In / Q Ga ) between the molar flow rate Q In [mol / min] of the In raw material gas and the molar flow rate Q Ga [mol / min] of the Ga raw material gas is set to 0.75, and the N raw material gas The molar flow rate ratio (Q V / Q In ) between the molar flow rate Q V [mol / min] and the molar flow rate Q In was 24000. As a result, the growth rate for growing this InGaN well layer was 0.06 [μm / hour]. The thickness of the InGaN well layer was 5 [nm].

このような発光素子に電流を供給したところ、緑色発光を好適に得ることができた。また、発光波長の短波長化(ブルーシフト)について調べたところ、供給電流量20[mA]〜200[mA]の範囲における波長変化は17[nm]であった。なお、c面を主面とするGaNウェハ上にこれと同様の多重量子井戸構造を作製し(但し、InGaN井戸層の成長温度を、EL発光が得られる750℃とした)、発光波長のブルーシフトについて調べたところ、上記電流範囲における波長変化は27[nm]であった。したがって、ピエゾ電界が低減してブルーシフトが抑えられていることが確認された。また、c面に対するオフ角がa軸方向に28°であるGaNウェハを用いて、上記と同様の多重量子井戸構造を作製し、発光波長のブルーシフトについて調べたところ、上記電流範囲における波長変化は10[nm]であり、ブルーシフトが更に抑えられることが確認された。   When a current was supplied to such a light emitting element, green light emission could be suitably obtained. Further, when the emission wavelength was shortened (blue shift), the wavelength change in the range of the supplied current amount of 20 [mA] to 200 [mA] was 17 [nm]. A multi-quantum well structure similar to this is fabricated on a GaN wafer having the c-plane as the main surface (however, the growth temperature of the InGaN well layer is set to 750 ° C. at which EL emission can be obtained), and the emission wavelength is blue. When the shift was examined, the wavelength change in the current range was 27 [nm]. Therefore, it was confirmed that the piezoelectric field was reduced and the blue shift was suppressed. Further, using a GaN wafer having an off-angle with respect to the c-plane of 28 ° in the a-axis direction, a multi-quantum well structure similar to the above was fabricated and the blue shift of the emission wavelength was examined. Was 10 [nm], and it was confirmed that the blue shift was further suppressed.

本発明による半導体発光素子の製造方法は、上記した実施形態に限られるものではなく、他に様々な変形が可能である。例えば、上記実施形態においては、GaNウェハ(GaN基板)上に成長させるIII族窒化物半導体層の例として、InGaNからなる井戸層を例示した。本発明におけるIII族窒化物半導体層はこれに限られず、Inを含むIII族窒化物半導体であれば他の組成を有してもよい。   The method for manufacturing a semiconductor light emitting device according to the present invention is not limited to the above-described embodiment, and various other modifications are possible. For example, in the above embodiment, a well layer made of InGaN has been exemplified as an example of a group III nitride semiconductor layer grown on a GaN wafer (GaN substrate). The group III nitride semiconductor layer in the present invention is not limited to this, and may have other compositions as long as it is a group III nitride semiconductor containing In.

図1は、実施の形態に係る半導体発光素子の製造方法によって製造される半導体発光素子の一例を概略的に示す側断面図である。FIG. 1 is a side sectional view schematically showing an example of a semiconductor light emitting device manufactured by the method for manufacturing a semiconductor light emitting device according to the embodiment. 図2は、実施の形態に係る、半導体発光素子を製造する方法の主要な工程を示すフローチャートである。FIG. 2 is a flowchart showing main steps of a method for manufacturing a semiconductor light emitting device according to the embodiment. 図3は、図2に示した各工程を説明するための図である。FIG. 3 is a diagram for explaining each step shown in FIG. 図4は、図2に示した各工程を説明するための図である。FIG. 4 is a diagram for explaining each step shown in FIG. 図5は、(a)活性層を成長させる際のGaNウェハの温度の遷移と、(b)原料ガスの供給/非供給の状態とを示すグラフである。FIG. 5 is a graph showing (a) the transition of the temperature of the GaN wafer when the active layer is grown, and (b) the supply / non-supply state of the source gas. 図6は、c面に対するオフ角と、InGaN結晶におけるIn組成比との関係を示している。FIG. 6 shows the relationship between the off angle with respect to the c-plane and the In composition ratio in the InGaN crystal. 図7は、実施形態に係る製造方法により得られる半導体発光素子の電流−EL特性の一例であり、横軸は供給電流値を示し、縦軸はEL強度を示している。FIG. 7 is an example of current-EL characteristics of the semiconductor light emitting device obtained by the manufacturing method according to the embodiment, the horizontal axis indicates the supply current value, and the vertical axis indicates the EL intensity. 図8は、実施形態に係る製造方法により得られる半導体発光素子の発光スペクトルの一例であり、横軸は波長を示し、縦軸は光強度を示している。FIG. 8 is an example of an emission spectrum of the semiconductor light emitting device obtained by the manufacturing method according to the embodiment, the horizontal axis indicates the wavelength, and the vertical axis indicates the light intensity.

符号の説明Explanation of symbols

1…半導体発光素子、3,42…n型窒化ガリウム系半導体層、5,44…活性層、5a…井戸層、5b…障壁層、7,45…p型AlGaN半導体層、9,46…p型窒化ガリウム系半導体層、11,19…電極、15…n型GaN基板、15a…主面、17,41…n型AlGaN層、21,43…n型窒化ガリウム系緩衝層、40…n型GaNウェハ。   DESCRIPTION OF SYMBOLS 1 ... Semiconductor light-emitting device, 3, 42 ... n-type gallium nitride semiconductor layer, 5,44 ... Active layer, 5a ... Well layer, 5b ... Barrier layer, 7, 45 ... p-type AlGaN semiconductor layer, 9, 46 ... p ... Type electrode gallium nitride semiconductor layer, 11, 19... Electrode, 15... N type GaN substrate, 15a... Main surface, 17, 41... N type AlGaN layer, 21, 43. GaN wafer.

Claims (1)

インジウムを含む一又は複数のIII族窒化物半導体層を有する活性層を窒化ガリウム基板上に備える半導体発光素子の製造方法であって、
(0001)面からのオフ角が20°以上28°以下の範囲に含まれる主面を有する前記窒化ガリウム基板上に前記III族窒化物半導体層を成長させる工程を備え、
前記工程における成長温度が600℃以上700℃以下の範囲に含まれ、
前記工程におけるV族元素の原料ガスの流量QV[mol/分]とインジウムの原料ガスの流量QIn[mol/分]とのモル流量比(QV/QIn)が9000以上30000以下の範囲に含まれ、
前記工程における前記III族窒化物半導体層の成長速度が0.01[μm/時]以上0.1[μm/時]以下の範囲に含まれ、
前記III族窒化物半導体層の一層毎の厚さが10nm以下である
ことを特徴とする、半導体発光素子の製造方法。
A method of manufacturing a semiconductor light emitting device comprising an active layer having one or more group III nitride semiconductor layers containing indium on a gallium nitride substrate,
A step of growing the group III nitride semiconductor layer on the gallium nitride substrate having a main surface with an off angle from the (0001) plane of 20 ° or more and 28 ° or less,
The growth temperature in the step is included in a range of 600 ° C. or more and 700 ° C. or less,
The molar flow rate ratio (Q V / Q In ) between the flow rate Q V [mol / min] of the group V element source gas and the indium source gas flow rate Q In [mol / min] in the above process is 9000 or more and 30000 or less. Included in the scope,
The growth rate of the group III nitride semiconductor layer in the step is included in a range of 0.01 [μm / hour] to 0.1 [μm / hour],
A method of manufacturing a semiconductor light emitting device, wherein the thickness of each group III nitride semiconductor layer is 10 nm or less.
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JP2009266963A (en) * 2008-04-23 2009-11-12 Sumitomo Electric Ind Ltd Nitride-based light emitting device, and method of manufacturing semiconductor light emitting device
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