JP2008226384A - Semiconductor memory device and its testing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device and its testing method by which a normal read-out operation is performed in a state that a supply voltage to memory cells is more lowered than a power source voltage in a normal mode, and a data holding property of the memory cell can simply be tested. <P>SOLUTION: The device is provided with: a first current path adjusting part M1 adjusting a value of conductance of a current path R1 provided between a low potential power source of the memory cell and ground; a second current path adjusting part 40 adjusting a value of conductance of a current path 2 to a larger value than a value of conductance of the current path R1; and an adjusting capability restricting part 50 restricting adjusting capability of the second current path adjusting part 40. In the test mode, values of conductance of the current paths R1, R2 are adjusted respectively by the first current path adjusting part M1 and the second current path adjusting part 40, and then access operation is performed for the memory cells. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention provides a semiconductor memory for simply testing data retention characteristics of a memory cell in a so-called sleep mode, which reduces power consumption during standby by stepping down a power supply voltage supplied to an internal circuit while prohibiting signal input The present invention relates to an apparatus and a test method thereof.

  A test in a data retention mode, which is a power saving mode in a semiconductor memory device such as an SRAM, is performed after a power source voltage is lowered and maintained for a predetermined time with respect to a memory cell in which data is written with a power source voltage within a guaranteed operating range. In this test, the data is read by returning the power supply voltage to the power supply voltage within the guaranteed operating range, and the data retention characteristic in the memory cell is tested.

  In the semiconductor memory device disclosed in Patent Document 1, the test time in the data retention mode test is shortened. When the power supply voltage supplied to the memory cell is stepped down, the “H” potential at the storage node of the memory cell leaks to the power supply VCC via the PMOS transistor of the write driver and falls rapidly to a low potential. In the semiconductor memory device described above, the time required for the “H” potential of the storage node to become stable at a low potential is shortened, and the test time in the data retention mode test is shortened.

  Here, both the data retention mode and the standby mode are operation modes for reducing power consumption during standby of the semiconductor memory device, and can be individually controlled. In the data retention mode, by reducing the power supply voltage supplied to the power supply voltage terminal, the power supply voltage supplied to the memory cell is stepped down to reduce power consumption. In the standby mode, control is performed by the enable terminal (CE terminal) and the chip select terminal (CS terminal), and in the standby state, the input buffer circuit for various signals is in a signal input prohibited state, thereby reducing power consumption. ing. When these operation modes are used in combination, the power consumption during standby of the semiconductor memory device can be further reduced.

In the above background art, assuming that the data retention mode is controlled separately from the standby mode, the memory cell storage is performed when the reduced power supply voltage is applied to the power supply voltage terminal to perform the test in the data retention mode. The purpose is to reduce the “H” potential of the node to the voltage value of the power supply voltage that has been stepped down quickly. The subsequent read operation is performed by normal read control for the semiconductor memory device. In addition, the technique disclosed by patent document 2, 3 is known as a thing relevant to said background art.
JP 2004-303283 A JP 2002-32990 A JP-A-4-278300

  However, in recent years, a sleep mode has been developed as control during standby of a semiconductor memory device. The sleep mode is an operation mode that reduces power consumption by stepping down the internal power supply voltage supplied to the internal circuit without accepting external signal input from the voltage value during normal use (normal mode). This is an operation mode similar to the simultaneous execution of the mode and the standby mode. In the test of the data retention characteristic of the memory cell at the stepped down internal power supply voltage, wait for the elapse of a predetermined time while the power supply voltage stepped down in the sleep mode is supplied, and then return to the normal mode and read the data. Was necessary.

  In this regard, although the above-described background art aims to reduce the test time during data retention, the reduction is made until the “H” potential of the storage node of the memory cell is quickly lowered to the power supply voltage that is stepped down. Is the time. The test of the data retention characteristic at the stepped down power supply voltage is nothing but the comparison between the passage of a predetermined time at the stepped down power supply voltage and the expected data by the read operation after returning to the normal power supply voltage.

  In the sleep mode, in the test of the data retention characteristic when the reduced power supply voltage is supplied to the memory cell, it is necessary to perform the data retention operation for a predetermined time while the reduced power supply voltage is supplied. Depending on the predetermined time, the test time cannot be shortened and the test time may be increased.

  The present invention has been proposed in view of such a situation, and for a semiconductor memory device having a sleep mode as an operation mode for reducing current consumption during standby, a supply voltage to a memory cell is set to a normal mode. An object of the present invention is to provide a semiconductor memory device and a test method thereof that can perform a normal read operation in a state where the voltage is lower than the power supply voltage in the memory cell and can easily test the data retention characteristics of the memory cell. .

  According to a first aspect of the present invention, there is provided a semiconductor memory device capable of setting a sleep mode and a test mode, wherein the semiconductor memory device is connected between a low potential power source and a ground of a memory cell, and A first current path adjusting unit for adjusting a conductance value of a first current path provided between the first current path and a low potential power source of the memory cell and the ground; A second current path adjustment unit that adjusts conductance values of different second current paths to a value larger than a conductance value of the first current path, a sleep mode setting signal that sets the sleep mode, and the test mode are set An adjustment capability limiting unit that limits the adjustment capability of the second current path adjustment unit according to a test mode setting signal to be performed, and in the test mode, The conductance value of the first current path and the conductance value of the second current path are respectively adjusted by the first current path adjuster and the second current path adjuster with the adjustment capability limited. An access operation is performed on the memory cell.

According to the semiconductor memory device of the first aspect of the invention, the adjustment of the second current path adjustment unit is performed by the adjustment capability limiting unit in accordance with the sleep mode setting signal for setting the sleep mode and the test mode setting signal for setting the test mode. When the capacity is limited, the second current path adjustment unit adjusts the conductance value of the second current path so as to approach the conductance value of the first current path, thereby reducing the potential on the low potential side of the memory cell. The potential of the high potential side of the memory cell, the potential of the low potential side of the memory cell, and the value of the differential voltage are lower than before the adjustment capability of the second current path adjustment unit is limited. . For this reason, the supply voltage to the memory cell determined according to the difference voltage is lower than before the adjustment capability of the second current path adjustment unit is limited. Therefore, according to the semiconductor memory device of the first aspect of the invention, in the leap mode and the test mode, the voltage supplied to the memory cell is lowered by supplying the memory cell with a voltage determined according to the difference voltage. The power consumed by the semiconductor memory device can be reduced.
According to the semiconductor memory device of the first aspect of the present invention, in the test mode, the conductance value of the first current path is adjusted by the first current path adjusting unit and the second current path adjusting unit whose adjustment capability is limited. And the conductance value of the second current path is adjusted, and the memory cell is accessed. Therefore, according to the semiconductor memory device of the first aspect of the present invention, when the voltage supplied to the memory cell decreases, the memory voltage is supplied under the condition that the supply voltage to the memory cell is insufficient for stable operation of the memory cell. You can access the cell. Therefore, according to the semiconductor memory device of the first aspect of the present invention, it is possible to identify a memory cell having a small operation margin due to manufacturing process variations and the like based on the access result to the memory cell. Therefore, according to the semiconductor memory device of the first aspect of the present invention, it is possible to detect in advance a memory cell that may cause an operation failure by specifying a memory cell having a small operation margin.

  According to a sixth aspect of the present invention, there is provided a test method for a semiconductor memory device, comprising: a first current provided between a low potential power source of a memory cell and ground; A first current path adjusting step of adjusting a conductance value of the path; and a conductance value of a second current path different from the first current path provided between the low potential power source of the memory cell and the ground. A second current path adjusting step for adjusting to a value larger than a conductance value of the first current path, a sleep mode setting signal for setting the sleep mode, and a test mode setting signal for setting the test mode, An adjustment capability limiting step for limiting the adjustment capability of the second current path adjustment unit, and in the test mode, The value of conductance of the first current path and the value of conductance of the second current path are respectively adjusted by the current path adjustment step and the second current path adjustment step in which the adjustment capability is limited, and the memory An access operation is performed on the cell.

According to the semiconductor memory device testing method of the sixth aspect of the present invention, the adjustment of the second current path is performed by the adjustment capability control step according to the sleep mode setting signal for setting the sleep mode and the test mode setting signal for setting the test mode. Before the conductance value is adjusted to approach the conductance value of the first current path, the potential on the low potential side of the memory cell can be increased, and the adjustment capability of the second current path adjustment step is limited. In comparison with this, the potential of the high potential side of the memory cell, the potential of the low potential side of the memory cell, and the value of the difference voltage are lowered. For this reason, the supply voltage to the memory cell determined according to the differential voltage is lower than before the adjustment capability of the second current path adjustment step is limited. Therefore, according to the test method of the semiconductor memory device of the sixth aspect of the invention, in the sleep mode and the test mode, the memory cell is supplied with a voltage determined according to the differential voltage to be supplied to the memory cell. The voltage can be reduced, and the power consumed by the semiconductor memory device can be reduced.
According to the semiconductor memory device testing method of the sixth aspect of the present invention, in the test mode, the first current path is adjusted by the first current path adjusting step and the second current path adjusting step in which the adjustment capability is limited. The conductance value and the conductance value of the second current path are adjusted, and an access operation is performed on the memory cell. Therefore, according to the semiconductor memory device testing method of the sixth aspect of the present invention, the conductance value of the second current path is changed to the value of the conductance of the first current path by the second current path adjustment step in which the adjustment capability is limited. When the difference voltage decreases and the voltage supplied to the memory cell decreases, the supply voltage to the memory cell decreases under the condition that the supply voltage to the memory cell is insufficient for stable operation of the memory cell. Can be accessed. Therefore, according to the semiconductor memory device testing method of the sixth aspect of the present invention, it is possible to identify a memory cell having a small operation margin due to manufacturing process variations and the like based on the access result to the memory cell. it can. Therefore, according to the semiconductor memory device testing method of the sixth aspect of the invention, it is possible to detect in advance a memory cell that may cause a malfunction by specifying a memory cell having a small operation margin. .

According to the semiconductor memory device and the test method thereof of the present invention, the memory cell is provided between the low-potential power supply of the memory cell and the ground according to the sleep mode setting signal for setting the sleep mode and the test mode setting signal for setting the test mode. The conductance value of the second current path is adjusted so as to approach the conductance value of the first current path provided between the low potential power source of the memory cell and the ground, and the potential on the low potential side of the memory cell is adjusted. Compared with the value of the conductance of the second current path approaching the value of the conductance of the one current path, the potential on the high potential side of the memory cell and the potential on the low potential side of the memory cell The value of the differential voltage decreases. For this reason, compared with the value before the conductance value of the second current path approaches the conductance value of the one current path, the supply voltage to the memory cell determined according to the difference voltage is lowered. Therefore, according to the method for testing a semiconductor memory device of the present invention, in the leap mode and the test mode, the voltage supplied to the memory cell is lowered by supplying the memory cell with a voltage determined according to the difference voltage. Thus, the power consumed by the semiconductor memory device can be reduced.
Further, according to the semiconductor memory device and the test method thereof of the present invention, in the test mode, the conductance value of the first current path and the conductance value of the second current path are adjusted respectively, and the memory cell An access operation is performed. Therefore, according to the semiconductor memory device and the test method thereof of the present invention, the value of the conductance of the second current path is adjusted so as to approach the value of the conductance of the first current path, the difference voltage is reduced, and the memory cell When the voltage supplied to the memory cell decreases, the memory cell can be accessed under conditions where the supply voltage to the memory cell is insufficient for the stable operation of the memory cell. Therefore, according to the semiconductor memory device and the test method thereof of the present invention, it is possible to identify a memory cell having a small operation margin due to manufacturing process variations and the like based on the access result to the memory cell. Therefore, according to the semiconductor memory device and the test method thereof of the present invention, it is possible to detect in advance a memory cell that may cause an operation failure by specifying a memory cell having a small operation margin.

<Embodiment 1>
Embodiment 1 of the present invention will be described with reference to FIG. Here, the semiconductor memory device of the present invention will be described by taking a static random access memory (SRAM) 10 as an example. FIG. 1 is a circuit configuration diagram of the SRAM 10. The SRAM 10 includes an input circuit 20, a memory cell array 30, an N-type channel transistor M1, a switching circuit 40, and a switching control circuit 50.

  The input circuit 20 includes a chip enable buffer 21, a write enable buffer 22, an input buffer 23, and a sleep buffer 24. The chip enable buffer 21 includes a first signal input terminal (IN1). The output terminal of the chip enable buffer 21 is connected to the output line L1.

  The write enable buffer 22 includes a first signal input terminal (IN2). A second input terminal of the write enable buffer 22 is connected to the output line L1. The output terminal of the write enable buffer 22 is connected to the output line L2.

  The input buffer 23 includes a first signal input terminal (IN3). The second signal input terminal of the input buffer 23 is connected to the output line L1. The output terminal of the input buffer 23 is connected to the output line L3.

  The sleep buffer 24 includes a signal input terminal (IN4). The output terminal of the sleep buffer 24 is connected to the output line L4. The output line L4 is connected to the second signal input terminal of the chip enable buffer 21.

  An output line L2 is connected to the memory cell array 30 via a write driver (not shown). Further, an output line L3 is connected to the memory cell array 30 via a row decoder and a column decoder (not shown). The memory cell array 30 has a plurality of memory cells arranged in a matrix not shown. Each memory cell is supplied with a power supply potential VCC and a ground potential VSS. Each memory cell is connected to a ground potential supply line 31.

  The drain and gate of the N-type channel transistor M 1 are connected to the ground potential supply line 31. The source of the N-type channel transistor M1 is connected to the ground.

  The switching circuit 40 includes N-type channel transistors M2 to M5. The drains of the N-type channel transistors M <b> 2 to M <b> 5 are connected to the ground potential supply line 31. The sources of the N-type channel transistors M2 to M5 are connected to the ground.

  The switching control circuit 50 includes a test mode setting signal input terminal (IN5), a NAND gate circuit 51, an inverter 52, and delay circuits 53 to 55. Each delay circuit 53 to 55 includes two inverters. The output line L4 is connected to the first input of the NAND gate circuit 51. A test mode setting signal input terminal (IN5) is connected to the second input of the NAND gate circuit 51. The output of the NAND gate circuit 51 is connected to the input of the inverter 52. The output of the inverter 52 is connected to the gate of an N-type channel transistor M2 provided in the switching circuit 40.

  The delay circuit 53 includes inverters 53A and 53B. The output of the inverter 52 is connected to the input of the inverter 53A. The output of the inverter 53A is connected to the input of the inverter 53B. The output of the inverter 53B is connected to the gate of an N-type channel transistor M3 provided in the switching circuit 40.

  The delay circuit 54 includes inverters 54A and 54B. The output of the inverter 53B is connected to the input of the inverter 54A. The output of the inverter 54A is connected to the input of the inverter 54B. The output of the inverter 54B is connected to the gate of an N-type channel transistor M4 provided in the switching circuit 40.

  The delay circuit 55 includes inverters 55A and 55B. The output of the inverter 54B is connected to the input of the inverter 55A. The output of the inverter 55A is connected to the input of the inverter 55B. The output of the inverter 55B is connected to the gate of an N-type channel transistor M5 provided in the switching circuit 40.

  Next, the operation of the SRAM 10 of this embodiment will be described. In the SRAM 10, it is possible to set a normal mode, a sleep mode, and a test mode. In the normal mode, data is written into the memory cell and stored data is read from the memory cell. In the sleep mode, a bit line or a word line arranged corresponding to the memory cell is not selected in a state where signals input from the first signal input terminals (IN1) to (IN3) are not received, and the memory cell Data is not stored in or read from data stored in the memory cell. In the test mode, in order to determine whether or not the operation of the memory cell is normal, the voltage supplied to the memory cell is lower than that in the normal mode, and data is stored in the memory cell or stored in the memory cell. The read data is read out.

  In the sleep mode, the SRAM 10 operates as described below. In the sleep mode, a low-level sleep mode setting signal SLP is input to the sleep buffer 24 through the signal input terminal (IN4). The sleep buffer 24 outputs a low-level sleep mode setting signal SLP to the chip enable buffer 21 through the output line L4.

  When the low-level sleep mode setting signal SLP is input to the second input terminal of the chip enable buffer 21, the chip enable buffer 21 does not receive the chip enable signal CE input from the first signal input terminal (IN1). To be controlled. Thereby, it is prohibited to transmit the chip enable signal CE to the second signal input terminal of the write enable buffer 22 and the second signal input terminal of the input buffer 23 through the output line L1.

  When the chip enable signal CE is not input to the second signal input terminal of the write enable buffer 22, the write enable buffer 22 is disabled. As a result, the write enable buffer 22 does not output the write enable signal WE input from the first signal input terminal (IN2) to the output line L2. Therefore, the signal WE is not input to the write driver connected to the output line L2, and data is not written to the memory cell by the write driver.

  Further, when the chip enable signal CE is not input to the second signal input terminal of the input buffer 23, the input buffer 23 is disabled. As a result, the input buffer 23 does not output the address signal ADD or the data signal D input from the first signal input terminal (IN3) to the output line L3. Therefore, the address signal ADD is not input to the row decoder or column decoder connected to the output line L3, and no bit line or word line is selected.

  In addition, in the sleep mode, a low-level signal SLP is input to the first input of the NAND gate circuit 51 included in the switching control circuit 50 through the output line L4. On the other hand, in the sleep mode, the high-level test mode setting signal TEST is input to the second input of the NAND gate circuit 51 through the test mode setting signal input terminal (IN5).

  The NAND gate circuit 51 outputs a high level signal to the input of the inverter 52. The inverter 52 outputs a low-level signal CS to the gate of the N-type channel transistor M2. As a result, the gate voltage of the N-type channel transistor M2 is fixed to a low level voltage, and the N-type channel transistor M2 is turned off.

  The delay circuits 53 to 55 output signals CS1 to CS3 obtained by sequentially delaying the cycle of the signal CS by the delay circuits 53 to 55 to the gates of the N-type channel transistors M3 to M5, respectively. As a result, the gate voltages of the N-type channel transistors M3 to M5 are sequentially fixed to a low level voltage, and the N-type channel transistors M3 to M5 are sequentially turned off.

  On the other hand, in the sleep mode, the gate voltage of the N-type channel transistor M1 is fixed near the threshold voltage, and the N-type channel transistor M1 is always kept on. When the N-type channel transistor M1 is turned on, a current path R1 is formed from the ground potential supply line 31 that supplies the ground potential to the memory cell to the ground through the N-type channel transistor M1. When the N-type channel transistor M1 is always on, the conductance value of the current path R1 is maintained at a constant value. In the present embodiment, the current path R1 corresponds to the first current path of the present invention, and the N-type channel transistor M1 corresponds to the first current path adjustment unit of the present invention. Further, maintaining the N-type channel transistor M1 in the on state at all times and keeping the conductance value of the current path R1 at a constant value corresponds to the first current path adjusting step.

  In the present embodiment, in the normal mode, a high level sleep mode setting signal SLP is input to the first input of the NAND gate circuit 51, and a high level test mode setting is input to the second input of the NAND gate circuit 51. A signal TEST is input. The NAND gate circuit 51 outputs a low level signal to the input of the inverter 52. Thereafter, the inverter 52 outputs a high-level signal CS to the gate of the N-type channel transistor M2. As a result, the gate voltage of the N-type channel transistor M2 is fixed to a high level voltage, and the N-type channel transistor M2 is turned on.

  Further, in the normal mode, the delay circuits 53 to 55 output signals CS1 to CS3 obtained by sequentially delaying the cycle of the signal CS to the gates of the N-type channel transistors M3 to M5. As a result, the gate voltages of the N-type channel transistors M3 to M5 are sequentially fixed to the high level voltage, and the N-type channel transistors M3 to M5 are sequentially turned on.

  When each N-type channel transistor M2 to M5 is turned on, a current path R2 from the ground potential supply line 31 to the ground through each N-type channel transistor M2 to M5 is formed. Therefore, the ground potential VSS is supplied to the memory cell, and the conductance value of the current path R2 is lower than in the sleep mode in which the transistors M2 to M5 are in the off state.

  In the present embodiment, the current path R2 corresponds to the second current path of the present invention. In the present embodiment, when each of the N-type channel transistors M2 to M5 of the switching circuit 40 is turned on, a current path R2 is formed, and the conductance value of the current path R2 is greater than the conductance value of the current path R1. It is adjusted to be larger. Therefore, the switching circuit 40 corresponds to the second current path adjusting unit of the present invention. Further, the second current path adjustment according to the present invention is performed by turning on each of the N-type channel transistors M2 to M5 and adjusting the conductance value of the current path R2 to be larger than the conductance value of the current path R1. It corresponds to a step.

  In the test mode, the SRAM 10 operates as described below. In order to switch to the test mode, a low-level test mode setting signal TEST is input through the test mode setting signal input terminal (IN5). In the test mode, a sleep mode setting signal SLP at a high level is input to the sleep buffer 24 in order to cancel the sleep mode. The sleep buffer 24 outputs a high-level sleep mode setting signal SLP to the chip enable buffer 21 through the output line L4.

  When the high-level sleep mode setting signal SLP is input to the second input terminal of the chip enable buffer 21, the chip enable buffer 21 receives the chip enable from the first signal input terminal (IN1) through the output line L1. The signal CE is output to the second signal input terminal of the write enable buffer 22.

  When the chip enable signal CE is input to the second signal input terminal of the write enable buffer 22, the write enable buffer 22 is enabled. As a result, the write enable buffer 22 outputs the write enable signal WE input from the first signal input terminal (IN2) to the output line L2.

  When the chip enable signal CE is input to the second signal input terminal of the input buffer 23, the input buffer 23 is enabled. Thereby, the input buffer 23 outputs the address signal ADD and the data signal D input from the first signal input terminal (IN3) to the output line L3. Therefore, an address signal ADD is input to the row decoder or column decoder connected to the output line L3, and a bit line or a word line is selected. Data corresponding to the data signal D is stored in the memory cells connected to the selected bit line and word line by the write driver connected to the output line L2.

  In addition, in the test mode, a high-level sleep mode setting signal SLP is input to the first input of the NAND gate circuit 51 through the output line L4. Furthermore, in the test mode, as described above, the low-level test mode setting signal TEST is input to the second input of the NAND gate circuit 51.

  In the test mode, the SRAM 10 operates in the same manner as in the sleep mode described above, and the gate voltage of each N-type channel transistor M2 to M5 of the switching circuit 40 is sequentially fixed to a low level voltage, and each N-type channel transistor M2 M5 is sequentially turned off. On the other hand, in the test mode, as in the sleep mode described above, the N-type channel transistor M1 is always kept on.

  In the test mode, when the N-type channel transistors M2 to M5 are sequentially turned off, the potential supplied to the memory cell by the ground potential supply line 31 rises above the ground potential VSS. In the present embodiment, the potential supplied to the memory cell is determined by the threshold voltage of the N-type channel transistor M1. Therefore, the difference between the power supply potential VCC of the memory cell and the potential determined by the threshold voltage is reduced.

  Therefore, in the test mode, the applied voltage to the memory cell determined by the difference between the power supply potential VCC and the potential determined by the threshold voltage is smaller than that in the normal mode. In the test mode, data is stored in the memory cell in a state where the voltage applied to the memory cell is suppressed compared to the normal mode. In the test mode, by supplying a read voltage to the word line and the bit line, stored data is read from the memory cells connected to the word line and the bit line by a read circuit (not shown).

  In the present embodiment, when the sleep mode setting signal SLP or the test mode setting signal TEST is input to the input of the NAND gate circuit 51 included in the switching control circuit 50, as described above, the inverter 52 included in the switching control circuit 50 includes The gate voltages of the N-type channel transistors M2 to M5 are fixed to a low level voltage or a high level voltage by the output signal CS and the output signals CS1 to CS3 of the delay circuits 53 to 55, respectively. Thereby, each transistor M2-M5 is controlled to an OFF state or an ON state. Since the switching control circuit 50 can vary the conductance value of the second current path R2 by controlling each of the transistors M2 to M5 to be in an off state or an on state, the switching control circuit 50 corresponds to the adjustment capability limiting unit of the present invention. . Further, it is possible to adjust the conductance value of the second current path R2 by controlling each of the transistors M2 to M5 in the off state or the on state by the sleep mode setting signal SLP or the test mode setting signal TEST. Corresponds to the limiting step.

<Effect of Embodiment 1>
In the SRAM 10 of the present embodiment, a low level signal is input from the switching control circuit 50 to the N-type channel transistor M2 due to the test mode setting signal TEST and the sleep mode setting signal SLP being input to the NAND gate circuit 51. When the signal CS is input and the low-level signals CS1 to CS3 are respectively input to the gates of the N-type channel transistors M3 to M5, and the transistors M2 to M5 are turned off, the transistors M2 to M5 are turned on. Compared to a certain normal mode, the potential supplied to the memory cell can be raised above the ground potential VSS by the ground potential supply line 31. Therefore, in the sleep mode and the test mode, the applied voltage to the memory cell determined by the difference between the power supply potential VCC of the memory cell and the potential supplied by the ground potential supply line 31 is smaller than in the normal mode. Therefore, according to the SRAM 10 of the present embodiment, the power consumed by the SRAM 10 can be reduced in the sleep mode and the test mode by reducing the voltage applied to the memory cell compared to the normal mode.
Further, in the SRAM 10 of the present embodiment, in the test mode, the N-type channel transistor M1 and the transistors M2 to M5 are turned on and the current paths R1 and R2 are formed, and the data to the memory cell is And stored data are read from the memory cell. Therefore, in the test mode, when the applied voltage to the memory cell is smaller than that in the normal mode, the applied voltage is insufficient for the storage into the memory cell and the read operation from the memory cell. The data is stored in the memory cell and the stored data is read from the memory cell. Therefore, it is possible to identify a memory cell in which the storage operation or the read operation is not stable due to the variation in the manufacturing process based on the storage result of the data in the memory cell or the read result of the storage data from the memory cell. it can. For this reason, in the SRAM 10 of the present embodiment, by specifying a memory cell in which the storage operation or the read operation is not stable, a memory cell that may cause a storage operation failure or a read operation failure is detected in advance. Can do.

Further, according to the test method of the SRAM 10 of the present embodiment, the low-level signal CS is input to the N-type channel transistor M2 due to the input of the test mode setting signal TEST and the sleep mode setting signal SLP. When the low-level signals CS1 to CS3 are input to the gates of the N-type channel transistors M3 to M5, respectively, and when the transistors M2 to M5 are turned off, the transistors M2 to M5 are turned on compared to the normal mode. Thus, the potential supplied to the memory cell can be made higher than the ground potential VSS by the ground potential supply line 31. Therefore, in the sleep mode and the test mode, the applied voltage to the memory cell determined by the difference between the power supply potential VCC of the memory cell and the potential supplied by the ground potential supply line 31 is smaller than in the normal mode. Therefore, according to the test method of the SRAM 10 of the present embodiment, the power consumed by the SRAM 10 can be reduced in the sleep mode and the test mode by reducing the voltage applied to the memory cell compared to the normal mode. it can.
In the test method of the SRAM 10 of this embodiment, in the test mode, the N-type channel transistor M1 and the transistors M2 to M5 are turned on, and the current paths R1 and R2 are formed, and the memory cell The data is stored in the memory cell and the stored data is read from the memory cell. Therefore, in the test mode, when the applied voltage to the memory cell is smaller than that in the normal mode, the applied voltage is insufficient for the storage into the memory cell and the read operation from the memory cell. The data is stored in the memory cell and the stored data is read from the memory cell. Therefore, it is possible to identify a memory cell in which the storage operation or the read operation is not stable due to the variation in the manufacturing process based on the storage result of the data in the memory cell or the read result of the storage data from the memory cell. it can. For this reason, in the test method of the SRAM 10 according to the present embodiment, by specifying a memory cell in which the storage operation or the read operation is not stable, a memory cell that may cause a storage operation failure or a read operation failure is determined in advance. Can be detected.

  In the present embodiment, when the switching control circuit 50 includes a test mode setting signal input terminal (IN5), it is distinguished from each of the first signal input terminals (IN1) to (IN3) and the signal input terminal (IN4). The test mode setting signal TEST can be input from the test mode setting signal input terminal (IN5), and the switching operation to the test mode can be easily performed.

<Embodiment 2>
A second embodiment of the present invention will be described with reference to FIG. FIG. 2 is a circuit configuration diagram of the SRAM 10A of the present embodiment. Here, the same configurations as those of the first embodiment are denoted by the same reference numerals, and the description thereof is omitted. The SRAM 10A includes an input circuit 20A and a switching control circuit 50A instead of the input circuit 20 and the switching control timing 50 of the SRAM 10 of the first embodiment.

  The input circuit 20A includes a command buffer 21A, a write enable buffer 22, and an input buffer 23. The command buffer 21A includes a first signal input terminal (IN1A), a second signal input terminal (IN2A), and a third signal input terminal (IN3A). The first signal output terminal of the command buffer 21A is connected to the output line L1A. The second signal output terminal of the command buffer 21A is connected to the output line L1B.

  A second input terminal of the write enable buffer 22 is connected to the output line L1A. A second input terminal of the input buffer 23 is connected to the output line L1A.

  The switching circuit 50A includes an inverter 51A instead of the NAND gate circuit 51 of the switching circuit 50 of the first embodiment. The second signal output terminal of the command buffer 21A is connected to the input of the inverter 51A through the output line L1B. The output of the inverter 51A is connected to the input of the inverter 52.

  Next, the operation of the SRAM 10A of this embodiment will be described. Here, the description of the same operation as that of the first embodiment is omitted. In the SRAM 10A, as in the first embodiment, it is possible to set the normal mode, the sleep mode, and the test mode. The chip enable command signal CE1 is input to the first signal input terminal (IN1A) of the command buffer 21A. The sleep mode setting command signal SLP1 is input to the second signal input terminal (IN2A) of the command buffer 21A. Various test command signals Test1 are input to the third signal input terminal (IN3A) of the command buffer 21A. For example, the test command signal Test1 includes a signal for checking a connection after mounting the substrate on the SRAM 10A, a scan test regarding the operation of the SRAM 10A, and the like.

  In the normal mode, the SRAM 10A operates as described below. In the normal mode, the chip enable command signal CE1 is input to the command buffer 21A through the first signal input terminal (IN1A).

  In the normal mode, the command buffer 21A outputs a high-level sleep mode setting signal SLP toward the input of the inverter 51A through the output line L1B. The inverter 51A outputs a low level signal to the input of the inverter 52. Thereafter, the inverter 52 outputs a high-level signal CS to the gate of the N-type channel transistor M2.

  Subsequently, as in the first embodiment, in the normal mode, the high-level signals CS1 to CS3 obtained by sequentially delaying the cycle of the signal CS are applied to the gates of the N-type channel transistors M3 to M5 by the delay circuits 53 to 55, respectively. Output. Thereby, in the normal mode, as in the first embodiment, the N-type channel transistors M2 to M5 are sequentially turned on.

  On the other hand, in the normal mode, the gate voltage of the N-type channel transistor M1 is fixed near the threshold voltage, and the N-type channel transistor M1 is always kept on.

  In the normal mode, the command buffer 21A outputs the chip enable signal CE to the second signal input terminal of the write enable buffer 22 through the output line L1A in correspondence with the chip enable command signal CE1. When the chip enable signal CE is input to the second signal input terminal of the write enable buffer 22, the write enable buffer 22 is enabled.

  In addition, in the normal mode, the command buffer 21A outputs a chip enable signal CE toward the second signal input terminal of the input buffer 23 through the output line L1A. When the chip enable signal CE is input to the second signal input terminal of the input buffer 23, the input buffer 23 is enabled. In the normal mode of the present embodiment, when the write enable buffer 22 and the input buffer 23 are enabled, data is stored in the memory cell as in the first embodiment.

  In the sleep mode, the SRAM 10A operates as described below. In the sleep mode, the sleep mode setting command signal SLP1 is input to the command buffer 21A through the second signal input terminal (IN2A). At this time, in the command buffer 21A, the input of the chip enable command signal CE1 is prohibited.

  In response to the sleep mode setting command signal SLP1, the command buffer 21A outputs a low-level sleep mode setting signal SLP to the input of the inverter 51A through the output line L1B. The inverter 51A outputs a high level signal to the input of the inverter 52. Thereafter, the inverter 52 outputs a low-level signal CS to the gate of the N-type channel transistor M2.

  Subsequently, as in the first embodiment, in the sleep mode, the low-level signals CS1 to CS3 obtained by sequentially delaying the cycle of the signal CS are applied to the gates of the N-type channel transistors M3 to M5 by the delay circuits 53 to 55, respectively. Output. Thereby, in the sleep mode, as in the first embodiment, the N-type channel transistors M2 to M5 are sequentially turned off.

  Further, in the sleep mode, when the chip enable command signal CE1 is prohibited from being input to the command buffer 21A and the chip enable signal CE is not input to the second signal input terminal of the write enable buffer 22, the write enable buffer 22 Disabled.

  In addition, in the sleep mode, when the chip enable signal CE is not input to the second signal input terminal of the input buffer 23, the input buffer 23 is disabled. In the sleep mode of the present embodiment, data is not written to the memory cell, similarly to the sleep mode of the first embodiment.

  In the test mode, the SRAM 10A operates as described below. In the test mode, a low-level test command signal Test1 is input to the command buffer 21A through the third signal input terminal (IN3A). At this time, in the command buffer 21A, the chip enable command signal CE1 is input through the first signal input terminal (IN1A) and the input of the sleep mode setting command signal SLP1 is prohibited. Here, the test command signal Test1 is a signal for setting a test mode.

  The command buffer 21A buffers the test command signal Test1, and outputs a low-level test signal Test toward the input of the inverter 51A through the output line L1B. The inverter 51A outputs a high level signal to the input of the inverter 52. Thereafter, the inverter 52 outputs a low-level signal CS to the gate of the N-type channel transistor M2.

  Subsequently, similarly to the sleep mode, in the test mode, the delay circuits 53 to 55 output low-level signals CS1 to CS3 to the gates of the N-type channel transistors M3 to M5, respectively. Thereby, in the test mode, each of the N-type channel transistors M2 to M5 is sequentially turned off as in the sleep mode.

  In the test mode, as in the normal mode, the chip enable signal CE is output to the second signal input terminal of the write enable buffer 22 through the output line L1A. As a result, the write enable buffer 22 is enabled.

  In addition, in the test mode, the chip enable signal CE is output to the second input terminal of the input buffer 23 through the output line L1A as in the normal mode. Thereby, the input buffer 23 is enabled. In the test mode, as in the sleep mode, the write enable buffer 22 and the input buffer 23 are enabled, and data is stored in the memory cells. Further, in the test mode, stored data is read from the memory cell in accordance with a read operation performed by a read circuit (not shown).

  In the present embodiment, each command signal CE1, SLP1, Test1 corresponds to the first input signal of the present invention. Each signal input terminal (IN1A) to (IN3A) corresponds to a signal input terminal of the present invention. The command buffer 21A corresponds to the command buffer unit of the present invention. In the present embodiment, the test signal Test corresponds to the test mode setting signal of the present invention.

<Effect of Embodiment 2>
In the present embodiment, the command buffer 21A outputs the test signal Test to the inverter 51A included in the switching control circuit 50A in correspondence with the test command signal Test1 input to the third signal input terminal (IN3A). Therefore, unlike the SRAM 10 of the first embodiment, the SRAM 10A of the present embodiment generates the test signal Test corresponding to the test command signal Test1 input to the third signal input terminal (IN3A). There is no need to provide a signal input terminal.

<Embodiment 3>
A third embodiment of the present invention will be described with reference to FIG. FIG. 3 is a circuit configuration diagram of the SRAM 10B of the present embodiment. Here, the same configurations as those of the first and second embodiments are denoted by the same reference numerals, and the description thereof is omitted. The SRAM 10B includes an input circuit 20B instead of the input circuit 20A of the second embodiment.

  The input circuit 20B includes a mode register set control unit 21B, an interface control unit 22B, a register REG1, a register REG2, and a control signal generation unit 23B.

  The mode register set control unit 21B includes a first signal input terminal (IN1B), a second signal input terminal (IN2B), a third signal input terminal (IN3B), a fourth signal input terminal (IN4B), and a fifth signal input terminal (IN2B). And a signal input terminal (IN5B).

  The interface control unit 22B includes a first signal input terminal (IN6B). The signal output terminal of the mode register set control unit 21B is connected to the second signal input terminal of the interface control unit 22B.

  The signal input terminal of the register REG1 is connected to the signal output terminal of the interface control unit 22B. An output line L3A is connected to the signal output terminal of the register REG1. The output line L3A is connected to the memory cell array 30 via a row decoder, a column decoder, etc. (not shown). The signal input terminal of the register REG2 is connected to the signal output terminal of the interface control unit 22B.

  The first signal input terminal of the control signal generator 23B is connected to the signal output terminal of the mode register set controller 21B. The second signal input terminal of the control signal generator 23B is connected to the signal output terminal of the register REG2. The signal output terminal of the control signal generator 23B is connected to the output line L1C and the output line L1D. The output line L1C is connected to an inverter 51A provided in the switching control circuit 50A. The output line L1D is connected to the memory cell array 30 via a row decoder and a column decoder (not shown).

  Next, the operation of the SRAM 10B of this embodiment will be described. Here, the description of the same operations as those in the first and second embodiments is omitted. Also in the SRAM 10B, as in the first and second embodiments, the normal mode, the sleep mode, and the test mode can be set.

  The chip enable signal CE is input to the first signal input terminal (IN1B) of the mode register set control unit 21B. A control signal for selecting each mode (normal mode, sleep mode, test mode) is input to the second signal input terminal (IN2B) to the fourth signal input terminal (IN4B) of the mode register set control unit 21B. . The row address strobe signal RAS is input to the second signal input terminal (IN2B). A column address strobe signal CAS is input to the third signal input terminal (IN3B). The write enable signal WE is input to the fourth signal input terminal (IN4B). The clock signal CLK is input to the fifth input signal (IN5B). The clock signal CLK is a master clock signal of the SRAM 10B.

  The address signal ADD and the data signal D are input to the first input terminal (IN6B) of the interface control unit 22B.

  In the normal mode, the SRAM 10B operates as described below. When a signal for selecting the normal mode is input to the mode register set control unit 21B according to the control signals CE, RAS, CAS, and WE, the normal mode control signal is supplied to the interface control unit 22B and the control signal generation unit 23B. MRS1 is output.

  The control signal generator 23B generates a low-level control signal CS5 when the normal mode control signal MRS1 is input to the first signal input terminal. The control signal generator 23B outputs a high level control signal CS5 toward the input of the inverter 51A through the output line L1C. As a result, as in the first and second embodiments, the N-type channel transistors M2 to M5 are sequentially turned on. Further, as in the first and second embodiments, the N-type channel transistor M1 is always kept on.

  Further, when the normal mode control signal MRS1 is input to the second signal input terminal, the interface control unit 22B outputs the address signal ADD and the data signal D to the register REG1. The address signal ADD and the data signal D are stored in REG1, and then output to a row decoder, a column decoder, and a write driver (not shown) through the output line L3A. Thereafter, in the SRAM 10B, the data corresponding to the data signal D is stored in the memory cell as in the normal mode of the first and second embodiments.

  In the sleep mode, the SRAM 10B operates as described below. The mode register set control unit 21B outputs a sleep mode control signal MRS2 to the interface control unit 22B and the control signal generation unit 23B according to the control signals CE, RAS, CAS, and WE.

  The control signal generator 23B generates a low-level control signal CS5 when the sleep mode control signal MRS2 is input to the first signal input terminal. The control signal generator 23B outputs a low level control signal CS5 toward the input of the inverter 51A through the output line L1C. As a result, as in the first and second embodiments, the N-type channel transistors M2 to M5 are sequentially turned off. Further, as in the first and second embodiments, the N-type channel transistor M10 is always kept on.

  Further, when the sleep mode control signal MRS2 is input to the second signal input terminal, the interface control unit 22B prohibits the output of the address signal ADD and the data signal D to the register REG1 and the register REG2. In the sleep mode of the present embodiment, data is not written to the memory cell as in the sleep mode of the first and second embodiments.

  In the test mode, the SRAM 10B operates as described below. The mode register set control unit 21B outputs a test mode control signal MRS3 to the interface control unit 22B and the control signal generation unit 23B according to the control signals CE, RAS, CAS, and WE.

  When the test mode control signal MRS3 is input to the second signal input terminal, the interface control unit 22B outputs the address signal ADD and the data signal D to the register REG2. The address signal ADD and the data signal D are output to the second signal input terminal of the control signal generator 23B after being stored in the register REG2.

  The control signal generator 23B generates a low-level control signal CS5 according to the test mode control signal MRS3 input to the first signal input terminal and the address signal ADD and data signal D input to the second signal input terminal. To do. The control signal CS5 is output toward the input of the inverter 51A through the output line L1C. The address signal ADD and the data signal D are output to a row decoder, a column decoder, and a write driver (not shown) through the output line L1D.

  When the low-level control signal CS5 is input to the inverter 51A, the N-type channel transistors M2 to M5 are sequentially turned off as in the above-described sleep mode. Similar to the sleep mode described above, the N-type channel transistor M1 is always kept on.

  In the test mode, each N-type channel transistor M2 to M5 maintains an off state, and the N-type channel transistor M1 maintains an on state, and data corresponding to the data D is received by a write driver (not shown). Stored in the memory cell. Further, in the test mode, stored data is read from the memory cell in accordance with a read operation performed by a read circuit (not shown).

  In the present embodiment, each signal CE, RAS, CAS, WE corresponds to the first input signal of the present invention. Each signal ADD, D corresponds to a second input signal of the present invention. Each of the signal input terminals (IN1B) to (IN6B) corresponds to a signal input terminal of the present invention. Since each mode control signal MRS1 to MRS3 is used to select each mode (normal mode, sleep mode, test mode), it corresponds to a state setting command of the present invention.

  In the present embodiment, the mode register set control unit 21B corresponds to the first decoder of the present invention. Since the register REG2 stores the address signal ADD and the data signal D input from the second input terminal (IN6B) of the interface control unit 22B, it corresponds to the register of the invention.

<Effect of Embodiment 3>
In the SRAM 10B of the present embodiment, the mode register set control unit 21B directs the test mode control signal MRS3 to the second signal input terminal of the interface control unit 22B in response to the control signals CE, RAS, CAS, and WE. Output. Thereafter, when the test mode control signal MRS3 is input to the second signal input terminal, the interface control unit 22B outputs the address signal ADD and the data signal D to the register REG2. Then, the control signal generator 23B generates a low-level control signal CS5 according to the address signal ADD, the data signal D, and the test mode control signal MRS3 stored in the register REG2. As a result, in the SRAM 10B of the present embodiment, the N-type channel transistors M2 to M5 are sequentially turned off, and data is stored in the memory cell in a state where the voltage applied to the memory cell is suppressed compared to the normal mode. The stored data is read from the memory cell. Therefore, in the SRAM 10B of this embodiment, in order to select the test mode, the test mode is selected separately from the control signals RAS and the like input from the signal input terminals (IN1B) to (IN6B) and the address signal ADD. There is no need to provide a terminal for inputting a signal.

<Embodiment 4>
A fourth embodiment of the present invention will be described with reference to FIG. FIG. 4 is a circuit configuration diagram illustrating a main part of the SRAM 10C of the present embodiment. Here, the same configurations as those of the first to third embodiments are denoted by the same reference numerals, and the description thereof is omitted. The SRAM 10C includes a voltage generation circuit 60. The voltage adjustment circuit 60 includes a reference voltage generation circuit 61, a voltage adjustment circuit 62, and an N-type channel transistor M7.

  The reference voltage generation circuit 61 includes a test mode setting signal input terminal (IN5) and a voltage dividing circuit (not shown). The test mode setting signal input terminal (IN5) is connected to a starting circuit (not shown) connected to the input part of the voltage dividing circuit. The test mode setting signal input terminal (IN5) is connected to the first input of the NAND gate circuit 51 provided in the switching control circuit 50. A signal input terminal (IN4) is connected to the second input of the NAND gate circuit 51. The sleep mode setting signal SLP is input to the signal input terminal (IN4).

  The voltage adjustment circuit 62 includes an error amplifier ERA1. The inverting input terminal of the error amplifier ERA1 is connected to the output part of the voltage dividing circuit. The non-inverting input terminal of the error amplifier ERA1 is connected to the ground potential supply line 31.

  The drain of the N-type channel transistor M7 is connected to the ground potential supply line 31. The gate of the N-type channel transistor M7 is connected to the output terminal (N) of the error amplifier ERA1. The source of the N-type channel transistor M7 is connected to the ground.

  Next, the operation of the SRAM 10C of this embodiment will be described. Here, the description of the same operation as that of the embodiment to the embodiment 3 is omitted. Also in the SRAM 10C, the normal mode, the sleep mode, and the test mode can be set as in the first and second embodiments. In the normal mode, the SRAM 10C operates in the same manner as in the first to third embodiments.

  In the sleep mode, the SRAM 10C operates as described below. In the sleep mode, the low-level sleep mode setting signal SLP is input to the second input of the NAND gate circuit 51 through the signal input terminal (IN4). In the sleep mode, the high-level test mode setting signal TEST is input to the first input of the NAND gate circuit 51 through the test mode setting signal input terminal (IN5). As a result, similarly to the first to third embodiments, the N-type channel transistors M2 to M5 are sequentially turned off. Further, as in the first to third embodiments, the N-type channel transistor M1 is always kept on.

  In the test mode, the SRAM 10C operates as described below. In the test mode, the low-level test mode setting signal TEST is input to the start-up unit of the voltage dividing circuit included in the reference voltage generation circuit 61 through the test mode setting signal input terminal (IN5).

  When the low-level test mode setting signal TEST is input to the starter, the voltage dividing circuit divides the power supply potential VCC and generates the reference voltage VREF. The voltage dividing circuit applies the reference voltage VREF to the inverting input terminal of the error amplifier ERA1 through the output unit. On the other hand, the potential V1 supplied to the memory cell by the ground potential supply line 31 is applied to the non-inverting input terminal of the error amplifier ERA1.

  The error amplifier ERA1 compares the reference voltage VREF with the potential V1, and outputs an error output voltage VOP from the output terminal (N) to the gate of the N-type channel transistor M7. In the present embodiment, the ON state of the N-type channel transistor M7 is controlled by the error output voltage VOP, and the value of the potential V1 is controlled to be the value of the reference voltage VREF. When the N-type channel transistor M7 is turned on, a current path R3 is formed from the ground potential supply line 31 to the ground through the N-type channel transistor M7.

  In addition, the low-level test mode setting signal TEST is input to the first input of the NAND gate circuit 51 through the test mode setting signal input terminal (IN5). In the test mode, the high level sleep signal SLP is input to the second input of the NAND gate circuit 51 through the signal input terminal (IN4). As a result, in the SRAM 10C, as in the SRAM 10 of the first embodiment, the respective type channel transistors M2 to M5 are sequentially turned off. For this reason, the current path R2 reaching the ground through the N-type channel transistors M2 to M5 is not formed.

  In the SRAM 10C, as in the SRAM 10 of the first embodiment, the N-type channel transistor M1 is kept on, and the conductance value of the current path R1 is kept constant.

  In this embodiment, the current drive capability of the N-type channel transistor M7 is adjusted to be different from the current drive capability of the N-type channel transistor M1 and the current drive capability of the transistor group including the N-type channel transistors M2 to M5. The conductance value of the current path R3 is set to be larger than the conductance value of the current path R1, and smaller than the conductance value of the current path R2.

  In the present embodiment, the current path R1 and the current path R3 are formed by the above-described operation in the test mode. By setting the conductance values of the current paths R1 to R3 in the relationship as described above, in the test mode, the current path R1 is compared with the sleep mode in which the current path R1 excluding the current paths R2 and R3 is formed. , R3, the potential supplied to the memory cell by the ground potential supply line 31 is lowered. For this reason, the difference between the power supply potential VCC and the potential supplied to the memory cell by the ground potential supply line 31 increases. Therefore, in the test mode, compared with the sleep mode, the voltage applied to the memory cell determined by the difference between the power supply potential VCC and the potential supplied to the memory cell by the ground potential supply line 31 is increased. For this reason, compared with the sleep mode, in the test mode, the voltage applied to the memory cell can be made closer to the voltage necessary for the stable operation of the memory cell.

  In the present embodiment, the current path R3 corresponds to the third current path of the present invention. When the low-level test mode setting signal TEST is input from the test mode setting signal input terminal (IN5) to the start-up section of the voltage dividing circuit, the reference voltage generating circuit 61 generates the reference voltage VREF. Let Therefore, the reference voltage generation circuit 61 corresponds to the reference voltage generation unit of the present invention.

  In this embodiment, the error output voltage VOP of the error amplifier ERA1 included in the voltage adjustment circuit 62 controls the ON state of the N-type channel transistor M7, and the conductance value of the current path R3 is set to the conductance value of the current path R1. It is set to be larger than the value and smaller than the conductance value of the current path R2. Therefore, the voltage adjustment circuit 62 and the N-type channel transistor M7 correspond to the conductance adjustment unit of the present invention. In the present embodiment, the voltage generation circuit 60 including the reference voltage generation circuit 61, the voltage adjustment circuit 62, and the N-type channel transistor M7 corresponds to the third current path adjustment unit of the present invention.

<Effect of Embodiment 4>
In the SRAM 10C of this embodiment, when the low-level test mode setting signal TEST is input from the test mode setting signal input terminal (IN5) to the start-up unit of the voltage dividing circuit, the voltage dividing circuit generates the reference voltage VREF. Let Further, in the SRAM 10C of the present embodiment, the potential V1 supplied to the memory cell by the ground potential supply line 31 is compared with the reference voltage VREF by the error amplifier ERA1, and the error output voltage VOP of the error amplifier ERA1 is the N-type channel. It is supplied to the gate of the transistor M7. Therefore, the ON state of the N-type channel transistor M7 is controlled by the error output voltage VOP, and the conductance value of the current path R3 is larger than the conductance value of the current path R1, and is larger than the conductance value of the current path R2. Set small.
Therefore, in the SRAM 10C of this embodiment, if the value of the reference voltage VREF is arbitrarily changed by adjusting the voltage dividing ratio of the voltage dividing circuit, the error output voltage VOP is made to correspond to the arbitrarily changed value of the reference voltage VREF. Can be changed. When the changed error output voltage VOP is supplied to the gate of the N-type channel transistor M7, the ON state of the N-type channel transistor M7 is controlled according to the error output voltage VOP, and the conductance value of the current path R3 is set. The value can be set larger than the conductance value of the current path R1 and smaller than the conductance value of the current path R2.
Therefore, in the SRAM 10C of the present embodiment, by arbitrarily adjusting the conductance value of the current path R3, the potential V1 supplied to the memory cell by the ground potential supply line 31 changes, and the power supply potential VCC and the ground potential are changed. The voltage applied to the memory cell determined by the difference from the potential V1 supplied to the memory cell by the supply line 31 is arbitrarily adjusted. For this reason, when the voltage applied to the memory cell is arbitrarily adjusted, the operating condition of the memory cell can be changed, and the setting state of the test mode is changed according to the voltage applied to the arbitrarily adjusted memory cell. Can be changed.

  The present invention is not limited to the embodiment described above, and can be implemented by appropriately changing a part of the configuration without departing from the spirit of the invention.

It is a circuit block diagram of SRAM of Embodiment 1 of this invention. FIG. 6 is a circuit configuration diagram of an SRAM according to a second embodiment. FIG. 6 is a circuit configuration diagram of an SRAM according to a third embodiment. FIG. 10 is a circuit configuration diagram of an SRAM according to a fourth embodiment.

Explanation of symbols

10 SRAM
21A Command buffer 30 Memory cell array 40 Switching circuit 50 Switching control circuit 61 Reference voltage generation circuit 62 Voltage adjustment circuit IN5 Test mode setting signal input terminals R1 to R3 Current path SLP Sleep mode setting signal TEST Test mode setting signal

Claims (6)

In a semiconductor memory device capable of setting a sleep mode and a test mode,
A first current path adjusting unit that is connected between the low potential power supply of the memory cell and the ground and adjusts the conductance value of the first current path provided between the low potential power supply and the ground;
A conductance value of a second current path that is connected between the low potential power supply of the memory cell and the ground is adjusted to a value larger than a conductance value of the first current path. A second current path adjusting unit that
An adjustment capability limiting unit that limits the adjustment capability of the second current path adjustment unit according to a sleep mode setting signal that sets the sleep mode and a test mode setting signal that sets the test mode,
In the test mode, the conductance value of the first current path and the conductance value of the second current path are set by the first current path adjuster and the second current path adjuster in which the adjustment capability is limited. A semiconductor memory device, wherein each of the memory cells is adjusted and an access operation is performed on the memory cell.   2. The semiconductor memory device according to claim 1, wherein the adjustment capability limiting unit includes a test mode setting signal input terminal to which the test mode setting signal is input. A command buffer unit for receiving a first input signal input to a signal input terminal different from the test mode setting signal input terminal;
The semiconductor memory device according to claim 1, wherein the command buffer unit generates the test mode setting signal according to the first input signal. A first decoder for decoding the first input signal;
A register that stores a second input signal that is different from the first input signal and is input to the signal input terminal according to a decoding result of the first decoder;
When the first decoder recognizes that the first input signal is a state setting command, the second input signal is stored in the register, and the second input stored in the register is stored. 2. The semiconductor memory device according to claim 1, wherein whether or not the test mode is selected is recognized based on a signal. A third current path adjusting unit that is connected between the low potential power supply of the memory cell and the ground and adjusts a conductance value of a third current path different from the first current path and the second current path; Prepared,
The third current path adjuster is
A reference voltage generator for generating a reference voltage in response to the test mode setting signal;
Conductance for adjusting the conductance value of the third current path to a value that is larger than the conductance value of the first current path and smaller than the conductance value of the second current path according to the reference voltage. An adjustment unit;
The semiconductor memory device according to claim 1, further comprising: In a test method of a semiconductor memory device capable of setting a sleep mode and a test mode,
A first current path adjusting step of adjusting a conductance value of a first current path provided between the low potential power source of the memory cell and the ground;
The conductance value of a second current path different from the first current path provided between the low potential power supply of the memory cell and the ground is adjusted to a value larger than the conductance value of the first current path. A second current path adjusting step,
An adjustment capability limiting step of limiting the adjustment capability of the second current path adjustment step according to a sleep mode setting signal for setting the sleep mode and a test mode setting signal for setting the test mode,
In the test mode, a conductance value of the first current path and a conductance value of the second current path are obtained by the first current path adjustment step and the second current path adjustment step in which the adjustment capability is limited. A test method for a semiconductor memory device, wherein each of the memory cells is adjusted and an access operation is performed on the memory cell.

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