CN112309482A - Memory element test circuit and memory element test method - Google Patents
Memory element test circuit and memory element test method Download PDFInfo
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- CN112309482A CN112309482A CN201910703354.5A CN201910703354A CN112309482A CN 112309482 A CN112309482 A CN 112309482A CN 201910703354 A CN201910703354 A CN 201910703354A CN 112309482 A CN112309482 A CN 112309482A
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- 238000012360 testing method Methods 0.000 title claims abstract description 146
- 230000015654 memory Effects 0.000 title claims abstract description 68
- 238000010998 test method Methods 0.000 title description 4
- 238000000034 method Methods 0.000 claims description 13
- 238000011084 recovery Methods 0.000 claims description 6
- 206010062519 Poor quality sleep Diseases 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
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Abstract
The invention discloses a memory element testing circuit and a memory element testing method. The memory element test circuit is used for testing a memory element and comprises a memory circuit, a comparison circuit and a control circuit. The storage circuit stores a test data. The comparison circuit is coupled to the storage circuit. The control circuit is coupled to the storage circuit, the comparison circuit and the storage element and is used for executing the following steps to test the storage element: writing the test data to the memory element; controlling the memory element to enter a low power mode; controlling the memory element to enter a functional mode; and controlling the comparison circuit to compare an output data of the storage element with the test data.
Description
Technical Field
The present invention relates to a memory device, and more particularly, to a test circuit and a test method for a memory device.
Background
In order to reduce the standby power consumption of a System on a Chip (SoC) and maintain the storage value of the memory device, the circuit is usually controlled by a power mode. For example, in a memory application, the low power modes of the memory include a light sleep mode (light sleep mode) and a deep sleep mode (deep sleep mode). However, the current built-in self-test (BIST) circuit only tests in the functional mode of the memory, and cannot test whether the memory is affected by the low power mode and loses the logic value that it should maintain after the memory returns from the low power mode to the functional mode. Therefore, a built-in self-test circuit capable of testing a low power mode of a memory is required.
Disclosure of Invention
In view of the foregoing, it is an object of the present invention to provide a memory device testing circuit and a memory device testing method for testing a low power consumption mode of a memory device.
The invention discloses a memory element test circuit, which is used for testing a memory element and comprises a storage circuit, a comparison circuit and a control circuit. The storage circuit stores a test data. The comparison circuit is coupled to the storage circuit. The control circuit is coupled to the storage circuit, the comparison circuit and the storage element and is used for executing the following steps to test the storage element: writing the test data to the memory element; controlling the memory element to enter a low power mode; controlling the memory element to enter a functional mode; and controlling the comparison circuit to compare an output data of the storage element with the test data.
The invention also discloses a memory device testing method for testing a memory device, which comprises the following steps: writing test data into the memory element; controlling the memory element to enter a low power mode; controlling the memory element to enter a functional mode; and comparing an output data of the memory element with the test data.
The memory element test circuit and the test method can test the low power consumption mode of the memory element, and can flexibly adjust the time length of the memory element to be tested in the low power consumption mode and the length of the awakening period after the low power consumption mode returns to the functional mode according to the type, the design and the application mode of the memory element to be tested and the test requirement. Compared with the prior art, the invention can test the storage element more comprehensively and more thoroughly.
The features, operation and effects of the present invention will be described in detail with reference to the drawings.
Drawings
FIG. 1 is a functional block diagram of a memory device built-in self-test circuit according to an embodiment of the present invention;
FIG. 2 is a flow chart of a method for testing a memory device according to the present invention;
FIG. 3 is a timing diagram of the main signals of FIG. 1; and
FIG. 4 is a flow chart of a method for testing a memory device according to the present invention.
Detailed Description
In the following description, the technical terms refer to the common terms in the technical field, and some terms are explained or defined in the specification, and the explanation of the some terms is based on the explanation or the definition in the specification.
The disclosure of the present invention includes a memory device testing circuit and a memory device testing method. Since some of the components included in the memory device test circuit of the present invention may individually be known components, the following description will omit details of known components without affecting the full disclosure and feasibility of the present invention. In addition, some or all of the processes of the memory device testing method of the present invention can be implemented in software and/or firmware, and can be executed by the memory device testing circuit of the present invention or its equivalent device.
In the following description, a signal at high level represents active (active) and at low level represents inactive (inactive), and an enable/disable signal represents pulling up/down the signal level. However, this is merely an example of an implementation or illustration and is not intended to limit the present invention. In other words, in various embodiments, a signal may be inactive when high, active when low, and an active/inactive signal when low represents pulling the signal low/high. Level shifting or logic level shifting represents a change from enabled (active) to disabled (inactive) or vice versa.
FIG. 1 is a functional block diagram of a memory device built-in self-test circuit according to an embodiment of the present invention. The memory device testing circuit 20 is coupled to the memory device 30 for testing the memory device 30. The memory device testing circuit 20 includes a storage circuit 210, a control circuit 220, and a comparison circuit 230. In normal operation, the logic circuit 10 (which may include a memory element control circuit) controls the memory element 30 with the address signal ADDR, the memory element enable/disable signal ME, and the memory element mode control signal PM. The input data D is data to be written into the memory element 30, and the output data Q is data read from the memory element 30. In the TEST mode, the control circuit 220 of the memory device TEST circuit 20 controls or operates the memory device 30 with the address signal TEST _ ADDR, the memory device enable/disable signal TEST _ ME, and the memory device mode control signal TEST _ PM. When the memory element 30 is enabled, it can be accessed (read and/or write), and when the memory element 30 is disabled, it cannot be accessed. The storage element mode control signal PM/TEST _ PM can control the storage element 30 not only to enter the low power consumption mode, but also to further control the storage element 30 to enter different kinds of low power consumption modes: a light sleep mode or a deep sleep mode.
The BIST _ MODE control multiplexer 242 to 248 outputs the signal generated by the logic circuit 10 or the signal generated by the memory device test circuit 20, which determines whether the memory device 30 is controlled by the logic circuit 10 (i.e., normal operation) or the control circuit 220 (i.e., test MODE). The memory element test circuit 20 operates according to the frequency BIST _ CLK. FIG. 2 is a flow chart of a method for testing a memory device according to the present invention, and FIG. 3 is a timing diagram of main signals of FIG. 1. Please refer to fig. 1 to 3 for the following description.
At the beginning of the TEST (the TEST enable signal BIST _ MODE is high), the control circuit 220 controls the memory device 30 to operate in the functional MODE (i.e. signals the control memory device MODE control signal TEST _ PM to be low), enables the memory device 30 (i.e. by controlling the memory device enable/disable signal TEST _ ME to be high), and writes the TEST data TEST _ D stored in the storage circuit 210 into the memory device 30 (step S210, between time points T0 and T1). After the write of the TEST data TEST _ D is completed, the control circuit 220 disables the memory device 30 by controlling the memory device enable/disable signal TEST _ ME to be low (step S220, time T1). Next, the control circuit 220 controls the TEST notification signal START _ PAUSE to be high level to notify the tester that the storage element 30 is about to enter the low power consumption mode (step S230, time point T2), and then controls the storage element 30 to enter the low power consumption mode (which may be a light sleep mode or a deep sleep mode) by controlling the storage element mode control signal TEST _ PM to be high level (step S240, time point T3). The tester knows that the memory device 30 will enter the low power mode and then starts timing, which aims to control the duration of the memory device 30 entering the low power mode. Thereafter, the tester may indicate that the storage element TEST circuit 20 should end the low power consumption mode by sending a recovery signal TEST _ RESUME to the storage element TEST circuit 20. In other words, the control circuit 220 does not act in step S245 (i.e., between time points T3 and T4) until the recovery signal TEST _ RESUME is received. Between time points T3 and T4, the storage element 30 stores TEST data TEST _ D and operates in a low power mode.
After receiving the RESUME signal TEST _ RESUME (yes in step S245, time point T4), the control circuit 220 notifies the tester that the storage element 30 is about to leave the low power consumption mode by controlling the TEST notification signal START _ PAUSE to be low (step S250, time point T5). The tester can calculate the duration of time that the storage element 30 operates in the low power consumption mode during the test according to the test notification signal START _ PAUSE. Next, the control circuit 220 controls the storage element 30 to enter the functional mode by controlling the storage element mode control signal TEST _ PM to be low level (step S260, time point T6). The memory device 30 returns from the low power consumption mode to the functional mode, which requires a wake-up period to ensure that the memory device 30 and/or the peripheral circuits thereof return to a normal operating state, so the control circuit 220 waits in step S265 until the end of the wake-up period (yes in step S265). In some embodiments, a setting value associated with the wake-up period is stored in the storage circuit 210, and the control circuit 220 controls when to end the wake-up period according to the setting value and the clock BIST _ CLK, and enables the memory device 30 by controlling the memory device enable/disable signal TEST _ ME to be high after the wake-up period ends (step S270, time T7). In some embodiments, the set point may be the number of cycles of the BIST _ CLK frequency and may be stored by a tester into the storage circuit 210 of the memory element test circuit 20 prior to testing.
After the memory device 30 is enabled again, the memory device testing circuit 20 accesses the memory device 30, and the control circuit 220 controls the comparing circuit 230 to compare the output data Q of the memory device 30 with the TEST data TEST _ D (step S280). If the output data Q is equal to the TEST data TEST _ D, it represents that the memory element 30 passes the TEST; otherwise, it means that the memory element 30 fails the test. The comparison circuit 230 may indicate whether the storage element 30 passes the test by outputting the comparison result RLT. Under normal operation, the output data Q of the storage element 30 can be processed by a subsequent output logic circuit (not shown).
In some embodiments, to further TEST the storage element 30, the storage element TEST circuit 20 may perform the process of fig. 2 again using the inverted data of the TEST data TEST _ D (i.e., steps S210 to S280). Referring to fig. 4, fig. 4 is a flow chart of a testing method of a memory device according to the present invention. After the process of fig. 2 is finished, when the output data Q is not the same as the TEST data TEST _ D (no in step S410), the comparison result RLT indicates that the memory device fails the TEST (step S420); when the output data Q is the same as the TEST data TEST _ D (yes in step S410), the control circuit 220 determines whether the memory device 30 was tested using the TEST data # TEST _ D that is the inverse of the TEST data TEST _ D (step S430). If the inverted TEST data # TEST _ D has not been tested (NO in step S430), the control circuit 220 uses the inverted TEST data # TEST _ D (step S440) to perform the process of FIG. 2 again (i.e., steps S210 to 280); if the inverted TEST data # TEST _ D has been tested (YES in step S430), it represents that the storage element passes the TEST (step S450), and the TEST flow may end. In step S440, the control circuit 220 may read the inverted TEST data # TEST _ D from the storage circuit 210 or invert the original TEST data # TEST _ D to generate the inverted TEST data # TEST _ D. Logic 1 and logic 0 are inverse data of each other. The invention can not only test the low power consumption mode of the storage element 30, but also flexibly adjust or set the duration of the storage element 30 in the low power consumption mode and the length of the wake-up period of the storage element 30. More specifically, the tester can freely control when the recovery signal TEST _ RESUME is input to the storage element TEST circuit 20 to control the duration of the low power consumption mode, and adjust the length of the wake-up period by changing the setting value. The length of the wake-up period (i.e., the setting value) can be set according to the type of the storage element 30 and/or the type of the low power mode. For example, the tester may give different settings for different types of Static Random Access Memories (SRAMs), and may give different settings for the light sleep mode and the deep sleep mode. In some embodiments, the length of the wake-up period of the deep sleep mode is greater than the length of the wake-up period of the light sleep mode.
The storage circuit 210 may be a memory or a buffer (register). The control circuit 220 may be a Finite State Machine (FSM) composed of a plurality of logic circuits, which can be completed by one of ordinary skill in the art according to the flow chart of fig. 2. The comparison circuit 230 is well known to those skilled in the art and will not be described herein.
It should be noted that in some embodiments, steps S220, S265 and S270 may be omitted, i.e. the invention may only test the low power mode of the memory device without testing the impact on the memory device during wake-up.
Since the details and variations of the disclosed method and invention can be understood by those skilled in the art from the disclosure of the present device and invention, the repetitive description is omitted here for the sake of brevity and without affecting the disclosed requirements and feasibility of the method and invention. It should be noted that the shapes, sizes, proportions, and sequence of steps of the components and other elements in the drawings are illustrative only and are not intended to be limiting, since those skilled in the art will recognize the present invention. In addition, although the memory is illustrated and described in the foregoing embodiments, it is not intended to limit the invention, and those skilled in the art can appropriately apply the invention to other types of memory devices, such as registers, according to the disclosure of the invention.
Although the embodiments of the present invention have been described above, these embodiments are not intended to limit the present invention, and those skilled in the art can make variations on the technical features of the present invention according to the explicit or implicit contents of the present invention, and all such variations may fall within the scope of the patent protection sought by the present invention.
[ notation ] to show
10 logic circuit
20 storage element test circuit
210 storage circuit
220 control circuit
230 comparison circuit
242. 244, 246, 248 multiplexer
30 storage element
ADDR, TEST _ ADDR Address signals
D input data
TEST _ D TEST data
Q output data
ME, TEST _ ME memory element enable/disable signal
PM, TEST _ PM storage element mode control signal
BIST _ MODE test enable signal
BIST _ CLK frequency
START _ PAUSE test Notification Signal
TEST _ RESUME recovery signal
RLT comparison results
Steps S210 to S290.
Claims (10)
1. A memory element test circuit for testing a memory element, comprising:
a storage circuit for storing a test data;
a comparison circuit coupled to the storage circuit;
a control circuit coupled to the storage circuit, the comparison circuit and the memory device, the control circuit being configured to perform the following steps to test the memory device:
(A) writing the test data to the memory element;
(B) controlling the memory element to enter a low power mode;
(C) controlling the memory element to enter a functional mode; and
(D) the comparison circuit is controlled to compare an output data of the storage element with the test data.
2. The memory element test circuit of claim 1, the control circuit further performing the steps of:
(E) disabling the storage element before controlling the storage element to enter the low power mode; and
(F) enabling the memory element after controlling the memory element to enter the functional mode.
3. The memory element test circuit of claim 2, wherein the storage circuit further stores a set value, the control circuit further performing the steps of:
(G) after controlling the storage element to enter the functional mode, the storage element is enabled after waiting for a period of time according to the setting value, wherein the setting value is related to the type of the storage element and/or the type of the low power consumption mode.
4. The memory element test circuit of claim 1, wherein the control circuit further performs the steps of:
(E) waiting for a restore signal after controlling the memory element to enter the low power mode; and
(F) and controlling the storage element to enter the functional mode according to the recovery signal.
5. The memory element test circuit of claim 1, wherein the control circuit further performs the steps of:
(E) and (D) executing the steps (A) to (D) again by using the inverted data of the test data.
6. A memory device testing method for testing a memory device, comprising:
(A) writing test data into the memory element;
(B) controlling the memory element to enter a low power mode;
(C) controlling the memory element to enter a functional mode; and
(D) an output data of the memory element is compared with the test data.
7. The method of claim 6, further comprising:
(E) disabling the storage element before controlling the storage element to enter the low power mode; and
(F) enabling the memory element after controlling the memory element to enter the functional mode.
8. The method of claim 7, further comprising:
(G) waiting for a period of time to enable the memory element after controlling the memory element to enter the functional mode;
wherein the period of time is related to the type of the storage element and/or the type of the low power mode.
9. The method of claim 6, further comprising:
(E) waiting for a restore signal after controlling the memory element to enter the low power mode; and
(F) and controlling the storage element to enter the functional mode according to the recovery signal.
10. The method of claim 6, further comprising:
(E) and (D) executing the steps (A) to (D) again by using the inverted data of the test data.
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| CN201910703354.5A CN112309482A (en) | 2019-07-31 | 2019-07-31 | Memory element test circuit and memory element test method |
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| CN201910703354.5A CN112309482A (en) | 2019-07-31 | 2019-07-31 | Memory element test circuit and memory element test method |
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Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5173906A (en) * | 1990-08-31 | 1992-12-22 | Dreibelbis Jeffrey H | Built-in self test for integrated circuits |
| CN1252604A (en) * | 1998-10-23 | 2000-05-10 | 联华电子股份有限公司 | Memory element testing circuit |
| KR20020014031A (en) * | 2000-08-14 | 2002-02-25 | 이국상 | Apparatus for testing semiconductor memory devices |
| CN1641371A (en) * | 2004-01-16 | 2005-07-20 | 松下电器产业株式会社 | Test method for a semiconductor integrated circuit and a semiconductor integrated circuit |
| US20070226568A1 (en) * | 2006-03-10 | 2007-09-27 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit and design apparatus thereof |
| US20070230260A1 (en) * | 2006-03-31 | 2007-10-04 | Gorman Kevin W | Automatic shutdown or throttling of a bist state machine using thermal feedback |
| JP2008226384A (en) * | 2007-03-14 | 2008-09-25 | Fujitsu Ltd | Semiconductor memory device and its testing method |
| US20100287430A1 (en) * | 2001-02-15 | 2010-11-11 | Syntest Technologies, Inc. | Multiple-capture dft system to reduce peak capture power during self-test or scan test |
| US20150137841A1 (en) * | 2012-06-07 | 2015-05-21 | Freescale Semiconductor, Inc. | Built-in self test system, system on a chip and method for controlling built-in self tests |
| US20160111170A1 (en) * | 2014-10-16 | 2016-04-21 | Yunwu Zhao | Method and apparatus for testing memory |
| US20160231797A1 (en) * | 2015-02-05 | 2016-08-11 | Apple Inc. | Solid state drive with self-refresh power saving mode |
-
2019
- 2019-07-31 CN CN201910703354.5A patent/CN112309482A/en active Pending
Patent Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5173906A (en) * | 1990-08-31 | 1992-12-22 | Dreibelbis Jeffrey H | Built-in self test for integrated circuits |
| CN1252604A (en) * | 1998-10-23 | 2000-05-10 | 联华电子股份有限公司 | Memory element testing circuit |
| KR20020014031A (en) * | 2000-08-14 | 2002-02-25 | 이국상 | Apparatus for testing semiconductor memory devices |
| US20100287430A1 (en) * | 2001-02-15 | 2010-11-11 | Syntest Technologies, Inc. | Multiple-capture dft system to reduce peak capture power during self-test or scan test |
| CN1641371A (en) * | 2004-01-16 | 2005-07-20 | 松下电器产业株式会社 | Test method for a semiconductor integrated circuit and a semiconductor integrated circuit |
| US20070226568A1 (en) * | 2006-03-10 | 2007-09-27 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit and design apparatus thereof |
| US20070230260A1 (en) * | 2006-03-31 | 2007-10-04 | Gorman Kevin W | Automatic shutdown or throttling of a bist state machine using thermal feedback |
| JP2008226384A (en) * | 2007-03-14 | 2008-09-25 | Fujitsu Ltd | Semiconductor memory device and its testing method |
| US20150137841A1 (en) * | 2012-06-07 | 2015-05-21 | Freescale Semiconductor, Inc. | Built-in self test system, system on a chip and method for controlling built-in self tests |
| US20160111170A1 (en) * | 2014-10-16 | 2016-04-21 | Yunwu Zhao | Method and apparatus for testing memory |
| CN105575438A (en) * | 2014-10-16 | 2016-05-11 | 飞思卡尔半导体公司 | Method and device for testing memory |
| US20160231797A1 (en) * | 2015-02-05 | 2016-08-11 | Apple Inc. | Solid state drive with self-refresh power saving mode |
| CN107210057A (en) * | 2015-02-05 | 2017-09-26 | 苹果公司 | Solid-state drive with self-refresh energy-saving mode |
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