JP2008218638A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent misregistration in a lithography process by forming a local source line self-alignedly. <P>SOLUTION: In an NOR flash memory device, gate electrodes MG of memory cells are made by stacking a silicon oxide film 4, a polycrystal silicon film 5, an ONO film 6, another polycrystal silicon film 7, a tungsten silicide film 8, and a silicon oxide film 9 in order on a silicon substrate 1. On the silicon oxide film 9, a silicon oxide film 10 and a silicon nitride film 11 are stacked to form a BPSG film 12 to embed spaces between the gate electrodes MG. The BPSG film 12 embedded between the gate electrodes MG is removed by wet etching, and then the silicon oxide film 10 and the silicon nitride film 11 are etched by RIE to form a trench wherein an impurity diffusion region 1b is exposed. The local source line LS is formed in the trench in a way that its upper part partially covers the top faces of the gate electrodes MG. A drain contact DC and a via plug VP are formed by another photolithographic process. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a configuration in which sources of a plurality of transistors are electrically connected by a common source line, and a manufacturing method thereof.

  As a semiconductor device, for example, in a NOR flash memory device which is one of the flash memory devices shown in Patent Document 1, an element isolation region in which a large number of memory cell transistors are arranged in a matrix and arranged in one direction. Thus, the memory cell transistors arranged in a line are divided. A common source line is formed so that the source regions of the memory cell transistors adjacent to each other across the element isolation region are electrically connected. The drain regions of the memory cell transistors are electrically connected by individually formed drain contacts.

The common source line and drain contact are formed in a source region and a drain region that are formed in common on the surface layer of the semiconductor substrate between the gate electrodes of adjacent memory cell transistors. In this case, when forming the common source line and the drain contact, it is necessary to prevent occurrence of a short circuit with the gate electrode, and therefore, it is necessary to form a pattern in consideration of misalignment in the lithography process. For this reason, the width dimension between the gate electrodes is required to be set including a certain misalignment from the width dimension of the gate electrode and the width dimension of the common source line or drain contact. Therefore, this has limited the miniaturization in pattern design.
JP 2004-152878 A

  According to the present invention, when forming a contact for providing a common source line for commonly connecting source regions of a plurality of transistors, the formation of the common source line is performed in a self-aligned manner in order to cope with a defect due to misalignment in a lithography process. An object of the present invention is to provide a semiconductor device that can be formed and a method of manufacturing the same.

  A semiconductor device according to one embodiment of the present invention includes a gate electrode formed on a surface of a semiconductor substrate with a gate insulating film interposed therebetween and a first insulating film on an upper surface portion, and a surface layer portion of the semiconductor substrate on both sides of the gate electrode. A plurality of transistors each having a source region and a drain region formed, an element isolation region that insulates and separates a cell array in which a predetermined number of the transistors are arranged in rows, and an upper surface portion and a side wall portion of the gate electrode are covered. A lower insulating film that is in electrical contact with the source region and that is in contact with the side walls of the gate electrodes of the two transistors facing the source region via the second insulating film. And an upper portion covering each of part of the upper surfaces of the two gate electrodes, and the transistors formed at positions adjacent to each other through the element isolation region Over a common source line electrically connected in common between the source region, characterized in it was and a plug formed on the upper portion of the common source line so as to be electrically connected to the common source line.

  According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device in which a plurality of active regions partitioned in a strip shape in an element isolation region are formed on a semiconductor substrate, a gate insulating film is formed in each active region, and a first insulating film is formed. Forming a gate electrode provided on the upper surface; introducing a impurity into a surface layer of the semiconductor substrate sandwiched between the gate electrodes; forming a source region and a drain region; and Forming a second insulating film on the side wall and the upper surface and the surfaces of the source region and the drain region; and embedding insulation on the semiconductor substrate so as to be embedded between the gate electrodes on which the second insulating film is formed A step of forming a film, and a band-shaped opening pattern having a width dimension larger than a width dimension of the gate electrode located on both sides of a portion corresponding to the source region, Forming a resist pattern on the gate electrode and the buried insulating film so as to expose a portion corresponding to a region, and the portion formed on the portion corresponding to the source region by wet etching using the resist pattern as a mask Removing the buried insulating film; and anisotropically etching the resist pattern as a mask to remove the second insulating film on the semiconductor substrate and the gate electrode exposed by removing the buried insulating film. It is characterized in that it comprises a step of removing, and a step of forming a common source line by embedding a conductor in the portion where the second insulating film is removed.

  According to the present invention, it is possible to reduce the cell size by reducing problems caused by misalignment of the common source lines.

  Hereinafter, an embodiment in which the present invention is applied to a NOR flash memory device will be described with reference to FIGS. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones.

First, the configuration of the NOR type flash memory device of this embodiment will be described.
FIG. 1 is an equivalent circuit diagram showing a part of a memory cell array formed in a memory cell region of a floating gate type NOR flash memory device. FIG. 2 shows an example of a layout obtained by extracting a part of the cell array of the NOR flash memory device of FIG.

  In the cell array of the NOR type flash memory device shown in FIGS. 1 and 2, memory cell transistors Trm are arranged in a matrix (row direction: X direction, column direction) on a well region formed in a surface layer portion of a silicon substrate 1 as a semiconductor substrate. : Y direction). Each memory cell transistor Trm has an active region (a source / drain diffusion layer and a channel region) 2 formed in a well region, and has a two-layer gate structure (of a floating gate) via a gate insulating film on the well region. And a gate electrode MG having a structure in which a control gate is formed via an inter-gate insulating film.

  In the NOR type cell array, two adjacent memory cell transistors Trm share a drain region, and two adjacent memory cell transistors Trm share a source region. Each column of Trm arranged in the Y direction is separated by an STI (shallow trench isolation) region 3 which is a trench type element isolation region.

  A plurality of word lines WL are arranged in the X direction (row direction) so as to be connected in common to the control electrodes of the memory cell transistors Trm in the same row on the cell array, and are common to the source regions S of the memory cells in the same row. A plurality of local source lines LS are arranged in the X direction (row direction) as common source lines made of metal wirings connected to. As shown in FIG. 2, the local source line LS has a wide upper end and is formed so as to cover a part of the upper surface of the adjacent gate electrode MG.

  In addition, a plurality of bit lines BL made of metal wiring are arranged in the Y direction (column direction) so as to be in common contact with the drain regions of the memory cell transistors Trm in the same column on the cell array, and are connected to the plurality of local source lines LS. A plurality of source lines (main source lines) MS made of common metal wires are intermittently arranged in the Y direction (column direction) in the bit line BL array.

  As described above, the drain shared by two adjacent memory cell transistors Trm is connected to the low-resistance bit line BL via the drain contact DC. Further, a source shared by two adjacent memory cell transistors Trm is connected to a local source line LS existing in parallel with the word line WL between the word lines WL, and the local source line LS has a source line contact. And is connected to a low-resistance main source line MS, and a potential is applied from outside the cell array.

  In the NOR type flash memory having the above configuration, when channel hot electron injection is used to inject electrons into the floating gate electrode in order to write data to the memory cell transistor, a ground potential is applied to the source and well regions of the memory cell transistor Trm. . A desired potential that maximizes the generation efficiency of hot electrons is applied from the external circuit to the control gate and drain via the word line WL and the bit line BL, respectively.

  FIG. 3 shows a longitudinal section of the portion indicated by the line AA in FIG. 2, and shows a section of the gate electrode MG, drain contact DC and local source line LS along the longitudinal direction of the active region 2. . Gate electrodes MG are formed on the surface of the silicon substrate 1 at predetermined intervals via a silicon oxide film 4 as a gate insulating film. The gate electrode MG includes a polycrystalline silicon film 5 for a floating gate electrode, an ONO (Oxide-Nitride-Oxide) film 6 as an inter-gate insulating film, a polycrystalline silicon film 7 for a control gate electrode, and WSi (tungsten silicide). ) A film 8 and a silicon oxide film 9 as a first insulating film are sequentially stacked.

  On the surface layer of the silicon substrate 1 beside the gate electrode MG, an impurity diffusion region 1a is formed corresponding to the drain region, and an impurity diffusion region 1b is formed corresponding to the source region. A silicon oxide film 10 made of a TEOS oxide film or the like and a silicon nitride film 11 as a second insulating film are laminated so as to cover the upper surface and side surfaces of the gate electrode MG and the surface of the silicon substrate 1 between the gate electrodes MG. . In the portion corresponding to the impurity diffusion region 1a (drain region) between the gate electrodes MG, a BPSG film 12 is buried as a silicon oxide film from the bottom to the upper surface of the gate electrode MG.

  The BPSG film 12 is planarized by CMP (chemical mechanical polishing) so as to coincide with the upper surface height of the silicon nitride film 11 covering the upper surface of the gate electrode MG. A silicon oxide film 13 as an interlayer insulating film is laminated on the upper surface of the gate electrode MG and the upper part of the BPSG film 12.

  A drain contact DC is buried in the portion corresponding to the impurity diffusion region 1a from above so as to penetrate the silicon oxide film 13, the BPSG film 12, the silicon nitride film 11, and the silicon oxide film 10 and to contact the impurity diffusion region 1a. Has been. The drain contact DC is composed of a titanium (Ti) film 14 as a barrier metal and a tungsten (W) film 15 as a contact plug.

  A local source line LS is embedded in a portion corresponding to the impurity diffusion region 1b between the gate electrodes MG. Under the local source line LS, the BPSG film 12 between the gate electrodes MG is removed, and the silicon nitride film 11 and the silicon oxide film 10 are removed so that the surface of the impurity diffusion region 1b as the source region is exposed. It is formed in the groove. The upper part of the local source line LS is formed so as to protrude into a portion where the silicon oxide film 10 and the silicon nitride film 11 on the upper surface of the gate electrode MG located on both sides are partially removed and embedded in the portion. . That is, the upper part of the local source line LS is formed so that the width dimension is larger than the width dimension between the gate electrodes located on both sides. The upper part of the local source line LS is buried and formed by the above-described CMP method so that the upper surface thereof coincides with the upper surface of the silicon nitride film 11. The local source line LS has a substantially T-shaped cross section as a whole due to the upper and lower shapes. The local source line LS includes a titanium (Ti) film 14 as a barrier metal and a tungsten (W) film 15 as a contact plug.

  As shown in FIG. 3, a via plug VP formed through the silicon oxide film 13 is formed at a portion of the local source line LS connected to the main source line MSL, and the local source is connected via the via plug VP. The line LS and the main source line MSL are electrically connected. The via plug VP is formed so that its width dimension is smaller than the width dimension of the upper part of the local source line LS. The via plug VP is also composed of a titanium (Ti) film 14 as a barrier metal and a tungsten (W) film 15 as a contact plug.

  Next, the manufacturing process of the said structure is demonstrated. 4 to 11 schematically show a manufacturing process of the NOR type flash memory device, and show a cross section along the direction (Y direction) of the active region 2 in FIG. In the following description, the process of forming the local source line LS and the drain contact DC will be mainly described, and the other processes will be briefly described.

  First, in FIG. 4, after forming necessary wells in the silicon substrate 1, a silicon oxide film 4 as a gate insulating film is formed, and a polycrystalline silicon film 5 for a floating gate electrode, a hard mask, and the like are formed thereon. In the formed state, a trench is formed, and an insulating film is embedded in the trench to form an STI region 3 as an element isolation region. Subsequently, as the remaining layer structure of the gate electrode MG, an ONO film 6 as an inter-gate insulating film, a polycrystalline silicon film 7 as a control gate electrode, a tungsten silicide (WSi) film 8 and a silicon oxide film 9 are formed.

  Next, as shown in FIG. 5, the resist is patterned by a photolithography process, and this is used as a mask, and by a RIE (reactive ion etching) process, a silicon oxide film 9, a tungsten silicide film 8, a polycrystalline silicon film 7, The ONO film 6, the polycrystalline silicon film 5, and the silicon oxide film 4 are removed, and the gate electrode MG is separated and formed. In this state, impurities are introduced by ion implantation into portions corresponding to the source region and the drain region between the gate electrodes MG to form impurity diffusion regions 1a and 1b. The silicon oxide film 4 can be left unremoved.

  Next, as shown in FIG. 6, a silicon oxide film 10 and a silicon nitride film 11 are formed on the entire surface so as to cover the upper and side surfaces of the gate electrode MG formed separately and the impurity diffusion regions 1a and 1b of the silicon substrate 1, respectively. Form. The silicon nitride film 11 functions not only as an etching stopper but also as a CMP stopper.

  Next, as shown in FIG. 7, a BPSG film 12 is buried as an insulating film so as to be buried between the gate electrodes MG. First, a BPSG film 12 is formed on the entire surface of the above structure. The film thickness of the BPSG film 12 is equal to or more than that which can be embedded between the gate electrodes MG. Thereafter, the BPSG film 12 remaining on the gate electrode MG is polished by CMP and planarized using the silicon nitride film 12 as a stopper. Thereby, as shown in FIG. 7, the space between the gate electrodes MG is filled with the BPSG film 12.

  Next, as shown in FIG. 8, etching for forming a groove of the local source line LS is performed by photolithography. First, the resist 16 is patterned to form a strip-shaped opening 16a in the formation region of the local source line LS. The opening 16a is formed on the upper surface of the BPSG film 12 buried on the impurity diffusion region 1b and the gate electrode MG from the end on the impurity diffusion region 1b side of the silicon nitride film 11 on the gate electrode MG located on both sides thereof. It is formed so as to expose up to a portion corresponding to the central portion of the upper surface of. That is, the opening 16a is formed so that its width dimension is larger than the width dimension between the gate electrodes MG adjacent to the impurity diffusion region 1b. The opening 16a is formed in a strip shape in the X direction shown in FIG.

  Subsequently, by performing a wet etching process with an etchant such as hydrofluoric acid (HF), using the silicon nitride film 12 as an etching stopper, the BPSG film 12 filled between the gate electrodes MG exposed in the opening 16a. Is selectively removed.

  Next, as shown in FIG. 9, with the above resist 16 remaining, etching is performed by RIE to remove the exposed silicon nitride film 11 and silicon oxide film 10, and the surface of the impurity diffusion region 1b. To expose. At this time, the silicon nitride film 11 and the silicon oxide film 10 on the upper surface of the gate electrode MG are also removed, and the silicon oxide film 9 formed above the gate electrode MG is exposed.

  Thereby, as a groove for forming the local source line LS, the lower groove 17a in the portion where the silicon nitride film 11 between the gate electrodes MG is opposed, and the silicon oxide film 10 and the silicon nitride film 11 on the upper surface portion of the gate electrode MG are formed. A partially removed upper groove 17b is formed.

  Next, the resist 16 is removed by ashing, and a local source line LS is formed as shown in FIG. In forming the local source line LS, first, a titanium film 14 is formed as a barrier metal layer, and then a tungsten film 15 is formed so as to fill the lower groove 17a. In the impurity diffusion region 1b, an ohmic contact is formed by the tungsten film 15 of the local source line LS. Thereafter, the titanium film 14 and the tungsten film 15 are removed and planarized by CMP treatment using the silicon nitride film 11 as a stopper. As a result, a local source line LS having a T-shaped cross section is formed as shown.

  Next, as shown in FIG. 11, a silicon oxide film 13 is formed on the upper surface of the above structure, and a resist 18 is patterned by photolithography to form openings 18a and 18b, and then contact holes 19 are formed. To do. The silicon oxide film 13 as an interlayer insulating film is formed by a CVD method. In the patterning of the resist 18, an opening 18a for forming the contact hole 19 for the drain contact DC and an opening 18b for the via plug VP for conducting to the local source line LS are formed.

  Etching is performed by the RIE method using the resist 18 as a mask to form the contact hole 19 and the via hole 20 simultaneously. The contact hole 19 is formed so as to penetrate the silicon oxide film 13, the BPSG film 12, the silicon nitride film 11, and the silicon oxide film 10 and reach the surface of the impurity diffusion region 1 a, and the via hole 20 penetrates the silicon oxide film 13. Then, it is formed to reach the upper surface of the local source line LS. In this case, under the etching conditions for forming the contact hole 19, tungsten silicide constituting the local source line LS serves as an etching stopper, and can be formed simultaneously.

  Thereafter, the resist 18 is removed by ashing or the like, and subsequently, the drain contact DC and the via plug VP are formed in the contact hole 19 and the via hole 20 as shown in FIG. Similar to the formation of the local source line LS, a titanium (Ti) film 14 as a barrier metal is formed in the contact hole 10 and the via hole 20, and then the tungsten film 15 is embedded. Thereafter, the titanium film 14 and the tungsten film 15 remaining on the silicon oxide film 13 are removed by polishing by the CMP method, and the whole is flattened. Thereby, the configuration shown in FIG. 3 is obtained.

The actual semiconductor device is formed as a chip of a NOR flash memory device through various well-known manufacturing processes.
According to this embodiment, when patterning the local source line LS, an opening having a width dimension larger than the width dimension between the gate electrodes MG is formed in the resist 16 so that the upper part of the gate electrode MG is partially exposed. 16a is formed, the BPSG film 12 is removed by wet etching, and then the lower groove 17a and the upper groove 17b are formed by dry etching processing. Therefore, even if misalignment occurs in photolithography processing, The local source line LS can be formed without causing a short circuit.

  In addition, by forming the upper portion of the local source line LS formed at this time with a wide shape, it is possible to provide a margin for misalignment of the via plug VP formed on the upper portion, and process capability. Can be improved.

  In addition, since the drain contact DC is formed by performing a photolithography process separately from the local source line LS, it is possible to provide a margin for the displacement of the via hole 20 when forming the contact hole 19 of the drain contact DC. Therefore, the process capability with respect to misalignment may be determined by considering the process of only the drain contact DC, and as a result, the process capability can be improved as a whole, and occurrence of a short circuit with the gate electrode MG can also be suppressed. In other words, it is possible to reduce the limitation of miniaturization in pattern design.

(Other embodiments)
The present invention is not limited to the above embodiment, and can be modified or expanded as follows.

The width dimension of the upper part of the local source line LS can be set to an appropriate width according to the pattern width such as the process capability, the width dimension of the gate electrode MG, and the distance dimension between the gate electrodes MG.
Other barrier metals such as a titanium nitride (TiN) film can be used for the titanium film 14 as the barrier metal constituting the local source line LS, the drain contact DC, and the via plug VP. Also for the tungsten film 15, other conductive films such as copper and aluminum can be used.

1 is an equivalent circuit diagram showing a part of a memory cell array of a NOR type flash memory device showing an embodiment of the present invention; Schematic plan view showing a partial layout pattern of the memory cell region Sectional drawing of the part shown by the cutting line AA in FIG. Schematic cross-sectional view at one stage of the manufacturing process (Part 1) Schematic cross-sectional view at one stage of the manufacturing process (Part 2) Schematic cross-sectional view at one stage of the manufacturing process (Part 3) Schematic cross-sectional view at one stage of the manufacturing process (Part 4) Schematic cross-sectional view at one stage of the manufacturing process (Part 5) Schematic sectional view at one stage of the manufacturing process (No. 6) Schematic cross-sectional view at one stage of the manufacturing process (Part 7) Schematic cross-sectional view at one stage of the manufacturing process (No. 8)

Explanation of symbols

  In the drawings, 1 is a silicon substrate (semiconductor substrate), 3 is an STI region (element isolation region), 4 is a silicon oxide film (gate insulating film), 9 is a silicon oxide film, 10 is a silicon oxide film, and 11 is a silicon nitride film. , 12 is a BPSG film, 13 is a silicon oxide film, 14 is a titanium film, 15 is a tungsten silicide film, 17a is a lower groove, 17b is an upper groove, 19 is a contact hole, 20 is a via hole, MG is a gate electrode, and LS is A local source line (common source line), DC is a drain contact.

Claims (5)

A gate electrode formed on the surface of the semiconductor substrate through a gate insulating film and having a first insulating film on an upper surface portion; and a source region and a drain region formed on a surface layer portion of the semiconductor substrate on both sides of the gate electrode. A plurality of transistors,
An element isolation region for insulatingly separating cell arrays in which a plurality of transistors are arranged in a predetermined number of rows;
A second insulating film formed to cover the upper surface portion and the side wall portion of the gate electrode;
A lower portion that is in electrical contact with the source region and is in contact with the side walls of the gate electrodes of the two transistors facing the source region via the second insulating film, and a part of the upper surface of the two gate electrodes And a common source line electrically connecting in common between the source regions of the transistors formed at adjacent positions via the element isolation region,
A semiconductor device comprising: a plug formed on an upper portion of the common source line so as to be electrically connected to the common source line. The semiconductor device according to claim 1,
The semiconductor device, wherein the second insulating film is a stacked film of an oxide film formed so as to cover the gate electrode and a nitride film formed so as to cover the oxide film. The semiconductor device according to claim 1 or 2,
The semiconductor device according to claim 1, wherein a width dimension of the plug is smaller than a width dimension of the upper portion of the common source line. Forming a plurality of active regions divided into strips in an element isolation region on a semiconductor substrate, forming a gate insulating film in each active region and forming a gate electrode having a first insulating film on an upper surface;
Forming a source region and a drain region by introducing impurities into a surface layer of the semiconductor substrate and sandwiched between the gate electrodes;
Forming a second insulating film on the sidewall and upper surface of the gate electrode and on the surfaces of the source region and the drain region;
Forming a buried insulating film on the semiconductor substrate so as to be buried between the gate electrodes formed with the second insulating film;
The gate electrode and the buried insulating layer are exposed such that a strip-shaped opening pattern having a width dimension larger than the width dimension of the gate electrode located on both sides of the portion corresponding to the source region exposes the portion corresponding to the source region. Forming a resist pattern on the film;
Removing the buried insulating film formed in a portion corresponding to the source region by wet etching using the resist pattern as a mask;
Removing the second insulating film on the semiconductor substrate and the gate electrode exposed by removing the buried insulating film by anisotropic dry etching using the resist pattern as a mask;
Forming a common source line by burying a conductor in a portion where the second insulating film is removed;
A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device according to claim 4,
In the step of forming the second insulating film, a stacked film of an oxide film and a nitride film is formed so as to cover the gate electrode.

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