JP2008044096A - Microelectromechanical device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To manufacture a microstructure and an electric circuit included in a microelectromechanical device over the same insulating surface in the same step. <P>SOLUTION: In the microelectromechanical device, the electric circuit including a transistor and the microstructure are integrated over a substrate having an insulating surface. The microstructure and the transistor are provided with a laminate of an insulating layer and a semiconductor layer. That is, a structural layer includes a layer formed of the same insulating film as the gate insulating layer and a layer formed of the same semiconductor film as the semiconductor layer of the transistor. Further, the microstructure is manufactured by using each of conductive layers used for a gate electrode, a source electrode, and a drain electrode of the transistor as a sacrificial layer. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a microelectromechanical device (microelectromechanical system) formed on an insulating substrate and a manufacturing method thereof. In particular, the present invention relates to a micromechanical structure of a microelectromechanical device and a manufacturing method thereof.

  In recent years, research on micro mechanical systems called MEMS has been actively conducted. MEMS is an abbreviation for Micro Electro Mechanical System and is translated as a microelectromechanical device, a microelectromechanical system, or the like. Also, it is sometimes called a micromachine in Japan, and sometimes called MST (Micro System Technology) in Europe or the like. In this specification, MEMS is also referred to as a micromachine or a microelectromechanical device. The MEMS refers to an electronic device in which a fine mechanical part composed of a “movable microstructure having a three-dimensional structure” and an “electric circuit having a semiconductor element” for controlling the mechanical part are combined. In addition, MEMS is sometimes simply called a micromachine.

  Since MEMS can control its own microstructure with an electric circuit, it can construct an autonomous distributed type system instead of a central processing control type as in a conventional device using a conventional computer. Expected. For example, the information obtained by the sensor can be processed by an electric circuit, and an actuator or the like can be driven by the MEMS in accordance with the processing information.

  A lot of research has been done on micromachines. For example, Patent Document 1 proposes an improved MEMS wafer level package, with the problem that the manufacturing process cannot be compatible with wafer manufacturing and plastic assembly facilities. Patent Document 2 describes that the layers constituting the structure cause desirable mechanical characteristics by controlling laser irradiation.

However, as described in Patent Document 1, a microstructure constituting a micromachine is manufactured by a process for manufacturing a semiconductor element using a silicon wafer. In particular, in order to obtain a material having a thickness and strength sufficient for manufacturing a microstructure, a micromachine that is put into practical use is mainly manufactured using a silicon wafer. Further, Patent Document 2 only describes a cantilever that is a microstructure, and there is no description about integrating the microstructure and an electric circuit.
JP 2001-144117 A Japanese Patent Application Laid-Open No. 2004-1201

  It is an object of the present invention to provide a microelectromechanical device in which a microstructure and an electric circuit for controlling the microstructure are integrated on the same substrate, and a manufacturing method thereof.

  A microelectromechanical device according to the present invention has a microstructure and an electric circuit for controlling the microstructure on an insulating surface. The electric circuit is electrically connected to the microstructure and includes a transistor. The microstructure includes at least a structural layer that is not fixed to the substrate and a structural layer that is partially fixed to the substrate. That a part of the structural layer is fixed to the substrate means that a part of the structural layer is not fixed to the substrate. In other words, a part of the structural layer is fixed to the substrate, so that a space is formed between the substrate and the other part of the structural layer. The structural layer is movable with respect to the substrate. At least one of the structural layers constituting the microstructure is completely separated from the substrate and is formed to be movable with respect to the substrate. Further, the movable range of this structural layer is limited by another structural layer fixed to the substrate. For example, the structure layer completely separated from the substrate is used as a rotor, and the structure layer serving as the rotation axis of the rotor is fixed to the substrate. With such a structure, the movable layer of the structural layer serving as the rotor is limited by the structural layer serving as the rotation axis.

  One of the microelectromechanical devices of the present invention is characterized in that the microstructure includes a layer having the same stacked structure as the stacked structure of the gate insulating layer and the semiconductor layer of the transistor as the first and second structural layers. To do. In other words, the microstructure has a structure layer including a layer formed from the same insulating film as the gate insulating layer and a layer formed from the same semiconductor film as the semiconductor layer of the transistor.

  One of the microelectromechanical devices of the present invention is characterized in that the semiconductor layer included in the microstructure has a multilayer structure and the crystal structure of the layers is different. By doing in this way, since the defect of a mutual layer is supplemented, destruction of a microstructure can be suppressed.

  One of the microelectromechanical devices of the present invention is characterized in that a structure layer of a microstructure includes a compound of a semiconductor and a metal such as silicide. Thus, the strength of the structural layer can be increased as compared with that of polycrystalline silicon, and the conductivity can be increased.

  One of the methods for manufacturing a microelectromechanical device of the present invention is characterized in that a layer formed from the same film as the gate electrode is used as a sacrificial layer in order to provide a movable portion in the structure body. .

In the microelectromechanical device of the present invention, the microstructure and the electrical circuit that controls the microstructure are integrally formed on the same insulating surface, so that the mechanical connection portion of the electrical circuit and the microstructure is mechanically connected. High strength and poor connection failure.
Also provided is a micro electro mechanical device in which a micro structure and an electric circuit for controlling the micro structure are integrally formed on the same insulating surface through the same process by the method for manufacturing the micro electro mechanical device of the present invention. can do. In other words, there is no separation of steps such as manufacturing a microstructure after manufacturing an electric circuit or manufacturing an electric circuit after manufacturing a microstructure. Therefore, the manufacturing method is simplified, and as a result, the cost of the micro mechanical device is reduced.

  Embodiments of the present invention will be described below with reference to the drawings. However, the present invention is not limited to the following description. Various changes in form and details may be made without departing from the spirit and scope of the invention. Therefore, the present invention is not construed as being limited to the following embodiments and examples.

  Note that, in different embodiments, elements denoted by the same reference numerals indicate the same components, and repeated descriptions are omitted.

(Embodiment 1)
In this embodiment, a method for manufacturing a microstructure and an electric circuit for controlling the microstructure at the same time on the same substrate will be described. 1A and 1B are diagrams illustrating the structure of the MEMS of the present embodiment, FIG. 1A is a cross-sectional view of the MEMS, and FIG. 1B is a top view of a microstructure. A cross-sectional view taken along the chain line OP in FIG. 1B corresponds to the cross-sectional view of the microstructure 11 in FIG. Note that in FIG. 1A, the left side is a cross-sectional view of a first region where a microstructure is formed, and the right side is a cross-sectional view of a second region where an electric circuit is formed. This also applies to the cross-sectional views shown in FIGS. In FIG. 1A, the cross-sectional structure of the electric circuit 10 in the second region typically shows a transistor, and this is the same in other embodiments.

  The electric circuit 10 and the microstructure 11 are provided on the substrate 100 having the same insulating surface. The transistor of the electric circuit 10 is a thin film transistor, and its structure is a bottom gate type. The transistor includes a first conductive layer 101, a first insulating layer 102 over the first conductive layer 101, a semiconductor layer 103 over the first insulating layer 102, and a second conductive layer 104 over the semiconductor layer 103.

  The first conductive layer 101 forms a gate electrode or a gate wiring of a transistor. The first insulating layer 102 constitutes a gate insulating layer. In the semiconductor layer 103, at least a channel formation region and a high-concentration impurity region functioning as a source region or a drain region are formed. The second conductive layer 104 is connected to the high concentration impurity region of the semiconductor layer 103 and functions as a source electrode or a drain electrode.

  A second insulating layer 105 is formed so as to cover the transistor. A third conductive layer 106 is formed on the second insulating layer 105. The third conductive layer 106 is connected to the second conductive layer 104 through a contact hole formed in the second insulating layer 105.

  The electrode, wiring, and terminal of the electric circuit 10 are formed using the first conductive layer 101, the second conductive layer 104, and the third conductive layer 106. The microstructure 11 and the electric circuit 10 are electrically connected by electrodes and wirings formed of the first conductive layer 101, the second conductive layer 104, and the third conductive layer 106. In addition, elements other than transistors are formed in the electric circuit 10. For example, by using the semiconductor layer 103, an MIS capacitor or a diode can be formed.

  As shown in FIG. 1A, the microstructure 11 is formed in the opening 107 formed in the second insulating layer 105. The microstructure 11 includes a movable electrode 121 (first structure layer), twelve fixed electrodes 122 (second structure layer) fixed to the substrate 100, and a wiring 123 connected to the fixed electrode 122. The movable electrode 121 is a so-called rotor (rotor), and the fixed electrode 122 is a so-called stator (stator). The wiring 123 is connected to the electric circuit 10. The wiring 123 is formed integrally with the fixed electrode 122. In other words, a part of the wiring 123 forms the fixed electrode 122. Therefore, the fixed electrode 122 and the wiring 123 can be regarded as the second structure layer.

  The shape of the movable electrode 121 is a disk shape, is formed with four openings 121 a, and is separated from the substrate 100.

  The twelve fixed electrodes 122 are arranged in an arc shape surrounding the movable electrode 121. The fixed electrode 122 is fixed to the substrate 100, but the tip (the end close to the movable electrode 121) is separated from the substrate 100 so that an electrostatic force can act on the movable electrode 121 at a distance from the substrate. It has become.

  The movable electrode 121, the fixed electrode 122, and the wiring 123 have a multilayer structure, the lower layer is an insulating layer, and the upper layer is a conductive layer. The lower insulating layer is in the same layer as the first insulating layer 102 of the transistor, and is formed from the same insulating film as the first insulating layer 102. The upper conductive layer is in the same layer as the semiconductor layer 103 of the transistor and is formed from the same semiconductor film as the semiconductor layer 103.

  By connecting the twelve fixed electrodes 122 in parallel by the wiring 123 every three, the microstructure 11 can function as a three-phase four-pole motor. By sequentially applying a voltage to the three-phase fixed electrode 122, an electrostatic force (electrostatic attractive force) is generated between the movable electrode 121 and the fixed electrode 122. The movable electrode 121 is rotated by the electrostatic force. The rotation direction of the movable electrode 121 can be controlled by the voltage applied to the fixed electrode 122.

  Hereinafter, a method for manufacturing the MEMS illustrated in FIG. 1 will be described with reference to FIGS. Here, the microstructure 11 is formed in the first region and the electronic circuit 10 is formed in the second region. First, a substrate having an insulating surface is prepared as the substrate 100. A conductive film is formed over the substrate 100 and processed into a predetermined shape by a photolithography process and an etching process, so that first conductive layers 101 and 131 are formed as illustrated in FIG. That is, the same conductive film formed over the substrate 100 is patterned to form the first conductive layers 101 and 131. A process for processing a film into a predetermined shape by a photolithography process and an etching process is also called patterning. A first insulating layer 132 is formed on the first conductive layers 101 and 131.

As the substrate having an insulating surface, an insulating substrate such as a glass substrate, a quartz substrate, or a plastic substrate, or an insulating substrate having an insulating film formed on the surface can be used. In addition, a conductive substrate such as a silicon wafer, metal, or stainless steel having an insulating film formed on the surface can also be used.

The insulating film formed on the substrate surface is made of a material selected from silicon oxide, silicon nitride, silicon oxynitride (SiO _x N _y , x> y), silicon nitride oxide (SiO _x N _y , x <y), and the like. It can be formed of a layer film or a multilayer film. These films can be formed by CVD or sputtering. In the case of a silicon wafer or a metal substrate, the surface can be nitrided or oxidized to form nitrides or oxides.

  The material of the first conductive layers 101 and 131 includes molybdenum (Mo), tungsten (W), chromium (Cr), tantalum (Ta), titanium (Ti), aluminum (Al), and other metal elements, and these metal elements. A metal compound (for example, titanium nitride, tungsten nitride) having a main component, an alloy (for example, an alloy of aluminum and titanium, an alloy of chromium and molybdenum), or the like having such a metal as a main component can be selected. These materials can be formed by an evaporation method or a sputtering method, and the first conductive layers 101 and 131 are formed using a single layer film or a multilayer film of these materials.

  The first conductive layer 131 is a sacrificial layer, and the shape of the structural layer (the movable electrode 121, the fixed electrode 122, and the wiring 123) of the microstructure 11 is defined by the shape of the first conductive layer 131. As shown in FIG. 4, the first conductive layer 131 is formed in a disk shape. In the electric circuit 10, in addition to the gate electrode (gate wiring), an electrode, a wiring, a terminal, and the like constituting the electric circuit 10 can be formed by the first conductive layer 101.

Since the first insulating layer 132 forms a gate insulating film of the transistor, a material suitable for the gate insulating film is selected. For example, a single layer film or a multilayer film of a material selected from silicon oxide, silicon nitride, silicon oxynitride (SiO _x N _y , x> y), silicon nitride oxide (SiO _x N _y , x <y), etc. can do.

  Next, the semiconductor layer 133 is formed over the first insulating layer 132. The semiconductor layer 133 can be formed using silicon, germanium, or a compound of silicon and germanium (silicon germanium). In this embodiment, the semiconductor layer 133 is formed of a crystalline semiconductor. A crystalline semiconductor film can be formed by depositing an amorphous semiconductor by a CVD method or a sputtering method and crystallizing the amorphous semiconductor film by applying light energy or thermal energy. Alternatively, a microcrystalline or polycrystalline semiconductor can be formed by a CVD method or a sputtering method. In the latter case, after film formation, crystallization (or improvement in crystallinity) can be performed by applying light energy or heat energy.

For example, in order to form amorphous silicon, a film may be formed by a CVD method using a source gas obtained by diluting a silane (SiH ₄ ) gas with hydrogen. Alternatively, it can be formed by a sputtering method using a target made of silicon. Amorphous germanium can be formed by CVD using a source gas obtained by diluting germane (GeH ₄ ) gas with hydrogen, or by sputtering using a target made of germanium. You can also In order to form amorphous silicon germanium, a film can be formed by a CVD method using a source gas in which monosilane (SiH ₄ ) gas and germane (GeH ₄ ) gas are mixed at a predetermined ratio and diluted with hydrogen. Alternatively, a film can be formed by sputtering using two types of targets, silicon and germanium.

In the film formation by the CVD method, a rare gas such as helium gas, fluorine gas, Ar, Kr, or Ne can be added to the source gas in addition to hydrogen gas. Further, instead of monosilane (SiH ₄ ) gas, Si ₂ H ₆ , SiH ₂ Cl ₂ , SiHCl ₃ , SiCl ₄ , SiF ₄ or the like can be used as the source gas. Alternatively, a microcrystalline or polycrystalline semiconductor can be directly formed over the insulating layer 132 by a plasma CVD method using the above source gas. In film formation by sputtering, a microcrystal or a polycrystalline semiconductor can be formed by controlling the substrate temperature or the like.

  As a method for crystallizing an amorphous semiconductor film, a method of irradiating a laser beam, a method of irradiating infrared rays, a method of heating with an electric furnace, a metal element that promotes crystallization of a semiconductor is introduced into the semiconductor film. Examples thereof include a crystallization method.

As a laser used for crystallization, both a continuous wave laser (CW laser) and a pulsed laser (pulse laser) can be used. Examples of a gas laser suitable for crystallization include an Ar laser, a Kr laser, and an excimer laser. In the case of a solid-state laser, YAG, YVO ₄ , YAlO ₃ , GdVO ₄ , forsterite (Mg ₂ SiO ₄ ), etc. containing dopants (eg, Nd, Yb, Cr, Ti, Ho, Er, Tm, Ta) And a laser using the above crystal as a medium, a glass laser, a ruby laser, an alexandrite laser, and a Ti: sapphire laser.

In order to crystallize a semiconductor, not only the fundamental wave of the beam oscillated from these lasers but also the second to fourth harmonic beams of the fundamental wave can be irradiated. For example, a second harmonic (532 nm) or a third harmonic (355 nm) of an Nd: YVO ₄ laser (fundamental wave 1064 nm) can be used. Energy density of the laser is required 0.01 mW / cm ² or more 100 MW / cm ² or less, preferably in the range of a 0.1 MW / cm ² or more 10 MW / cm ² or less. The scanning speed may be in the range of 10 cm / sec to 200 cm / sec.

  Solid-state lasers such as YAG, Ar ion lasers, and Ti: sapphire lasers that use the above crystal as a medium can oscillate continuously, with Q-switch operation, mode synchronization, etc., at an oscillation frequency of 10 MHz or higher. It is also possible to cause pulse oscillation. When the laser beam is oscillated at an oscillation frequency of 10 MHz or more, the semiconductor film can be irradiated with the next pulse during the period from when the semiconductor film is melted by the laser beam to solidification. Therefore, by scanning the laser beam, the solid-liquid interface generated by irradiating the laser beam can be continuously moved, so that the crystal grains of the semiconductor film can be grown longer in the scanning direction. .

  Alternatively, the semiconductor film can be crystallized by irradiation with infrared light, visible light, or ultraviolet light using a lamp as a light source instead of a laser beam. As the lamp, a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, or a high pressure mercury lamp is typically used. The light irradiation with the lamp is repeated 1 to 10 times, preferably 2 to 6 times. In one-time irradiation, the lamp is operated for 1 second to 60 seconds, preferably 30 seconds to 60 seconds, so that the semiconductor film is instantaneously heated at a temperature of 600 ° C. to 1000 ° C. To do.

  When an electric furnace is used for the heat treatment, if the semiconductor is amorphous silicon using silane as a source gas, a heating step of about 400 ° C. is first performed to release hydrogen in the silicon, and then The temperature is preferably raised to a temperature at which amorphous silicon crystallizes. Such heat treatment can reduce film roughness during crystallization.

  As a method for forming a crystalline semiconductor, there is a method of crystallizing using a metal element that promotes crystallization. This method is particularly suitable for crystallizing an amorphous silicon film. By introducing a metal element that promotes crystallization of an amorphous silicon film into a semiconductor and performing heat treatment with laser beam irradiation or an electric furnace at 500 ° C. to 600 ° C., the continuity of crystal grains at grain boundaries can be improved. A highly crystalline semiconductor can be obtained. Metal elements that promote crystallization of silicon include iron (Fe), nickel (Ni), cobalt (Co), ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir) One or more kinds of metal elements selected from platinum (Pt), copper (Cu), and gold (Au) can be used. Crystallization using a metal element can be applied not only to amorphous silicon but also to crystallization of amorphous silicon germanium having germanium in an amount of about 0.01 to 4.5 atomic%.

  The means for introducing these metal elements into the semiconductor is not particularly limited as long as it is a technique capable of causing the metal elements to exist on the surface of the semiconductor or inside thereof. For example, a sputtering method, a CVD method, a plasma processing method (including a plasma CVD method), an adsorption method, or a method of applying a metal salt solution can be used. Among these, the method using the solution is simple and the concentration of the metal element introduced into the semiconductor can be easily adjusted. In order to apply the solution, it is preferable to improve the wettability of the surface of the semiconductor in order to spread the solution over the entire surface of the semiconductor. In order to improve wettability, it is desirable to form an extremely thin oxide film of 10 nm or less on the surface of the amorphous semiconductor. Such an extremely thin oxide film can be formed by UV light irradiation treatment in an oxygen atmosphere, thermal oxidation treatment, treatment with hydrogen peroxide, treatment with ozone water containing a hydroxyl radical, or the like.

  Crystalline silicon crystallized using a metal element, like single crystal silicon, is characterized by being continuous without breaking silicon element bonds at crystal grain boundaries. Due to such characteristics of the crystal structure, the toughness is higher than that of polycrystalline silicon produced by crystallization without using a metal element. This is because stress concentration caused by defects in the crystal grain boundaries does not occur, and as a result, the fracture stress is higher than that of polycrystalline silicon crystallized without using a metal element. Further, since the atomic mobility is large due to the continuous bonding of atoms at the crystal grain boundary, it is suitable as a material for the structural layer of the microstructure controlled by electrostatic force (electrostatic attractive force). Needless to say, such crystalline silicon can be applied to a microstructure controlled by electromagnetic force.

  A metal element such as nickel used for crystallization is bonded to silicon to form silicide. It is known that metal compounds such as nickel silicide are stronger than silicon. Therefore, a metal element may be introduced so that silicide is formed in the structural layer.

  On the other hand, since the metal element used for crystallization deteriorates the characteristics of the elements of the electric circuit 10, the metal element introduced is at least in the region (second region) where the electric circuit 10 is formed after crystallization. Is desirably removed from the semiconductor layer 133. The method will be described below.

  First, by treating the surface of crystalline silicon with an ozone-containing aqueous solution (typically ozone water), a barrier layer made of an oxide film (called chemical oxide) is formed on the surface of the crystalline semiconductor film with a thickness of 1 nm to 10 nm. Form with thickness. The barrier layer functions as an etching stopper when only the gettering layer is selectively removed in a later step.

Next, a gettering layer containing a rare gas element is formed as a gettering site on the barrier layer. Here, a semiconductor film containing a rare gas element is formed as a gettering layer by a CVD method or a sputtering method. When forming the gettering layer, the sputtering conditions are adjusted as appropriate so that a rare gas element is added to the gettering layer. As the rare gas element, one or more selected from helium (He), neon (Ne), argon (Ar), krypton (Kr), and xenon (Xe) can be used. Note that, during gettering, the metal element tends to move to a region having a high oxygen concentration. Therefore, the oxygen concentration contained in the gettering layer is preferably set to 5 × 10 ¹⁸ cm ⁻³ or more, for example.

  Next, the crystalline silicon film, the barrier layer, and the gettering layer are subjected to heat treatment (for example, heat treatment using an electric furnace or laser beam irradiation treatment), so that the metal element is removed from the crystalline silicon and the crystallinity is increased. The concentration of the metal element in the silicon film can be reduced.

  Next, as shown in FIG. 2C, a photolithography process and an etching process are performed on the semiconductor layer 133 and the first insulating layer 132, and each is processed into a predetermined shape. From the semiconductor layer 133, the semiconductor layer 103 of the transistor, the semiconductor layer 134 that is part of the first structure layer, and the semiconductor layer 135 that is part of the second structure layer are formed. The first insulating layer 132 is processed into the same shape as the semiconductor layers 103, 134, and 135, the first insulating layer 102 serving as a gate insulating film of the transistor is formed in the second region, and the first region is formed in the first region. An insulating layer 126 that becomes a part of the structural layer and an insulating layer 127 that becomes a part of the second structural layer are formed. FIG. 5 is a top view of the microstructure 11 in FIG. A cross section taken along the chain line OP in FIG. 5 is shown in FIG.

  By this step, the shapes of the first and second structural layers of the microstructure 11 are determined. A stacked body of the insulating layer 127 and the semiconductor layer 135 formed in a circle forms the movable electrode 121, and a stacked body of the insulating layer 126 and the semiconductor layer 134 forms the fixed electrode 122 and the wiring 123. The movable electrode 121 is a first structure layer that is not fixed to the substrate 100 and is finally separated from the substrate 100. Therefore, the entire stacked body including the insulating layer 126 and the semiconductor layer 134 is disposed on the upper surface of the first conductive layer 131 serving as a sacrificial layer. Moreover, the 1st structure layer formed circularly may have the opening part 134a, as shown in FIG. The fixed electrode 122 is a second structure layer having a portion separated from the substrate 100 at the tip and a portion fixed to the substrate 100. In order to form such a fixed electrode 122, the front end of the stacked body including the insulating layer 127 and the semiconductor layer 135 is formed so as to cover the upper surface and the side surface of the first conductive layer 131, and the other part is the surface of the substrate 100. It is formed in contact with (insulating surface).

  Next, as illustrated in FIG. 2D, an impurity imparting conductivity to the semiconductor layer 103 is selectively formed by a doping method or an ion implantation method in order to form an n-type or p-type high concentration impurity region. Added. Phosphorus (P) or arsenic (As) is used as the impurity element imparting n-type, and boron (B) is used as the impurity element imparting p-type. In order to add an impurity to a portion other than the first conductive layer 101 to be a gate electrode, a region to which no impurity is added is covered with a resist mask by using a photolithography method, and the impurity may be added. By this step, a high concentration impurity region 103b is formed in the semiconductor layer 103, and a region on the first conductive layer 101 to which no impurity is added is determined as the channel formation region 103a.

  In addition, in the first region, the semiconductor layer 134 that forms the first structure layer and the semiconductor layer 135 that forms the second structure layer are added with impurities in the same manner, thereby imparting conductivity, so that the conductive layers 128, 129 is formed. Accordingly, the first structure layer can function as the movable electrode 121, and the second structure layer can function as the fixed electrode 122 and the wiring 123.

  Next, a conductive film is formed by a sputtering method or the like, and the shape of the conductive film is processed by a photolithography process and an etching process, so that a second conductive layer 104 is formed in the second region as illustrated in FIG. Then, the second conductive layer 137 is formed on the microstructure 11. In the second region, in addition to the electrode (wiring) connected to the high-concentration impurity region 103b, an electrode, a wiring, a terminal, and the like constituting the electric circuit 10 are formed by the second conductive layer 104.

  The second conductive layer 137 is formed to protect the first structure layer and the second structure layer so as not to be removed by etching when the opening 107 is formed in the second insulating layer 105 described later. Formed in the region. Further, since the second conductive layer 137 is finally removed, it is also a sacrificial layer (second sacrificial layer). The second conductive layer 137 is shaped to cover at least a portion of the structural layer (126 to 129) where the opening 107 is formed. Of course, the portion of the structural layer (126 to 129) that covers the portion that exists in the region where the second insulating layer 105 is left may be in the second conductive layer 137. In this case, the wiring 123 of the microstructure 11 partially has a stacked structure of the insulating layer 127, the conductive layer 129, and the second conductive layer 137.

  The material of the second conductive layers 104 and 137 can be selected from the same materials as the first conductive layers 101 and 131, and the second conductive layers 104 and 137 are formed of a single layer film or a multilayer film of these materials. . Note that since the second conductive layer 137 is formed so as to cover the conductive layers 128 and 129 made of a semiconductor, the second conductive layer 137 is made of a material containing a metal element that can form a metal compound by reacting with silicon or germanium. Use it. Examples of such a metal element include refractory metals such as tungsten, titanium, molybdenum, and tantalum, cobalt, nickel, and the like.

  In this case, after the second conductive layer 137 is formed, heat treatment is performed, whereby the second conductive layer 137 can be reacted with a metal element so that the conductive layers 128 and 129 are formed of a metal compound. If the conductive layers 128 and 129 are silicon, a silicide layer can be formed. When the conductive layers 128 and 129 are made of a metal compound such as silicide, both conductivity and strength can be improved. Alternatively, part of the conductive layers 128 and 129 can be a metal compound. As the heat treatment for forming the metal compound, heat treatment using an electric furnace, irradiation treatment with a laser beam or lamp light can be used.

  In the case where the conductive layers 128 and 129 can be made to have a necessary electrical conductivity by using a metal compound such as silicide, in the process of FIG. 2D, the semiconductor layers 134 and 135 are n-type or p-type. The impurities may not be added.

  Next, as shown in FIG. 3A, a second insulating layer 105 is formed. In the second region, after forming a contact hole in the second insulating layer 105, a conductive film is formed over the second conductive layer 104, and the conductive film is formed into a predetermined shape by a photolithography process and an etching process. The third conductive layer 106 is formed in the electric circuit 10 by processing. In the electric circuit 10, wirings and the like other than the wirings connected to the transistors are formed by the third conductive layer 106.

The second insulating layer 105 is an interlayer insulating film that separates the third conductive layer 106 and the second conductive layer 104 between layers, and can also function as a sealing layer that seals the electric circuit 10. As the second insulating layer 105, an inorganic insulating film such as silicon oxide, silicon nitride, silicon oxynitride (SiO _x N _y x> y), silicon nitride oxide (SiO _x N _y x <y), or the like can be used. Alternatively, an organic resin film such as polyimide or acrylic, or a film containing siloxane may be used. The organic resin may be photosensitive or non-photosensitive. The second insulating layer 105 can be a single-layered layer or a multilayered layer made of these insulating materials. For example, the first layer can be an inorganic insulating film made of silicon nitride, and the second layer can be an organic resin film such as polyimide. Note that siloxane is a material in which a skeleton structure is formed by a bond of silicon (Si) and oxygen (O), and includes an organic group (for example, an alkyl group or an aryl group) as a substituent. Moreover, the fluoro group may be included as a substituent.

  The third conductive layer 106 can be formed in the same manner as the first conductive layers 101 and 131 or the second conductive layers 104 and 137. However, since the first conductive layer 131 and the second conductive layer 137 are removed by etching, a material that cannot be removed by an etchant that removes the first conductive layer 131 and the second conductive layer 137 is selected for the third conductive layer 106. There is a need.

After forming the third conductive layer 106, as shown in FIG. 3B, an opening 107 is formed in the region of the second insulating layer 105 where the microstructure 11 is formed, and the second conductive layer 137 is formed. To expose. At this time, since the microstructure 11 is protected by the second conductive layer 137, the microstructure 11 may include a layer formed using a material having a low etching selectivity with respect to the second insulating layer 105. . For example, the same material as the second insulating layer 105 may be used for the first insulating layers 126 and 127.
Further, when the sacrificial layer etching is performed, the first structure layer which is the movable electrode 121 is not fixed anywhere on the substrate 100. If sacrificial layer etching is performed in such a state, the first structure layer may be lost. In order to prevent this, it is desirable to provide the opening 107 not in the entire first region but in a part of the first region. For example, the opening 107 can be formed in the same place as the opening 134a provided in the semiconductor layer 134 which is the first structure layer shown in FIG. Further, the opening 107 can be formed slightly wider than the opening 134a where the opening 134a is formed.

  Next, so-called sacrificial layer etching is performed in which the second conductive layer 137 (second sacrificial layer) and the first conductive layer 131 (first sacrificial layer) are removed by etching. When the sacrificial layer etching is completed, the microstructure 11 shown in FIG. 1 is completed. The opening 121a formed in the movable electrode 121 is provided to allow the etching agent to reach the first sacrificial layer 131 during the sacrificial layer etching. As a method for etching the second conductive layer 137 and the first conductive layer 131, either a wet etching method or a dry etching method can be used, and an etching agent is selected according to the material constituting the layer.

  For example, when the first conductive layer 131 and the second conductive layer 137 (sacrificial layer) are tungsten (W), a solution in which 28% ammonia and 31% hydrogen peroxide water are mixed in an etchant at a ratio of 1: 2. Can be used. When these sacrificial layers are aluminum, a mixed acid of nitric acid and phosphoric acid can be used as an etching agent.

Depending on the material of the sacrificial layer, the sacrificial layer can be etched by dry etching using a gas of F ₂ or XeF _{2 under} a high pressure condition such as atmospheric pressure.

  In addition, when drying after wet etching, in order to prevent the microstructure from buckling due to capillarity, rinsing is performed using a low-viscosity organic solvent (for example, cyclohexane), or drying is performed under low-temperature and low-pressure conditions, or both. It is better to perform a process that combines

  As described above, according to the present invention, a microstructure including a rotor and an electric circuit can be formed over a substrate having an insulating surface. Therefore, the mechanical strength of the connection portion between the electric circuit and the microstructure is high, and connection failure hardly occurs. Further, there is no process for integrating the microstructure and the electric circuit later, and the manufacturing cost can be reduced.

(Embodiment 2)
In this embodiment, a method for manufacturing a microstructure and an electric circuit for controlling the microstructure at the same time on the same substrate will be described. 6A and 6B are diagrams showing the structure of the MEMS of this embodiment, FIG. 6A is a cross-sectional view of the MEMS, and FIG. 6B is a top view of the microstructure. Note that in FIG. 6A, the left side is a cross-sectional view of a first region where a microstructure is formed, and the right side is a cross-sectional view of a second region where an electric circuit is formed. This also applies to the cross-sectional views shown in FIGS.

  In the MEMS of this embodiment mode, the electric circuit 20 and the microstructure 21 are provided over the same substrate 100. Although the transistor of the electric circuit 20 is a bottom-gate thin film transistor, the structure of the semiconductor layer 203 is different from that of Embodiment Mode 1. Further, the point that the microstructure 21 has a rotor (rotor) and a stator (stator) is the same as that of the first embodiment, but is different in that it has a rotation axis (third structure layer). The structure of the MEMS of this embodiment will be specifically described with reference to FIG.

  The electric circuit 20 and the microstructure 21 are provided on the same substrate 100 (on the same insulating surface). The thin film transistor of the electric circuit 20 is on the first conductive layer 101 and the first conductive layer 101 constituting the gate electrode or gate wiring of the transistor, and on the first insulating layer 102 and the first insulating layer 102 constituting the gate insulating layer. The semiconductor layer 203 and the second conductive layer 104 over the semiconductor layer 203.

  The semiconductor layer 203 has a two-layer structure, a semiconductor layer in which a channel formation region is formed, and an n-type or p-type conductive layer that is stacked over the semiconductor layer and functions as a source region or a drain region (high-concentration impurity region). A semiconductor layer (conductive layer) exhibiting properties. Hereinafter, the former will be described as a first semiconductor layer and the latter as a second semiconductor layer. A second conductive layer 104 is formed over the second semiconductor layer of the semiconductor layer 203, is connected to the second semiconductor layer, and functions as a source electrode or a drain electrode.

  In the electric circuit 20, a second insulating layer 105 is formed so as to cover the second conductive layer 104, the semiconductor layer 203, the first insulating layer 102, and the first conductive layer 101. A third conductive layer 106 is formed on the second insulating layer 105. The third conductive layer 106 is connected to the second conductive layer 104 through a contact hole formed in the second insulating layer 105.

  The electrodes, wirings, and terminals of the electric circuit 20 are formed using the first conductive layer 101, the second conductive layer 104, and the third conductive layer 106. In the electric circuit 20, elements other than transistors are also formed. For example, the capacitor can be formed using the n-type semiconductor layer of the semiconductor layer 203, the first insulating layer 102, and the first conductive layer 101.

  As shown in FIG. 6B, the microstructure 21 includes a movable electrode 221 (first structure layer), twelve fixed electrodes 222 (second structure layer) fixed to the substrate 100, and a fixed electrode 222. And a rotating shaft 225 (third structure layer) fitted in the center of the movable electrode 221. The movable electrode 221 is a so-called rotor (rotor), and the fixed electrode 222 is a so-called stator (stator). By sequentially applying a voltage to the three-phase fixed electrode 222, the movable electrode 221 rotates around the rotation shaft 225 by electrostatic attraction generated between the movable electrode 221 and the fixed electrode 222. The rotation direction of the movable electrode 221 can be controlled by a voltage applied to the fixed electrode 222.

  The structure of the fixed electrode 222 and the wiring 223 is the same as that of the fixed electrode 122 and the wiring 123 of Embodiment 1 except that the laminated structure of the structural layers constituting the electrodes and the wiring is different. The fixed electrode 222 and the wiring 223 are integrated. Is formed. The fixed electrode 222 and the wiring 223 can be regarded as the second structure layer.

  The shape of the movable electrode 221 is a shape in which four T-shaped layers (a shape having a wide tip) are provided symmetrically around the disk. When viewed from the top, the movable electrode 221 has a cross-shaped appearance, and the outer periphery of the movable electrode 221 forms an arc.

  The movable electrode 221, the fixed electrode 222, and the wiring 223 have a multi-layer structure. The lower layer is an insulating layer and the upper layer is a semiconductor layer. The lower insulating layer is in the same layer as the first insulating layer 102 of the transistor, and is formed from the same insulating film as the first insulating layer 102. The upper semiconductor layer is in the same layer as the semiconductor layer 203 of the transistor, has a two-layer structure of the same first semiconductor layer and second semiconductor layer (conductive layer) as the semiconductor layer 203, and is formed from the same semiconductor film as the semiconductor layer 203. Is done.

  The rotation shaft 225 is fixed to the substrate 100 through an opening formed at the center of the movable electrode 221. The tip of the rotating shaft 225 is larger than the opening of the movable electrode 221 so that the movable electrode 221 cannot be removed. Note that the position where the rotation shaft 225 is provided need not be the center of the movable electrode 221. When the microstructure 21 is desired to be used as a rotor, the position where the rotation shaft 225 is provided can be removed from the center.

  Hereinafter, a method for manufacturing the MEMS illustrated in FIG. 6 will be described with reference to FIGS. In addition, the description which overlaps with Embodiment 1 is abbreviate | omitted, and description of Embodiment 1 is used.

  First, similarly to Embodiment Mode 1, a substrate having an insulating surface is prepared as the substrate 100. A conductive film is formed over the substrate 100 and processed into a predetermined shape by a photolithography process and an etching process, so that first conductive layers 101 and 131 are formed as illustrated in FIG. A first insulating layer 132 is formed on the first conductive layers 101 and 131.

  In the electric circuit 20, other electrodes, wirings, and terminals are formed of the first conductive layer 101 in addition to the gate wiring of the transistor. The first conductive layer 131 formed in the microstructure 21 functions as a sacrificial layer, and is processed into a disk shape as shown in FIG.

  Next, a semiconductor layer that forms the movable electrode 221, the fixed electrode 222, and the wiring 223 is formed in the first region, and a semiconductor that forms the semiconductor layer 203 of the transistor is formed in the second region. First, as shown in FIG. 7B, a semiconductor film 233A constituting the first semiconductor layer is formed. Since the semiconductor film 233A forms a channel formation region of the transistor, the semiconductor film 233A is formed without intentionally adding an impurity imparting conductivity so as to be an intrinsic semiconductor (i-type semiconductor). The semiconductor film 233A may be an amorphous semiconductor, or a crystalline semiconductor such as a microcrystalline semiconductor or a polycrystalline semiconductor. As the method for forming the semiconductor film 233A, the method described in Embodiment 1 can be used.

  Next, as shown in FIG. 7C, a semiconductor film 233B forming the second semiconductor layer is formed. The semiconductor film 233B is a semiconductor layer containing an impurity imparting n-type or p-type conductivity and forms a source region and a drain region of the transistor, and also functions as a conductive layer. The semiconductor film 233B may be either an amorphous semiconductor or a crystalline semiconductor such as a microcrystalline semiconductor or a polycrystalline semiconductor. As the method for forming the semiconductor films 233B and 233B, the method described in Embodiment 1 can be used.

  In this embodiment mode, a semiconductor layer having a two-layer structure including the semiconductor film 233A and the semiconductor film 233B is used as the structural layer; therefore, the structural layer can be formed using two semiconductor layers having different crystal structures. Since properties such as strength differ depending on the crystal structure, defects of the crystal structure of each other layer can be compensated by forming the structural layer with a multilayer film of semiconductors having different crystal structures.

  For example, the semiconductor film 233A can be an amorphous semiconductor and the semiconductor film 233B can be a polycrystalline semiconductor. Further, the semiconductor film 233A can be a microcrystalline semiconductor and the semiconductor film 233B can be a polycrystalline semiconductor.

  Needless to say, the semiconductor films 233A and 233B may have the same crystal structure. By forming the semiconductor layer as a multilayer, it is easy to form a thick structural layer. For example, by repeating formation of an amorphous semiconductor film and crystallization by heat treatment with heat energy or light energy, a stacked film in which crystalline semiconductor films are stacked can be formed. In this manner, a stacked film of crystalline semiconductors can be formed, and internal stress in the lower layer can be relieved by heat treatment in the upper crystallization step, so that peeling of the film and deformation of the substrate can be prevented.

  In the case where a crystalline semiconductor is used for the semiconductor films 233A and 233B, the semiconductor films 233A and 233B can be stacked so that crystal growth directions are different. For example, when a semiconductor film is crystallized using a metal element, the crystal growth of the semiconductor proceeds in a direction perpendicular to the substrate when the metal element is added to the entire region to be crystallized. On the other hand, when a metal element is selectively added and laser irradiation or heat treatment is performed, crystal growth proceeds in a direction parallel to the substrate.

  By stacking layers having different crystal growth directions, a structural layer having excellent toughness can be formed. Since films having different crystal growth directions are stacked, defects of each other can be compensated. That is, even if a crack occurs in a crystal grain boundary of one layer, the crack is difficult to propagate to a layer having a different crystal growth direction, so that the destruction of the structural layer can be suppressed.

  Further, the semiconductor films 233A and 233B can be crystallized by selecting a region to be crystallized. That is, only the region (second region) for forming the electric circuit 20 or the region (first region) for forming the microstructure 21 can be selected and crystallized. For example, the semiconductor film 233A is formed using an amorphous semiconductor, and only a region to be the microstructure 21 is crystallized. The semiconductor film 233B is a microcrystalline semiconductor and is not partially crystallized. In this case, even if the first semiconductor layer of the microstructure 21 and the first semiconductor layer of the transistor are in the same layer, the crystal structure is different, and the second semiconductor layer has the same crystal structure in the microstructure 21 and the transistor. Become.

  Note that selective crystallization is realized by selectively irradiating a semiconductor with a laser beam. In the case of crystallization using a metal element, a region to which the metal element is added is made partial.

  After the semiconductor films 233A and 233B are formed, the semiconductor films 233A and 233B and the first insulating layer 132 are processed into a predetermined shape by a photolithography process and an etching process as shown in FIG.

  First semiconductor layers 234A, 228A, and 229A are formed from the semiconductor film 233A. Semiconductor layers 234B, 228B, and 229B are formed from the semiconductor film 233B. The first insulating layer 132 is removed by an etching process except for portions overlapping with the semiconductor layers 234A, 234B, 228A, 228B, 229A, and 229B, and the first insulating layer 102 is formed in the second region. The first insulating layers 226 and 227 are formed in this region.

  By this step, the shapes of the movable electrode 221, the fixed electrode 222, and the wiring 223 of the microstructure 21 are determined. FIG. 9 is a top view of the microstructure 21 in FIG. A cross section taken along the chain line OP in FIG. 9 is shown in FIG.

  A stacked body including the first insulating layer 226, the first semiconductor layer 228A, and the second semiconductor layer 228B is a structural layer (first structural layer) constituting the movable electrode 221, and an opening for providing the rotation shaft 225 at the center. 230 is formed. A stacked body including the first insulating layer 227, the first semiconductor layer 229A, and the second semiconductor layer 229B is a structural layer (second structural layer) that forms the fixed electrode 222 and the wiring 223.

  In the second region, the first insulating layer 102 serving as a gate insulating film and the semiconductor layer 234 forming the semiconductor layer 203 are formed. The semiconductor layer 234 is a stacked film of a first semiconductor layer 234A and a second semiconductor layer 234B.

  Next, a conductive film is formed by a sputtering method or the like, and the shape of the conductive film is processed by a photolithography process and an etching process, so that a second conductive layer 104 is formed in the second region as illustrated in FIG. Then, the second conductive layer 237 is formed on the microstructure 21. In the second region, in addition to the electrodes (wirings) of the transistors, electrodes, wirings, terminals, and the like constituting the electric circuit 20 are formed by the second conductive layer 104. In addition, the conductive film included in the second conductive layers 104 and 237 can be manufactured in a manner similar to that in Embodiment Mode 1.

  The second conductive layer 237 is formed to protect the structural layer from being removed by etching when the opening 107 is formed in the second insulating layer 105 described later. Further, since the second conductive layer 237 is finally removed, it is also a sacrificial layer (second sacrificial layer). The second conductive layer 237 covers at least the surface of the structural layer (the first semiconductor layers 228A, 229A, the second semiconductor layers 228B, 229B, and the insulating layers 226, 227) in the region where the opening 107 is formed. It is said. Of course, there may be a portion covering the structural layer (the first semiconductor layer 229A, the second semiconductor layer 229B, and the insulating layer 227) in the portion where the second insulating layer 105 is left. In this case, part of the wiring 223 of the microstructure 21 partially has a stacked structure of the insulating layer 227, the first semiconductor layer 229A, the second semiconductor layer 229B, and the second conductive layer 237.

  In the second region, part of the semiconductor layer 234 is removed by etching using the second conductive layer 104 as a mask, so that the semiconductor layer 203 is formed. By this etching, the second semiconductor layer 234B is divided, and a pair of second semiconductor layers 203B is formed. The pair of second semiconductor layers 203B functions as a source region and a drain region. A part of the surface layer of the first semiconductor layer 234A is removed, and a first semiconductor layer 203A in which a channel formation region is formed is formed.

  On the other hand, in the first region, the second semiconductor layer 237 is formed of a metal that can form a metal compound by reacting with silicon or germanium. The metal compound (typically, a silicide which is a compound of metal and silicon) can be formed by reacting 228A and 229A and the second semiconductor layers 228B and 229B with the second conductive layer 237. In this case, the metal compound is formed by heat treatment or the like after the semiconductor layer 234 is etched.

  In this case, the entire second semiconductor layers 228B and 229B can be made of a metal compound. Further, the surface layer can be partially made of a metal compound. The second semiconductor layers 228B and 229B are conductive layers exhibiting n-type or p-type conductivity, and by being formed into a metal compound, the electrical conductivity can be improved and the strength can also be improved.

  The first semiconductor layers 228A and 229A can be entirely made of a metal compound depending on the thickness of the second semiconductor layers 228B and 229B. At least a certain thickness of the side surface in contact with the second conductive layer 237 can be formed into a metal compound. That is, the side surfaces of the movable electrode 221 and the fixed electrode 222 and the inside of the opening 230 where the rotation shaft 225 is provided later can be made of a metal compound. It is very effective to use such a portion that is susceptible to impact as a metal compound by improving the strength of the microstructure.

  In addition, since the first semiconductor layers 229A and 229B are not particularly provided with conductivity for the purpose of forming a channel formation region of the transistor, by forming a metal compound, the movable electrode 221, the fixed electrode 222, and the wiring 223 are formed. Resistance can be lowered. In particular, since the metal compound is formed on the surface where the fixed electrode 222 and the movable electrode 221 face each other, the area of the portion where the electrostatic force can be generated can be increased.

  Note that the electric conductivity of the first semiconductor layers 228A and 229A can be increased to be a conductive layer. For example, before the second semiconductor film 233B is formed (see FIG. 7B), n-type or p-type conductivity is selectively imparted to a portion in the first region of the first semiconductor film 233A. An impurity may be added to form an n-type or p-type impurity region. Further, by selectively using such a region as a metal compound (silicide or a compound of germanium and metal), a conductive layer can be obtained. In addition, both the addition of impurities and the formation of a metal compound can be performed.

  Next, as shown in FIG. 8A, a second insulating layer 105 is formed. After a contact hole is formed in the second insulating layer 105, a conductive film is formed over the second conductive layer 104, and the conductive film is processed into a predetermined shape by a photolithography process and an etching process. Three conductive layers 106 are formed. After the third conductive layer 106 is formed, as shown in FIG. 8B, an opening 107 is formed in a region where the microstructure 21 of the second insulating layer 105 is formed by etching, and the second conductive layer 237 is formed. To expose.

  Next, as shown in FIG. 8B, an opening 238 that penetrates the second conductive layer 237 and the first conductive layer 131 is formed in a portion where the rotation shaft 225 is formed. The opening 238 can be formed by dry etching, and the second conductive layer 237 and the first conductive layer 131 are anisotropically etched.

  The opening 238 is formed inside the opening 230 of the movable electrode 221. In order to separate the rotating shaft 225 and the movable electrode 221, the opening 238 is formed smaller than the opening 230 provided in the movable electrode 221 shown in FIG. 7D, and the second conductive layer is formed in the opening 230. 237 remains.

  A film made of polycrystalline semiconductor, metal, metal compound, alloy, or the like is formed over the second conductive layer 237, processed into a predetermined shape by a photolithography process and an etching process, and rotated as shown in FIG. 8C. A shaft 225 is formed. As the material of the rotating shaft 225, a material that cannot be removed by an etching agent used for sacrificial layer etching for removing the first conductive layer 131 and the second conductive layer 237 is used.

  The rotating shaft 225 is processed so that the tip (portion on the second conductive layer 237) is wider than the opening 230, and the bottom of the rotating shaft is formed in close contact with the substrate 100.

  Next, so-called sacrificial layer etching is performed in which the second conductive layer 237 (second sacrificial layer) and the first conductive layer 131 (first sacrificial layer) are removed by etching. When the sacrificial layer etching is completed, the microstructure 21 shown in FIG. 6 is completed.

  As described above, according to the present invention, a microstructure including a rotor and an electric circuit can be formed over a substrate having an insulating surface. Therefore, the mechanical strength of the connection portion between the electric circuit and the microstructure is high, and connection failure hardly occurs. Further, there is no process for integrating the microstructure and the electric circuit later, and the manufacturing cost can be reduced.

(Embodiment 3)
In this embodiment, an example in which the microstructure is deformed in the MEMS of Embodiment 1 will be described. In this embodiment, the microstructure has a comb-teeth shape, has an elongated movable layer (slider), and fixed layers on both sides thereof, and moves in the horizontal direction of the substrate. Such microstructures change one mechanical movement into another movement, for example, turn rotational movement into linear movement. Specifically, as shown in FIG. 14, the comb teeth of the movable layer 422 (slider) and the teeth of the gear 421 mesh with each other, and the rotating gear 421 moves the movable layer 422. The movable layer 422 moves linearly in the major axis direction. In addition, the fixed layer 425 is at both ends of the movable layer 422 and restricts the movement of the movable layer in directions other than the major axis direction.
10A and 10B are views showing the structure of the MEMS of this embodiment, FIG. 10A is a cross-sectional view of the MEMS, and FIG. 10B is a top view of the microstructure. Note that in FIG. 10A, the left side is a cross-sectional view of a first region where a microstructure is formed, and the right side is a cross-sectional view of a second region where an electric circuit is formed. This also applies to the cross-sectional views shown in FIGS. Also. A cross-sectional view taken along a chain line OP in FIG. 10B corresponds to a cross-sectional view of the microstructure 31 in FIG. Note that since the microstructure 31 is elongated in the major axis direction, the top and bottom are omitted, and only a part is shown.

  In this embodiment also, the electric circuit 10 and the microstructure 31 are formed on the same substrate 100 (on the same insulating surface). As shown in FIG. 10B, the microstructure 31 includes a comb-shaped movable layer 321 (first structure layer), a pair of rectangular first fixed layers 322 (second structure layer), A wiring 323 connected to the first fixed layer 322 and a second fixed layer 325 are included. The wiring 323 is formed integrally with the first fixed layer 322 and is electrically connected to the electric circuit 10. Further, the second fixed layer 325 may be provided so that the movable layer 321 (first structure layer) does not move in the direction perpendicular to the substrate.

  The movable layer 321 is a comb-shaped electrode and is formed separately from the substrate 100. The pair of first fixed layers 322 are rectangular electrodes, and are arranged so as to sandwich the movable layer 321 therebetween. The first fixed layer 322 is formed to be fixed to the substrate 100, but the tip facing the movable layer 321 is separated from the substrate 100. The second fixed layer 325 is formed in close contact with the first fixed layer 322. The tip of the second fixed layer 325 is separated from the first fixed layer 322 and overlaps the movable layer 321.

  In the microstructure 31, the pair of first fixed layers 322 is a layer that restricts the movement of the movable layer 321 because it does not move in a direction different from the direction in which the movable layer 321 moves (here, the long axis direction of the movable layer).

  In this embodiment, since the structure of the electric circuit 10 is the same as that of the first embodiment, the stacked structure of the movable layer 321, the first fixed layer 322, and the wiring 323 is the first structure layer (movable electrode 121) of the first embodiment. And the second structural layer (fixed electrode 122, wiring 123).

  Hereinafter, a method for manufacturing the MEMS of the present embodiment will be described with reference to FIGS. In addition, the description which overlaps with Embodiment 1 is abbreviate | omitted, and description of Embodiment 1 is used.

  As in Embodiment Mode 1, a substrate having an insulating surface is prepared as the substrate 100. A conductive film is formed over the substrate 100, processed into a predetermined shape by a photolithography process and an etching process, and a first conductive layer 101 is formed in the second region as shown in FIG. The first conductive layer 331 is formed in the region. A first insulating layer 132 is formed on the first conductive layers 101 and 331. The first conductive layer 331 functions as a sacrificial layer (first sacrificial layer) and is processed into a rectangular shape as shown in FIG. 13 is a top view of the microstructure 31 shown in FIG. 11C, and a cross section taken along the chain line OP in FIG. 13 is shown in FIG.

  Next, as shown in FIG. 11B, a layer that forms the movable layer 321 and the first fixed layer 322 is formed in the first region, and a semiconductor that forms the semiconductor layer 103 of the transistor in the second region. Layer 333 is formed.

  Next, as illustrated in FIG. 11C, the semiconductor layer 333 and the first insulating layer 132 are processed into a predetermined shape by a photolithography process and an etching process. A semiconductor layer 103 of the transistor is formed in the second region from the semiconductor layer 333. In the first region, a semiconductor layer 334 that is part of the first structure layer and a semiconductor layer 335 that is part of the second structure layer are formed. The first insulating layer 132 is processed into the same shape as the semiconductor layers 103, 334, and 335, the first insulating layer 102 serving as a gate insulating film of the transistor is formed in the second region, and the first region is formed in the first region. Insulating layers 326 and 327 are formed.

  By this step, the shapes of the first and second structural layers of the microstructure 31 are determined. A stacked body of the insulating layer 326 and the semiconductor layer 334 forms the movable layer 321 (first structure layer), and a stacked body of the insulating layer 327 and the semiconductor layer 335 forms the first fixed layer 322 and the wiring 323 (second structural layer). Constitute. As shown in FIG. 13, the semiconductor layer 334 is formed in a rectangular shape having comb-like portions, and the pair of semiconductor layers 335 includes a rectangular portion serving as the first fixed layer 322 and a linear shape serving as the wiring 323. The portions are integrally formed, and are arranged so as to sandwich the semiconductor layer 334.

  Note that since the movable layer 321 is finally separated from the substrate 100, the entire stacked body including the insulating layer 326 and the semiconductor layer 334 is disposed on the upper surface of the first conductive layer 331. In addition, in order to form a portion separated from the substrate 100 at the tip of the first fixed layer 322 and fix the first fixed layer 322 to the substrate 100, the tip of the laminate including the insulating layer 327 and the semiconductor layer 335 is The first conductive layer 331 is formed so as to cover the upper surface and the side surface, and the other part is formed in contact with the surface (insulating surface) of the substrate 100.

  An n-type or p-type impurity imparting conductivity is selectively added to the semiconductor layers 103, 334, and 335 by a doping method or an ion implantation method. In order to selectively add an impurity to a portion other than the first conductive layer 101 to be a gate electrode, a resist mask is formed on a portion to which no impurity is added by using a photolithography method, and this mask is used. Impurities are added. Through this step, as shown in FIG. 11D, a high concentration impurity region 103b is formed in the semiconductor layer 103, and a region of the semiconductor layer 103 to which no impurity is added is determined as a channel formation region 103a. The high concentration impurity region 103b functions as a source region or a drain region. In the case where a resist mask is not formed over the structural layer, the semiconductor layers 334 and 335 included in the structural layer are given conductivity by addition of impurities, so that conductive layers 328 and 329 are formed. In the case of this embodiment mode, the structural layer does not need to have conductivity; therefore, a resist mask can be formed over the structural layer so that impurities are not added to the structural layer.

  Next, a conductive film is formed by a sputtering method or the like, and the shape of the conductive film is processed by a photolithography process and an etching process, so that a second conductive layer 104 is formed in the second region as illustrated in FIG. Then, a second conductive layer 337 (second sacrificial layer) is formed in the first region. The second conductive layer 104 functions as a source electrode or a drain electrode.

  The second conductive layer 337 is formed to protect the first and second structural layers from being removed by etching when the opening 107 is formed in the second insulating layer 105. Therefore, the second conductive layer 337 does not need to cover all the structural layers (328 and 329), and may have a shape that covers at least a portion existing in a region where the opening 107 is formed. The second conductive layer 337 also functions as a sacrificial layer for creating a gap between the first fixed layer 322 and the second fixed layer 325.

  In addition, when the structure layer needs to have conductivity, the second conductive layer 337 is formed using a material containing a metal element that can form a metal compound by reacting with silicon or germanium as described in Embodiment 1. The conductive layers 328 and 329 can be made of a metal compound (typically silicide).

  Next, as shown in FIG. 12A, a second insulating layer 105 is formed. After a contact hole is formed in the second insulating layer 105, a conductive film is formed over the second conductive layer 104, and the conductive film is processed into a predetermined shape by a photolithography process and an etching process, so that a second region is formed. A third conductive layer 106 is formed. After the third conductive layer 106 is formed, an opening 107 is formed in the second insulating layer 105 by etching in the first region, as shown in FIG. Then, so-called sacrificial layer etching is performed in which the second conductive layer 337 (second sacrificial layer) and the first conductive layer 331 (first sacrificial layer) are removed by etching. Similar to the movable electrode of the microstructure in Embodiment Mode 1, the movable layer 321 is not fixed to the substrate 100 when the sacrificial layers (337, 331) are removed. Therefore, as in Embodiment Mode 1, the opening 107 can be formed so that the second insulating layer 105 remains above the movable layer 321. It is also possible to form a second fixed layer on the movable layer 321. Here, an example of forming the second fixed layer is shown.

  Next, in order to connect the first fixed layer 322 and the second fixed layer 325, the second conductive layer 337 is partially removed by a photolithography process and an etching process (see FIG. 12B).

  A conductive layer is formed over the second conductive layer 237 and processed into a predetermined shape by a photolithography process and an etching process to form a second fixed layer 325 (third structure layer) as shown in FIG. . A part of the second fixed layer 325 is formed in close contact with the first fixed layer 322 and connected to the first fixed layer 322. The tip of the second fixed layer 325 is formed so as to cover the upper surface and the side surface of the second conductive layer 337. As a result, the tip of the second fixed layer 325 is separated from the first fixed layer 322 and provided to overlap the movable layer 321.

  The material of the second fixed layer 325 is a metal such as molybdenum (Mo), tungsten (W), chromium (Cr), tantalum (Ta), titanium (Ti), or aluminum (Al), and these metal elements as main components. A metal compound (for example, titanium nitride, tungsten nitride), an alloy mainly containing these metal elements (for example, an alloy of aluminum and titanium, an alloy of chromium and molybdenum), or the like can be selected. Alternatively, a refractory metal such as tungsten, titanium, molybdenum, or tantalum, a silicide such as cobalt or nickel, or crystalline silicon having n-type or p-type conductivity may be used. The second fixed layer 325 is formed of a single layer film or a multilayer film of a conductive film selected from these conductive materials. In the case where the second fixed layer 325 does not require conductivity, the second fixed layer 325 is formed using a single layer film or a multilayer film using an insulating material. Note that as the material of the second fixed layer 325, a material that is not removed by the etching agent used in the sacrifice layer etching for removing the first conductive layer 331 and the second conductive layer 337 is used.

  So-called sacrificial layer etching is performed in which the second conductive layer 337 (second sacrificial layer) and the first conductive layer 331 (first sacrificial layer) are removed by etching. When the sacrificial layer etching is completed, the microstructure 31 shown in FIG. 10 is completed.

  As described above, according to the present invention, a microstructure including a rotor and an electric circuit can be formed over a substrate having an insulating surface. Therefore, the mechanical strength of the connection portion between the electric circuit and the microstructure is high, and connection failure hardly occurs. In addition, since there is no step of integrating the microstructure and the electric circuit later, the structure of the MEMS is simplified and the manufacturing cost can be reduced.

  In this embodiment mode, the movable layer 321 (first structure layer) is comb-shaped, but can be processed into a shape that functions as a rotor or a gear or a shape that functions as a slider. The shape of the first structure layer is not limited to the shape of the present embodiment as long as the shape is processed so as to be movable.

  In the present embodiment, the configuration of the electric circuit is the electric circuit 10 of the first embodiment, but the electric circuit 20 of the second embodiment may be used. In this case, the laminated structure of the movable layer 321 and the first fixed layer 322 (first and second structure layers) is the same as the first and second structure layers (movable electrode 221 and fixed electrode 222) of the second embodiment. Become.

(Embodiment 4)
In this embodiment, an example of a structure of a microstructure is described. FIG. 14 is an external perspective view of the microstructure of the present embodiment. Although FIG. 14 illustrates only a microstructure, an electric circuit and the microstructure are integrated over a substrate having an insulating surface.

  The microstructure includes a first movable layer 421 (first structure layer) having a gear shape, a second movable layer 422 (second structure layer) having teeth meshing with the first movable layer 421, and a second movable layer 422. A fixed layer 425 (third structure layer) for applying an electrostatic force or the like. The fixed layer 425 is electrically connected to an electric circuit (not shown).

  The first movable layer 421 is a gear, and is separated from the substrate (insulating surface) and other structural layers, like the first structural layer of the other embodiments. The second movable layer 422 is a slider and has teeth that mesh with the first movable layer 421. Similar to the first structural layer, the second movable layer 422 is also separated from the substrate and other structural layers. As described above, the linear motion of the first structural layer 421 can be changed to the rotational motion of the second structural layer 422 by meshing the first structural layer 421 and the second structural layer 422. Conversely, the rotational motion of the second structural layer 422 can be changed to the linear motion of the first structural layer 421.

  For example, the second structure layer 422 can be linearly moved using the fixed layer 425. When an electrostatic force acts on the second movable layer 422 by applying a voltage between the fixed layer 425 and the second structural layer 422, the second movable layer 422 moves horizontally like the electrostatic linear motor, and the first One movable layer 421 rotates. Note that the second movable layer 422 can be moved not by electrostatic force but by electromagnetic force. Such a microstructure can be used as a manipulator that handles small cells. Further, as shown in the first embodiment or the second embodiment, the first movable layer 421 is rotated so that the rotational motion of the first movable layer 421 is converted into the horizontal motion of the second movable layer 422. It can also be a structure.

  The microstructure shown in FIG. 14 shows an example in which the MEMS manufacturing method of Embodiment 3 is used. Simultaneously with the electric circuit 10, the first to third structural layers (421, 422, 425) of the microstructure are formed on the substrate 100. In the third embodiment, the shape of the first to third structure layers (movable layer 321, first fixed layer 322, second fixed layer 325) and the first and second sacrificial layers (first conductive layer 331, second layer) By changing the shape of the conductive layer 337), the microstructure of this embodiment can be manufactured. Therefore, the stacked structure of each structural layer of the microstructure is the same as that of the microstructure 31 and is a stack of an insulating layer and a semiconductor layer.

  Also, the structure of the electric circuit can be the electric circuit 20 of the second embodiment. In this case, the laminated structure of the first to third structure layers (421, 422, 425) is the same as that of the first to third structure layers (221, 222, 225) of the second embodiment.

(Embodiment 5)
In this embodiment, a technique for allowing the movable portion of the microstructure to move smoothly will be described.

  The microstructure 11 according to Embodiment 1 will be described as an example. In order to facilitate understanding of the structure of the microstructure, FIG. 1A shows the movable electrode 121 (first structural layer) and the substrate 100 apart from each other, but the movable electrode 121 is formed by sacrificial layer etching. After that, it does not float from the substrate 100 but comes into contact with the substrate 100 by gravity. Therefore, friction with the insulating surface of the substrate 100 becomes a problem when the movable electrode 121 rotates. In the MEMS microstructure of the present invention, the lowermost layer of the structural layer constituting the movable portion is formed of an insulating layer (126 or the like). By forming the insulating layer, which is in contact with the substrate surface, of silicon nitride, silicon oxynitride, or silicon nitride oxide, friction can be reduced as compared with a structural layer without an insulating layer.

  By providing a low friction layer on the surface of the substrate 100 so that friction with the movable electrode 121 is reduced, the effect of suppressing friction can be further improved. As the low friction layer, a material containing silicon such as silicon nitride, silicon nitride oxide, silicon oxynitride, or silicon carbide formed by a CVD method or a sputtering method, or diamond-like carbon (DLC) can also be used. . Since DLC is dense, its protective function is high.

  The low friction layer can also be selectively formed on the entire surface of the substrate 100 in a region where the microstructure 11 is formed. The low friction layer can be formed as an insulating surface of the substrate 100 if the insulating property is sufficient.

  The low friction layer may be provided not only on the surface of the substrate but also in a portion where the structural layers are close to each other by electrostatic force or van der Waals force. For example, a portion where the low friction layer is provided in the microstructure 21 according to the second embodiment corresponds to the inside of the opening 230, the contact portion between the rotating shaft 225 and the movable electrode 221 and the like in the movable electrode 221. Further, in the microstructure 11 of the first embodiment, a portion where the movable electrode 121 and the fixed electrode 122 are in contact also corresponds.

  In the layer constituting the microstructure, it is preferable to process the shape by a photolithography process and an etching process so that the corner has a rounded shape when the corner has a shape as viewed from above. The same applies to the sacrificial layer. Since the generation of dust is suppressed by processing the shape into a rounded shape by taking a corner, the yield can be improved. In addition, since the stress concentration at the corners is relaxed, cracks that cause breakage are less likely to occur.

  FIG. 15 is a top view corresponding to FIG. 1B and shows an example in which the shape is processed so that the corners of the structural layer of the microstructure 11 of Embodiment 1 are rounded. Of course, the microstructures of Embodiments 2 to 4 can be processed so that the corners of the structure layer are rounded.

(Embodiment 6)
The microelectromechanical device of the present invention having a microstructure belongs to the field of micromachines and has a size of micrometer to millimeter. Further, when manufactured to be incorporated as a part of a certain mechanical device, it may have a metric size so that it can be easily handled during assembly.

  A configuration example of a microelectromechanical device having the microstructure of the present invention will be described with reference to FIG. FIG. 16 is a block diagram illustrating a configuration example of a microelectromechanical device (semiconductor device) of the present invention. The microelectromechanical device of the present invention is not limited to the configuration example of FIG.

  A microelectromechanical device (MEMS) 501 of the present invention is a device in which an electric circuit portion 502 including a semiconductor element and a structure portion 503 including a microstructure are combined. The electric circuit portion 502 includes a control circuit 504 that controls the microstructure, an interface 506 that communicates with the external control device 500, and the like. The structure portion 503 includes a sensor 505, an actuator 507, a switch, and the like by a microstructure. An actuator is a component that converts a signal (mainly an electrical signal) into a physical quantity. The structure body 503 can be provided with an electrostatic motor as described in Embodiment Modes 1 and 2.

  Further, the electric circuit portion 502 can include a central processing unit for processing information obtained by the structure portion 503.

  The external control device 500 transmits a signal for controlling the microelectromechanical device 501, receives information obtained by the microelectromechanical device 501, supplies driving power to the microelectromechanical device 501, etc. Perform the action.

In the present invention, a semiconductor element constituting such an electric circuit and a microstructure can be integrally formed on the same insulating surface. By integrally forming, connection failure between an electric circuit or the like and a microstructure can be reduced, and thus yield can be improved.

  Conventionally, when handling a minute object such as a millimeter or less, the structure of a minute object is enlarged, a human or a computer obtains the information to determine information processing and operation, and then reduces the operation. It needed a process of communicating to minute objects. However, a semiconductor device having a microstructure according to the present invention can handle a minute device simply by a human or computer transmitting a high-level conceptual command. That is, when a human or a computer determines a purpose and transmits a command, a semiconductor device having a microstructure can obtain information on an object using a sensor or the like, perform information processing, and take an action.

  In the above first to fifth embodiments, it is assumed that the object is minute. For example, the object itself has a size of a meter unit, but includes a weak signal (for example, a minute change in light or pressure) emitted from the object.

  As described above, Embodiments 1 to 6 can be appropriately combined. For example, the shape of the movable electrode 121 shown in Embodiment Mode 1 can be processed like the movable electrode 221 shown in Embodiment Mode 2. Conversely, the shape of the movable electrode 221 can be processed like the movable electrode 121.

  In this example, as described in Embodiment Mode 2 and the like, an example in which a structural layer is formed using semiconductor layers having different crystal structures is shown.

  As described in the second embodiment, silicon layers having different crystal structures, such as a polycrystalline silicon layer and an amorphous silicon layer, have different mechanical characteristics. Therefore, by stacking, structures according to various uses can be manufactured.

<Measurement of composite elastic modulus and indentation hardness>
In order to investigate the difference in mechanical properties of silicon layers with different crystal structures, the composite elastic modulus and indene of an amorphous silicon layer formed by CVD and a crystalline silicon layer crystallized from amorphous silicon The measurement of the stationation hardness was performed. Here, the crystalline silicon layer is obtained by laser crystallization of an amorphous silicon layer using a metal element.

  The amorphous silicon layer used for the sample was formed as follows. First, a silicon nitride layer having a thickness of 50 nm and a silicon oxide layer having a thickness of 100 nm are formed as a base layer on a quartz substrate by a CVD method, and an amorphous silicon layer having a thickness of 66 nm is formed on the base layer by plasma. A film was formed by a CVD method.

The crystalline silicon layer used for the sample was prepared as follows. An amorphous silicon layer having a thickness of 66 nm was formed by plasma CVD. Nickel was added to the amorphous silicon layer and crystallized using a continuous wave laser. The thickness of the crystalline silicon layer crystallized by laser irradiation was about 60 nm. The laser beam used for crystallization is Nd: a YVO ₄ second harmonic of the laser, the energy density is adjusted with 9W / cm ² or more 9.5 W / cm ² or less in the range of the scanning speed was 35 cm / sec .

  The measurement was performed by nanoindentation measurement in which a triangular pyramid indenter was pushed into the sample. The measurement condition was a single indentation of the indenter, and the indenter used was a Berkovich indenter made of diamond. Therefore, the indenter has an elastic modulus of about 1000 GPa and a Poisson's ratio of about 0.1.

  The measured composite elastic modulus is represented by the following formula (1), and is an elastic modulus obtained by combining the elastic modulus of the sample and the indenter. In the formula (1), Er is a composite elastic modulus, E is a Young's modulus, and ν is a Poisson's ratio. In addition, the first term (term indicated by sample) in the equation is a term contributed by the elastic modulus of the sample, and the second term (term indicated by indenter) is a term contributed by the elastic modulus of the indenter.

  As shown in Equation (1), the composite elastic modulus is obtained by the sum of the first term contributed by the elastic modulus of the sample and the second term contributed by the elastic modulus of the indenter. However, since the elastic modulus of the indenter is much larger than that of the sample, the second term can be ignored, and the composite elastic modulus approximately represents the elastic modulus of the sample.

  The indentation hardness is hardness measured by an indentation method, and is obtained by dividing the maximum press-fitting weight of the indenter by the projected area at the maximum press-fitting. Here, the projected area at the time of press-fitting is determined by the geometric shape of the indenter and the contact depth when the indenter pushes the sample. By multiplying this indentation hardness by 76, it can be handled equivalent to the Vickers hardness generally used as an index of hardness.

  Table 1 shows the measurement results of the composite elastic modulus and indentation hardness of the crystalline silicon layer and the amorphous silicon layer. The numerical value of Table 1 has shown the average value of 3 times of measurement results.

  From the results shown in Table 1, crystalline silicon has a higher elastic modulus than amorphous silicon. That is, when a force that bends the structure is applied, crystalline silicon is more resistant to bending damage than amorphous silicon. It has also been shown that crystalline silicon is harder than amorphous silicon.

  By laminating semiconductor layers having different elastic moduli and hardness in this way, a structural layer having both flexibility and strength against bending force can be manufactured. For example, by laminating the amorphous silicon layer and the crystalline silicon layer used as samples in this embodiment, even if the crystalline silicon layer is broken due to crystal defects, the destruction propagates to the amorphous silicon layer. Because it is difficult to do so, you can stop the destruction there. Thus, the balance between the flexibility and hardness of the structural layer can be determined by the ratio of the thicknesses of the layers to be stacked.

FIGS. 7A and 7B are diagrams illustrating a configuration example of a microelectromechanical device of the present invention, FIG. 9A is a cross-sectional view of the microelectromechanical device, and FIG. ). FIG. 10 is a cross-sectional view for illustrating a method for manufacturing a microelectromechanical device of the present invention (Embodiment 8). FIG. 9 is a cross-sectional view for illustrating a method for manufacturing a microelectromechanical device of the present invention (Embodiment 9). FIG. 10 is a top view of a microstructure in the middle of manufacture and a top view of a first conductive layer (first sacrificial layer) (Embodiment 10). It is a top view of the microstructure in the middle of manufacture, and is a top view of the microstructure illustrated in FIG. 2C (Embodiment 11). FIGS. 7A and 7B are diagrams illustrating a configuration example of a micro electro mechanical device of the present invention, FIG. 9A is a cross-sectional view of the micro electro mechanical device, and FIG. ). FIG. 19 is a cross-sectional view for illustrating a method for manufacturing a microelectromechanical device of the present invention (Embodiment 13). FIG. 19 is a cross-sectional view for illustrating a method for manufacturing a microelectromechanical device of the present invention (Embodiment 14). It is a top view of the microstructure in the middle of manufacture, and is a top view of the first conductive layer (first sacrificial layer) (Embodiment 15). FIGS. 7A and 7B are diagrams illustrating a configuration example of a micro electro mechanical device of the present invention, FIG. 6A is a cross-sectional view of the micro electro mechanical device, and FIG. ). FIG. 18 is a cross-sectional view for illustrating a method for manufacturing a microelectromechanical device of the present invention (Embodiment 17). FIG. 19 is a cross-sectional view for describing a method for manufacturing a microelectromechanical device of the present invention (Embodiment 18). FIG. 48 is a top view of a microstructure in the middle of manufacture and a top view of a first conductive layer (first sacrificial layer) (Embodiment 19). FIG. 20 is an external perspective view of a microstructure according to the present invention (Embodiment 20). FIG. 22 is a top view of a microstructure of the present invention whose shape is processed so that corners are rounded (Embodiment 21). It is a block diagram which shows the structural example of the microelectromechanical apparatus of this invention (Embodiment 22).

Explanation of symbols

10, 20 electrical circuit 11, 21, 31 microstructure 100 substrate, 101 first conductive layer, 102 first insulating layer, 103 semiconductor layer, 104 second conductive layer, 105 second insulating layer, 106 third conductive layer, 107 opening 121 movable electrode (first structure layer), 122 fixed electrode (second structure layer), 123 wiring (second structure layer), 131 first conductive layer (first sacrificial layer), 137 second conductive layer ( Second sacrificial layer)
203 semiconductor layer, 221 movable electrode (first structure layer), 222 fixed electrode (second structure layer), 223 wiring (second structure layer), 225 rotation axis (third structure layer), 237 second conductive layer (first structure layer) 2 sacrificial layers)
321 movable layer (first structure layer), 322 first fixed layer (second structure layer), 323 wiring (second structure layer), 325 second fixed layer (third structure layer), 331 first conductive layer (first structure layer) 1 sacrificial layer), 337 second conductive layer (second sacrificial layer)
421 First movable layer (first structure layer), 422 Second movable layer (second structure layer), 425 fixed layer (third structure layer)

Claims (19)

A first structural layer formed on a substrate having an insulating surface and movable with respect to the substrate, and a second structural layer partially fixed to the substrate, and formed on the substrate A microstructure,
An electrical circuit having a transistor, electrically connected to the microstructure, and formed on the substrate;
Have
The transistor includes a gate insulating layer and a first semiconductor layer provided with a channel formation region,
The first structure layer and the second structure layer have an insulating layer and a second semiconductor layer in contact with the insulating layer,
The insulating layer of the first structural layer, the insulating layer of the second structural layer, and the gate insulating layer are each an insulating layer formed by patterning the same insulating film on the substrate,
The first semiconductor layer, the second semiconductor layer of the first structure layer, and the second semiconductor layer of the second structure layer are each formed by patterning the same semiconductor film on the substrate. A microelectromechanical device characterized in that it is a layer. In claim 1,
The semiconductor layer of the first structure layer and the second structure layer is a crystalline semiconductor layer. In claim 1,
The micro electromechanical device, wherein the second semiconductor layer of the first structure layer and the second structure layer is a crystalline semiconductor layer crystallized using a metal element. A first structural layer formed on a substrate having an insulating surface and movable with respect to the substrate, and a second structural layer partially fixed to the substrate, and formed on the substrate A microstructure,
An electrical circuit having a transistor, electrically connected to the microstructure, and formed on the substrate;
Have
The transistor includes a gate insulating layer and a first semiconductor layer provided with a channel formation region,
The first structure layer and the second structure layer have an insulating layer and a conductive layer in contact with the insulating layer,
The insulating layer of the first structural layer, the insulating layer of the second structural layer, and the gate insulating layer are each an insulating layer formed by patterning the same insulating film on the substrate,
The first semiconductor layer, the conductive layer of the first structural layer, and the conductive layer of the second structural layer are each a semiconductor layer formed by patterning the same semiconductor film on the substrate,
The electromechanical device according to claim 1, wherein the conductive layers of the first structure layer and the second structure layer include a compound of a semiconductor and a metal element. A first structural layer formed on a substrate having an insulating surface and movable with respect to the substrate, and a second structural layer partially fixed to the substrate, and formed on the substrate A microstructure,
An electrical circuit having a transistor, electrically connected to the microstructure, and formed on the substrate;
Have
The transistor includes a gate insulating layer, a first semiconductor layer provided with a channel formation region, and a second semiconductor layer provided with a high concentration impurity region,
The first structure layer and the second structure layer have an insulating layer, a third semiconductor layer in contact with the insulating layer, and a fourth semiconductor layer in contact with the third semiconductor layer,
The insulating layer of the first structural layer, the insulating layer of the second structural layer, and the gate insulating layer are each an insulating layer formed by patterning the same insulating film on the substrate,
Each of the first semiconductor layer and the third semiconductor layer is a semiconductor layer formed by patterning the same semiconductor film on the substrate;
The micro electromechanical device, wherein each of the second semiconductor layer and the fourth semiconductor layer is a semiconductor layer formed by patterning the same semiconductor film on the substrate. A first structural layer formed on a substrate having an insulating surface and movable with respect to the substrate, and a second structural layer partially fixed to the substrate, and formed on the substrate A microstructure,
An electrical circuit having a transistor, electrically connected to the microstructure, and formed on the insulating surface;
Have
The transistor includes a gate insulating film, a first semiconductor layer provided with a channel formation region, and a second semiconductor layer provided with a high concentration impurity region,
The first structure layer and the second structure layer have an insulating layer, a third semiconductor layer in contact with the insulating layer, and a fourth semiconductor layer in contact with the third semiconductor layer,
The insulating layer of the first structural layer, the insulating layer of the second structural layer, and the gate insulating layer are each an insulating layer formed by patterning the same insulating film on the substrate,
Each of the first semiconductor layer and the third semiconductor layer is a semiconductor layer formed by patterning the same semiconductor film on the substrate, and the first semiconductor layer and the third semiconductor layer are crystalline. The structure is different
The micro electromechanical device, wherein each of the second semiconductor layer and the fourth semiconductor layer is a semiconductor layer formed by patterning the same semiconductor film on the substrate. A first structural layer formed on a substrate having an insulating surface and movable with respect to the substrate, and a second structural layer partially fixed to the substrate, and formed on the substrate A microstructure,
An electrical circuit having a transistor, electrically connected to the microstructure, and formed on the substrate;
Have
The transistor includes a gate insulating layer, a first semiconductor layer provided with a channel formation region, and a second semiconductor layer provided with a high concentration impurity region,
The first structure layer and the second structure layer have an insulating layer, a third semiconductor layer in contact with the insulating layer, and a fourth semiconductor layer in contact with the third semiconductor layer and exhibiting conductivity,
The insulating layer of the first structural layer, the insulating layer of the second structural layer, and the gate insulating layer are each an insulating layer formed by patterning the same insulating film on the substrate,
Each of the first semiconductor layer and the third semiconductor layer is a semiconductor layer formed by patterning the same semiconductor film on the substrate;
The second semiconductor layer and the fourth semiconductor layer are semiconductor layers formed by patterning the same semiconductor film on the substrate, respectively, and the second semiconductor layer and the fourth semiconductor layer are A microelectromechanical device characterized by different crystal structures. In any one of Claims 5 thru | or 7,
The microelectromechanical device, wherein the third semiconductor layer and the fourth semiconductor layer have different crystal structures. In any one of Claims 5 thru | or 7,
The microelectromechanical device, wherein the third semiconductor layer is an amorphous semiconductor layer or a microcrystalline semiconductor layer, and the fourth semiconductor layer is a polycrystalline semiconductor layer. In any one of Claims 5 thru | or 7,
The microelectromechanical device, wherein the third semiconductor layer is an amorphous semiconductor layer or a microcrystalline semiconductor layer, and the fourth semiconductor layer is a crystalline semiconductor layer crystallized using a metal. In any one of Claims 5 thru | or 7,
The third semiconductor layer and the fourth semiconductor layer are crystalline semiconductor layers;
The microelectromechanical device, wherein the third semiconductor layer and the fourth semiconductor layer have different crystal growth directions. In any one of Claims 5 thru | or 7,
The third semiconductor layer and the fourth semiconductor layer are crystalline semiconductor layers crystallized using a metal element;
The microelectromechanical device, wherein the third semiconductor layer and the fourth semiconductor layer have different crystal growth directions. A first structural layer formed on a substrate having an insulating surface and movable with respect to the substrate, and a second structural layer partially fixed to the substrate, and formed on the substrate A microstructure,
An electrical circuit having a transistor, electrically connected to the microstructure, and formed on the substrate;
Have
The transistor includes a gate insulating layer, a first semiconductor layer provided with a channel formation region, and a second semiconductor layer provided with a high concentration impurity region,
The structural layer includes an insulating layer, a third semiconductor layer in contact with the insulating layer, and a conductive layer in contact with the third semiconductor layer,
The insulating layer of the first structural layer, the insulating layer of the second structural layer, and the gate insulating layer are each an insulating layer formed by patterning the same insulating film on the substrate,
Each of the first semiconductor layer and the third semiconductor layer is a semiconductor layer formed by patterning the same semiconductor film on the substrate;
The conductive layer of the first structural layer, the conductive layer of the second structural layer, and the second semiconductor layer are each a semiconductor layer formed by patterning the same semiconductor film on the substrate, A microelectromechanical device comprising a compound of a semiconductor and a metal element. In claim 13,
The micro electromechanical device, wherein the third semiconductor layer contains a compound of a semiconductor and a metal element. A first structural layer formed on a substrate having an insulating surface and movable with respect to the substrate, and a second structural layer partially fixed to the substrate, and formed on the substrate A microstructure,
An electrical circuit having a transistor, electrically connected to the microstructure, and formed on the substrate;
Have
The transistor includes a gate insulating layer, a first semiconductor layer provided with a channel formation region, and a second semiconductor layer provided with a high concentration impurity region,
The first structure layer and the second structure layer have an insulating layer, a third semiconductor layer in contact with the insulating layer, and a conductive layer in contact with the third semiconductor layer,
The insulating layer of the first structural layer, the insulating layer of the second structural layer, and the gate insulating layer are each an insulating layer formed by patterning the same insulating film on the substrate,
Each of the first semiconductor layer and the third semiconductor layer is a semiconductor layer formed by patterning the same semiconductor film on the substrate;
The second semiconductor layer, the conductive layer of the first structural layer, and the conductive layer of the second structural layer are each a semiconductor layer formed by patterning the same semiconductor film on the substrate. The third semiconductor layer includes a compound of a semiconductor and a metal element. A method of manufacturing a microelectromechanical device including a microstructure formed on a substrate having an insulating surface and an electric circuit formed on the substrate and electrically connected to the microstructure.
The microstructure has a first structure layer formed in a first region of the substrate and movable with respect to the substrate, and a second structure layer partially fixed to the substrate. Have
The electrical circuit includes a transistor;
Forming a conductive layer on the substrate;
By processing the conductive layer into a predetermined shape, a first sacrificial layer is formed in the first region, and a first conductive layer to be a gate electrode of the transistor is formed in the second region,
Forming an insulating film and a semiconductor film on the substrate and the first conductive layer;
By processing the insulating film and the semiconductor film into a predetermined shape, the first structure layer and the second structure layer in which the insulating layer and the semiconductor layer are stacked in the first region are formed, Forming a gate insulating layer of the transistor from the semiconductor film in the second region, and forming a semiconductor layer in which a channel formation region is formed from the semiconductor film;
Selectively adding an impurity imparting n-type or p-type conductivity to the semiconductor layer of at least the second region;
Forming another conductive layer on the substrate, the first insulating layer, and the semiconductor layer;
By processing the other conductive layer into a predetermined shape, a second sacrificial layer is formed in the first region, and the microstructure and the electric circuit are electrically connected to the second region. Forming a second conductive layer to be an electrode to be
Forming another insulating layer on the first region and the second region;
Forming a second insulating layer by removing at least a part of a portion present in the first region of the other insulating layer;
Removing the first sacrificial layer and the second sacrificial layer, and forming the microstructure having the first structural layer and the second structural layer in the first region; A method for manufacturing a mechanical device. In claim 16,
The second conductive layer includes a metal element;
A method of manufacturing a microelectromechanical device, wherein the second conductive layer and the semiconductor layer in the first region are reacted to form a compound of a semiconductor and a metal element.   16. The microelectromechanical device according to claim 1, wherein the microstructure includes a rotor formed of the first structure.   18. The method for manufacturing a micro electro mechanical device according to claim 16, wherein the microstructure includes a rotor formed of the first structure.

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