JP2008022315A

JP2008022315A - Thermal infrared detection circuit

Info

Publication number: JP2008022315A
Application number: JP2006192618A
Authority: JP
Inventors: Akihiko Furukawa; 彰彦古川; Masafumi Ueno; 雅史上野; Yasuhiro Kagawa; 泰宏香川; Yasuhiro Ozasayama; 泰浩小笹山
Original assignee: Mitsubishi Electric Corp
Current assignee: Mitsubishi Electric Corp
Priority date: 2006-07-13
Filing date: 2006-07-13
Publication date: 2008-01-31

Abstract

PROBLEM TO BE SOLVED: To provide a thermal infrared detection circuit of high sensitivity with reduced superimposition of flicker noise in a pixel signal read-out system. SOLUTION: A pixel 1 composed of thermal infrared sensors having sensitivity to infrared ray and temperature is arranged in a matrix shape, and a reference pixel 2 having sensitivity to temperature but no sensitivity to infrared ray, is arranged adjacent to the matrix of the pixel 1 in the direction of column in adjacent to the matrix. Difference between voltage from the pixel 1 and voltage of a bias line 11 is amplified by a differential amplifier circuit 14, and a pixel signal is read out according to infrared ray. The bias line 11 has resistance substantially same as a drive line 3, and receives supply of substantially same current. A bias voltage circuit 30 generates voltage equal to voltage from reference pixel 2, and applies the voltage to the bias line 11. COPYRIGHT: (C)2008,JPO&INPIT

Description

この発明は、入射赤外線による温度変化を２次元に配置された半導体センサで検出する赤外線固体撮像回路に関し、特に、半導体センサからの電気信号を増幅して出力する熱型赤外線検出回路に関する。 The present invention relates to an infrared solid-state imaging circuit that detects a temperature change caused by incident infrared rays using a two-dimensionally arranged semiconductor sensor, and more particularly to a thermal infrared detection circuit that amplifies and outputs an electrical signal from a semiconductor sensor.

熱型赤外線撮像回路では、断熱構造を有する画素を２次元に配列し、赤外線の入射による画素の温度変化を電気信号に変換することで、対象物の赤外線画像を得ている。赤外線撮像回路の画素には、温度を検出する半導体センサとしてシリコンのＰＮ接合ダイオードが使われることがある。この画素の構造は例えば非特許文献１に示されている。図８（ａ）及び（ｂ）は従来の画素構造を示す断面図及び斜視図である。画素１において、温度センサとなるダイオード９０２は、２本の長い支持脚１１０１によってシリコン基板１１０２に設けられた中空部１１０３の上に支持されており、ダイオード９０２の電極配線１１０４が支持脚１１０１に埋め込まれている。ダイオード９０２は、感度を高めるために複数個が直列に接続されている。中空部１１０３は、ダイオード９０２とシリコン基板１１０２との間の熱抵抗を高めて、断熱構造を形成している。ダイオード９０２は、基板１１０２と独立した層にする必要があるので、ＳＯＩ基板を用いてＳＯＩ層上に形成されており、ＳＯＩ層下の埋め込み酸化膜は中空構造を支持する構造体の一部になっている。また、ダイオード部に熱的に接触している赤外線吸収構造１１０６が、図の上方から入射する赤外線を効率良く吸収できるように、支持脚１１０１の上方に張り出した構造となっている。尚、図８(ｂ)では下部の構造を判りやすくするため、図の前方の部分での赤外線吸収構造を除いて描いてある。 In a thermal infrared imaging circuit, pixels having a heat insulating structure are two-dimensionally arranged, and an infrared image of an object is obtained by converting a temperature change of the pixel due to incidence of infrared rays into an electrical signal. A pixel of an infrared imaging circuit may use a silicon PN junction diode as a semiconductor sensor for detecting temperature. The structure of this pixel is shown in Non-Patent Document 1, for example. FIGS. 8A and 8B are a cross-sectional view and a perspective view showing a conventional pixel structure. In the pixel 1, a diode 902 serving as a temperature sensor is supported on a hollow portion 1103 provided in the silicon substrate 1102 by two long support legs 1101, and an electrode wiring 1104 of the diode 902 is embedded in the support legs 1101. It is. A plurality of diodes 902 are connected in series to increase sensitivity. The hollow portion 1103 increases the thermal resistance between the diode 902 and the silicon substrate 1102 to form a heat insulating structure. Since the diode 902 needs to be a layer independent of the substrate 1102, the diode 902 is formed on the SOI layer using an SOI substrate, and the buried oxide film under the SOI layer is part of the structure supporting the hollow structure. It has become. In addition, the infrared absorption structure 1106 that is in thermal contact with the diode portion has a structure that protrudes above the support leg 1101 so that infrared rays incident from above can be efficiently absorbed. In FIG. 8B, in order to make the structure of the lower part easy to understand, the structure is drawn excluding the infrared absorption structure in the front part of the figure.

赤外線が画素１に入射すると、赤外線吸収構造１１０６で吸収され、上記の断熱構造により画素１の温度が変化し、温度センサとなるダイオード９０２の順方向電圧特性が変化する。このダイオード９０２の順方向電圧特性の変化量を、所定の検出回路で読み取るこ
とにより、入射した赤外線量に応じた出力信号を取出すことができる。ダイオードの検出電圧は１ｕＶのように微弱であり、１００倍程度に増幅する必要がある。一般的に、ダイオードや、ＭＯＳトランジスタは、微小電流や微弱電圧の揺らぎを伴っており、この揺らぎによるフリッカノイズ（１／ｆノイズとも呼ばれる）が発生するので、高感度で信号読み出しを行うには、信号読み出し系の回路自体でフリッカノイズの重畳を最小限に抑えることが重要である。また、２次元配置された画素から微弱な信号を単相入力の積分回路のみで増幅する場合には、（１）ダイオードに画素駆動電源電圧を与える駆動線の電圧降下によるオフセット分布の発生、（２）外部の環境温度によるノイズの重畳、（３）ダイオードの自己加熱で発生する熱によるノイズの重畳により、高感度の赤外線検出画像が得られなかった。これら３つの問題を解決した電圧読み出し方式の熱型赤外線検出回路は、例えば特許文献１に示されている。 When infrared rays are incident on the pixel 1, the infrared rays are absorbed by the infrared absorption structure 1106, the temperature of the pixel 1 is changed by the heat insulation structure, and the forward voltage characteristics of the diode 902 serving as a temperature sensor are changed. By reading the change amount of the forward voltage characteristic of the diode 902 with a predetermined detection circuit, an output signal corresponding to the amount of incident infrared rays can be taken out. The detection voltage of the diode is as weak as 1 uV and needs to be amplified about 100 times. In general, diodes and MOS transistors are accompanied by fluctuations in minute currents and weak voltages, and flicker noise (also called 1 / f noise) is generated by these fluctuations. It is important to minimize the flicker noise superposition in the signal readout circuit itself. When a weak signal from a two-dimensionally arranged pixel is amplified only by a single-phase input integration circuit, (1) generation of an offset distribution due to a voltage drop of a drive line that applies a pixel drive power supply voltage to a diode; 2) A high-sensitivity infrared detection image could not be obtained due to noise superposition due to external environmental temperature and (3) noise superposition due to heat generated by self-heating of the diode. A voltage readout type thermal infrared detection circuit that solves these three problems is disclosed in Patent Document 1, for example.

図９は上記の３つの問題を解決するためになされた従来の電圧読み出し方式の熱型赤外線検出回路及び差動増幅器に相当する回路図である。１は赤外線吸収構造と断熱構造を備えた複数個のダイオードが直列接続され、入射赤外線に対して感度を有する画素で、Ｍ行Ｎ列（Ｍ、Ｎは自然数）のマトリクス状に配置される。２は断熱構造を備えた複数個のダイオードが直列接続され、赤外線に対して無感度の参照画素である。参照画素２は、入射する赤外線に関係無く、画素１が受ける環境による素子の温度変化及び自己加熱による温度変化と同等の温度変化を検出することができるように赤外線吸収構造を除いた構造となっている。赤外線吸収構造を有しない画素は、例えば、図８（ａ）（ｂ）の画素１において赤外線吸収構造１１０６の形成を省略されたものである。３は画素１の陽極及び参照画素２の陽極を行毎に共通接続した駆動線、４は画素１の陰極を列毎に共通接続した信号線、５は参照画素２の陰極を一列に共通接続した参照信号線、６は信号線４の終端部に接続された定電流源、７は参照信号線５の終端部に接続された定電流源、８は選択スイッチ９を介して画素駆動電源１０を駆動線３に順次接続する垂直走査回路、１１は駆動線３と抵抗が実質的に同一であるバイアス線、１００はバイアス線の一端に接続された電圧を供給するバイアス電源である。１２は信号線４毎に設けられた定電流源６と実質的に同一の電流を流す定電流源でバイアス線１１に接続される。従って、バイアス線１１の抵抗及び電流は駆動線３と実質的に同一なので、バイアス線１１の電圧も駆動線３の電圧と実質的に同一となる。１３は参照信号線５に設けられた定電流源７と実質的に同一の電流を流す定電流源でバイアス線１１に接続される。１０１は各画素列の信号線４毎に設けられ、定電流源６の両端子の電圧と定電流源１２の両端子の電圧が差動入力される差動増幅器、１０２は参照画素列に設けられ、定電流源７の両端子の電圧と定電流源１３の両端子の電圧が差動入力される差動増幅器、１０３は画素列毎に設けられた差動増幅器１０１の出力と差動増幅器１０２の出力が差動入力される差動増幅器である。１０４は差動増幅器１０３の出力を順次選択し、差動増幅器１０３の信号を積分回路で一定時間積分処理して出力する水平駆動回路である。 FIG. 9 is a circuit diagram corresponding to a conventional thermal readout infrared detection circuit and differential amplifier of the voltage readout system made to solve the above three problems. Reference numeral 1 denotes a pixel having a plurality of diodes each having an infrared absorption structure and a heat insulation structure connected in series and having sensitivity to incident infrared rays, and is arranged in a matrix of M rows and N columns (M and N are natural numbers). Reference numeral 2 is a reference pixel that is insensitive to infrared rays, in which a plurality of diodes having a heat insulating structure are connected in series. The reference pixel 2 has a structure excluding the infrared absorption structure so that the temperature change of the element due to the environment received by the pixel 1 and the temperature change equivalent to the temperature change due to self-heating can be detected regardless of the incident infrared ray. ing. For example, the pixel that does not have the infrared absorption structure is obtained by omitting the formation of the infrared absorption structure 1106 in the pixel 1 in FIGS. 3 is a drive line in which the anode of the pixel 1 and the anode of the reference pixel 2 are commonly connected for each row, 4 is a signal line in which the cathode of the pixel 1 is commonly connected for each column, and 5 is a common connection of the cathode of the reference pixel 2 in one column. The reference signal line 6, a constant current source 6 connected to the terminal end of the signal line 4, 7 a constant current source connected to the terminal end of the reference signal line 5, and 8 a pixel drive power supply 10 via the selection switch 9. Is a vertical scanning circuit that sequentially connects to the drive line 3, 11 is a bias line having substantially the same resistance as the drive line 3, and 100 is a bias power source that supplies a voltage connected to one end of the bias line. A constant current source 12 is connected to the bias line 11 for supplying substantially the same current as the constant current source 6 provided for each signal line 4. Accordingly, since the resistance and current of the bias line 11 are substantially the same as those of the drive line 3, the voltage of the bias line 11 is also substantially the same as the voltage of the drive line 3. Reference numeral 13 denotes a constant current source that is provided in the reference signal line 5 and supplies substantially the same current as the constant current source 7 and is connected to the bias line 11. 101 is provided for each signal line 4 of each pixel column, and a differential amplifier in which the voltage at both terminals of the constant current source 6 and the voltage at both terminals of the constant current source 12 are input differentially, 102 is provided in the reference pixel column. A differential amplifier in which the voltage at both terminals of the constant current source 7 and the voltage at both terminals of the constant current source 13 are differentially input. 103 is the output of the differential amplifier 101 provided for each pixel column and the differential amplifier. This is a differential amplifier in which the output of 102 is differentially input. Reference numeral 104 denotes a horizontal drive circuit that sequentially selects the output of the differential amplifier 103 and integrates and outputs the signal of the differential amplifier 103 for a predetermined time by an integration circuit.

次に動作について説明する。まず、画素１に赤外線が入射していない状態を考える。垂直走査回路８によって順次選択される駆動線３は、選択スイッチ９を介して画素駆動電源１０が接続される。これに伴い画素１は定電流源６により一定電流で駆動され、順方向にバイアスされる。バイアス電源１００は垂直走査回路８の選択スイッチ９の制御信号と同期したパルスであり、バイアス線１１の電圧降下を考慮して、各列の差動増幅器１０１の差動入力端子対である反転端子と非反転端子間の電圧がほぼ同じになる電圧を出力する。このようにすることで、差動増幅器１０１は差動入力に差がほとんどない時の出力、即ち、準ゼロ基準電圧を出力する。参照画素２及び差動増幅器１０２は、画素１と差動増幅器１０１と同様の動作であり、準ゼロ基準電圧が出力される。差動増幅器１０３も差動増幅器１０１、１０２の出力がそれぞれの差動入力端子に入力されるので、バイアス電圧と画素駆動電圧との差を減算し、ゼロ基準電圧を出力する。 Next, the operation will be described. First, consider a state in which no infrared rays are incident on the pixel 1. The drive lines 3 sequentially selected by the vertical scanning circuit 8 are connected to the pixel drive power supply 10 via the selection switch 9. Accordingly, the pixel 1 is driven at a constant current by the constant current source 6 and is biased in the forward direction. The bias power supply 100 is a pulse synchronized with the control signal of the selection switch 9 of the vertical scanning circuit 8, and in consideration of the voltage drop of the bias line 11, an inverting terminal which is a differential input terminal pair of the differential amplifier 101 in each column. And a voltage at which the voltage between the non-inverting terminals is almost the same. In this way, the differential amplifier 101 outputs an output when there is almost no difference in the differential input, that is, a quasi-zero reference voltage. The reference pixel 2 and the differential amplifier 102 operate similarly to the pixel 1 and the differential amplifier 101, and output a quasi-zero reference voltage. The differential amplifier 103 also outputs the zero reference voltage by subtracting the difference between the bias voltage and the pixel drive voltage because the outputs of the differential amplifiers 101 and 102 are input to the respective differential input terminals.

画素１に赤外線が入射すると、選択され一定電流で駆動されるダイオードは赤外線によって温度上昇し、ダイオードの順方向電圧はΔＶだけ低下するので、差動増幅器の非反転端子の電圧はΔＶだけ高くなる。一方、参照画素は赤外線が入射しても、赤外線に対して無感度なので、ダイオードの順方向電圧は変化しない。したがって、差動増幅器１０１の出力は準ゼロ基準電圧より高くなるが、差動増幅器１０２の出力は準ゼロ基準電圧から変化がないことから、差動増幅器１０３の出力はゼロ基準電圧より高くなる。この増幅信号を水平駆動回路で順次取り出して、１行分の赤外線検出信号を得る。駆動線を順次選択し、上記の読み出し動作を繰り返し、さらに全画素の赤外線検出信号を信号処理することで、対象物の赤外線画像を得る。 When infrared rays are incident on the pixel 1, the temperature of the diode that is selected and driven by a constant current rises due to the infrared rays, and the forward voltage of the diode decreases by ΔV, so the voltage at the non-inverting terminal of the differential amplifier increases by ΔV. . On the other hand, even if infrared rays are incident on the reference pixel, the forward voltage of the diode does not change because it is insensitive to infrared rays. Accordingly, the output of the differential amplifier 101 is higher than the quasi-zero reference voltage, but the output of the differential amplifier 103 is higher than the zero reference voltage because the output of the differential amplifier 102 is not changed from the quasi-zero reference voltage. The amplified signals are sequentially taken out by a horizontal drive circuit to obtain an infrared detection signal for one row. By sequentially selecting the drive lines, repeating the above-described readout operation, and further processing the infrared detection signals of all the pixels, an infrared image of the object is obtained.

上記のように駆動線３と実質的に同一の電圧降下を有するバイアス線１１との信号を差動増幅器１０１で読み出すことで、上記（１）の問題を解決していた。さらに、参照画素でも検出する赤外線入射による温度変化以外の外部環境温度及び通電されることによるダイオードの自己加熱による温度を反映した参照画素信号を差動増幅器１０２で出力させ、差動積分回路１０３によって、画素１からの信号から差動増幅器１０２の出力を減算処理することで、上記（２）及び（３）の問題も解決していた。 As described above, the signal of the bias line 11 having substantially the same voltage drop as that of the drive line 3 is read by the differential amplifier 101, thereby solving the problem (1). Further, the differential amplifier 102 outputs a reference pixel signal reflecting the external environmental temperature other than the temperature change caused by the incidence of infrared light detected by the reference pixel and the temperature due to the self-heating of the diode due to energization, and the differential integration circuit 103 By subtracting the output of the differential amplifier 102 from the signal from the pixel 1, the problems (2) and (3) have been solved.

特開２００４−３６４２４１号公報（図７）Japanese Patent Laying-Open No. 2004-364241 (FIG. 7) Ｐｒｏｃ．ＳＰＩＥＶｏｌ．３６９８１９９９５５６頁から５６４頁（Ｆｉｇ．２）Proc. SPIE Vol. 3698 1999, pages 556 to 564 (Fig. 2)

上記のような従来の熱型赤外線検出回路では、上記（２）、（３）の問題を解決するために差動増幅器１０２とＮ個の差動増幅器１０３を追加していたので、これら多数の差動増幅器から発生するフリッカノイズが検出信号に重畳していた。従って画素信号の読み出しを高感度にできない問題点があった。 In the conventional thermal infrared detection circuit as described above, the differential amplifier 102 and the N differential amplifiers 103 are added to solve the problems (2) and (3). Flicker noise generated from the differential amplifier was superimposed on the detection signal. Therefore, there has been a problem that pixel signals cannot be read with high sensitivity.

この発明は、上記（２）、（３）の問題を解決するための回路構成を簡単化し、それによって画素信号読み出し系でのフリッカノイズの重畳を減らした高感度の熱型赤外線検出回路を得ることを目的とする。 The present invention simplifies the circuit configuration for solving the problems (2) and (3), and thereby obtains a highly sensitive thermal infrared detection circuit with reduced flicker noise superposition in the pixel signal readout system. For the purpose.

本発明の課題解決原理を説明する。図９に示す従来の熱型赤外線検出回路のバイアス線１１に上記（２）、（３）の問題を解決するための電圧である外部環境温度及び自己加熱による温度を反映した電圧を重畳させて、この電圧を差動増幅器１０１により画素１の検出電圧から減算するようにすれば、差動増幅器１０２、１０３は不要となる。参照画素２の電圧は外部環境温度及び自己加熱による温度を反映した電圧になっているが、この電圧が現れている参照信号線５をバイアス線１１に直接に接続することはできない。そこで、参照信号線５の電圧と同じ電圧を発生するバイアス電圧回路を構成し、この回路が発生した電圧をバイアス線１１に与えるようにした。 The problem solving principle of the present invention will be described. The bias line 11 of the conventional thermal infrared detection circuit shown in FIG. 9 is superimposed with a voltage reflecting the external environment temperature and the temperature due to self-heating, which are voltages for solving the problems (2) and (3). If this voltage is subtracted from the detection voltage of the pixel 1 by the differential amplifier 101, the differential amplifiers 102 and 103 become unnecessary. The voltage of the reference pixel 2 is a voltage reflecting the external environment temperature and the temperature due to self-heating, but the reference signal line 5 on which this voltage appears cannot be directly connected to the bias line 11. Therefore, a bias voltage circuit that generates the same voltage as the voltage of the reference signal line 5 is configured, and the voltage generated by this circuit is applied to the bias line 11.

この発明は、上記（２）、（３）の問題を解決するために追加する回路を簡単化したので、画素信号読み出し系でのフリッカノイズの重畳を減らすことができ、高感度の赤外線検出画像が得られる。 In the present invention, the circuit added to solve the problems (2) and (3) is simplified, so that the superimposition of flicker noise in the pixel signal readout system can be reduced, and a highly sensitive infrared detection image. Is obtained.

実施の形態１．
図１は、この発明の実施の形態１における電圧読み出し方式の熱型赤外線検出回路の回路図である。実際の画素はＭ行Ｎ列（Ｍ、Ｎは自然数）の画素が配列されているが、説明を簡単化するために画素エリアに３行Ｎ列の画素と画素エリアに隣接して１列の参照画素を配置した図を示した。 Embodiment 1 FIG.
FIG. 1 is a circuit diagram of a voltage readout type thermal infrared detection circuit according to Embodiment 1 of the present invention. Actual pixels are arranged in M rows and N columns (M and N are natural numbers). However, in order to simplify the description, pixels in 3 rows and N columns and one column adjacent to the pixel area are arranged in the pixel area. The figure which has arrange | positioned the reference pixel was shown.

図において、１は赤外線吸収構造と断熱構造を備えた複数個のダイオードが直列接続され、入射赤外線に対して感度を有する画素で、画素エリアに３行Ｎ列のマトリクス状に配置される。２は断熱構造を備えた複数個のダイオードが直列接続され、赤外線に対して無感度の参照画素で、画素エリアに隣接して１列配置される。３は画素１の陽極及び参照画素２の陽極を行毎に共通接続した駆動線、４は画素１の陰極を列毎に共通接続した信号線、５は参照画素２の陰極を一列に共通接続した参照信号線である。６は信号線４の終端部に接続された定電流源、７は参照信号線５の終端部に接続された定電流源である。８は選択スイッチ９を介して画素駆動電源１０を駆動線３に順次接続する垂直走査回路である。１１は駆動線３と実質的に同一の抵抗を有し、同一の電流が流れることにより同一の電圧降下を有するバイアス線である。１２は信号線４毎に設けられた定電流源６と実質的に同一の電流を流す定電流源でバイアス線１１に接続される。１３は参照信号線に設けられた定電流源７と実質的に同一の電流を流す定電流源でバイアス線１１に接続される。１４は各画素列の信号線４毎に設けられ、定電流源６の両端子の電圧と定電流源１２の両端子の電圧が差動入力され、一定時間積分増幅する差動積分回路である。１５は列毎の差動積分回路１４の出力を順次選択して出力する水平駆動回路である。 In the figure, reference numeral 1 denotes a pixel having a plurality of diodes each having an infrared absorption structure and a heat insulation structure connected in series and having sensitivity to incident infrared rays, and is arranged in a matrix of 3 rows and N columns in the pixel area. A plurality of diodes 2 having a heat insulating structure are connected in series, and reference pixels insensitive to infrared rays are arranged in a row adjacent to the pixel area. 3 is a drive line in which the anode of the pixel 1 and the anode of the reference pixel 2 are commonly connected for each row, 4 is a signal line in which the cathode of the pixel 1 is commonly connected for each column, and 5 is a common connection of the cathode of the reference pixel 2 in one column. Reference signal line. Reference numeral 6 denotes a constant current source connected to the terminal end of the signal line 4, and reference numeral 7 denotes a constant current source connected to the terminal end of the reference signal line 5. Reference numeral 8 denotes a vertical scanning circuit for sequentially connecting the pixel drive power supply 10 to the drive line 3 via the selection switch 9. Reference numeral 11 denotes a bias line having substantially the same resistance as that of the drive line 3 and having the same voltage drop when the same current flows. A constant current source 12 is connected to the bias line 11 for supplying substantially the same current as the constant current source 6 provided for each signal line 4. A constant current source 13 is connected to the bias line 11 and supplies a current substantially the same as the constant current source 7 provided on the reference signal line. A differential integration circuit 14 is provided for each signal line 4 of each pixel column, and differentially inputs the voltage at both terminals of the constant current source 6 and the voltage at both terminals of the constant current source 12 to integrate and amplify for a certain time. . A horizontal drive circuit 15 sequentially selects and outputs the outputs of the differential integration circuit 14 for each column.

バイアス線１１にバイアス電圧を供給するバイアス電圧回路３０の構成及び接続について説明する。バイアス電圧回路３０は、バイアス線１１に駆動線３と同じ電圧降下を生じさせるための電源であり、且つ、参照画素２が発生した環境温度及び自己加熱による温度を反映した電圧を受けてこれと同じ電圧を発生してバイアス線１１に与える回路である。バイアス電圧回路３０は入力端子３０Ａの電圧と等しくなるように制御されたバイアス電圧を端子３０Ｂからバイアス線１１に供給する。１６はバイアス電圧回路３０の入力端子３０Ａから反転端子に印加される参照画素２からの信号電圧とバイアス線１１に供給されるバイアス電圧との電圧差を増幅する差動増幅器である。参照画素２からの信号電圧は、参照信号線５を経てバイアス電圧回路３０の入力端子３０Ａに入力される。１７は差動増幅器１６の出力信号で制御され、画素駆動電源１０からバイアス電圧としてバイアス電圧回路３０の出力端子３０Ｂに接続されたバイアス線１１へ出力する駆動トランジスタである。駆動トランジスタ１７が出力するバイアス電圧は差動増幅器１６の非反転端子に接続され、差動増幅器１６と駆動トランジスタ１７でフィードバックループを構成している。１８は駆動トランジスタ１７の出力に接続される容量である。 The configuration and connection of the bias voltage circuit 30 that supplies the bias voltage to the bias line 11 will be described. The bias voltage circuit 30 is a power source for causing the bias line 11 to generate the same voltage drop as the drive line 3, and receives a voltage reflecting the environmental temperature generated by the reference pixel 2 and the temperature due to self-heating. In this circuit, the same voltage is generated and applied to the bias line 11. The bias voltage circuit 30 supplies a bias voltage controlled to be equal to the voltage of the input terminal 30A to the bias line 11 from the terminal 30B. A differential amplifier 16 amplifies the voltage difference between the signal voltage from the reference pixel 2 applied to the inverting terminal from the input terminal 30 A of the bias voltage circuit 30 and the bias voltage supplied to the bias line 11. The signal voltage from the reference pixel 2 is input to the input terminal 30 A of the bias voltage circuit 30 through the reference signal line 5. Reference numeral 17 denotes a drive transistor that is controlled by the output signal of the differential amplifier 16 and outputs the bias voltage from the pixel drive power supply 10 to the bias line 11 connected to the output terminal 30B of the bias voltage circuit 30. The bias voltage output from the drive transistor 17 is connected to the non-inverting terminal of the differential amplifier 16, and the differential amplifier 16 and the drive transistor 17 constitute a feedback loop. Reference numeral 18 denotes a capacitor connected to the output of the driving transistor 17.

本実施の形態では、駆動トランジスタ１７はＰＭＯＳトランジスタであり、ゲート電極及びソース電極にはそれぞれ差動増幅器１６の出力及び画素駆動電源１０が接続され、ドレイン電極に差動増幅器１６の非反転端子に接続される。 In the present embodiment, the drive transistor 17 is a PMOS transistor, the output of the differential amplifier 16 and the pixel drive power supply 10 are connected to the gate electrode and the source electrode, respectively, and the non-inverting terminal of the differential amplifier 16 is connected to the drain electrode. Connected.

図２は動作を説明する図で、図１に電圧モニター点を書き加えたものである。まず赤外線が入射していない場合を考える。Ｎ列目の画素１に注目して説明する。画素１に流れる電流をＩ１、画素駆動電源１０の電圧をＶｃｃ、選択スイッチ９の抵抗をＲｓｗ、Ｎ列までの駆動線の電圧降下をＶｒｎとする。定電流源６と定電流源７は実質的に同一の電流を流すので、参照画素２にも画素１と同じ電流Ｉ１が流れる。ノードＡ及びＢの電圧ＶＡ、ＶＢはそれぞれ、
ＶＡ＝Ｖｃｃ−Ｉ１×（Ｎ＋１）×Ｒｓｗ（１）
ＶＢ＝Ｖｃｃ−Ｉ１×（Ｎ＋１）×Ｒｓｗ−Ｖｒｎ（２）
となる。入射赤外線がなく、ある素子温度における画素１のダイオードの順方向電圧をＶｎとすると、ノードＣの電圧ＶＣは、
ＶＣ＝Ｖｃｃ−Ｉ１×（Ｎ＋１）×Ｒｓｗ−Ｖｒｎ−Ｖｎ（３）
となる。次に参照画素２に注目して説明する。参照画素２に流れる電流は、画素１と同じ電流Ｉ１であるから、参照画素２のダイオードの順方向電圧もＶｎであり、バイアス電圧回路の入力端子３０Ａの電圧Ｖ（３０Ａ）は、
Ｖ（３０Ａ）＝Ｖｃｃ−Ｉ１×（Ｎ＋１）×Ｒｓｗ−Ｖｎ（４）
となる。出力端子３０Ｂの電圧Ｖ（３０Ｂ）は、後述するバイアス電圧回路によって、Ｖ（３０Ａ）と等しくなるように制御される。したがって、出力端子３０Ｂの電圧は（４）式で示したもと等しくなる。バイアス線１１の電圧降下は画素１の駆動線３と実質的に同一であるため、ノードＤの電圧ＶＤは、
ＶＤ＝Ｖ（３０Ｂ）−Ｖｒｎ＝Ｖ（３０Ａ）−Ｖｒｎ（５）
であり、これに（４）式を代入すると、
ＶＤ＝Ｖｃｃ−Ｉ１×（Ｎ＋１）×Ｒｓｗ−Ｖｎ−Ｖｒｎ（６）
となり、ノードＣの電圧と等しくなる。これにより差動積分回路１４は赤外線非検出を示すゼロ基準電圧を出力し、水平駆動回路１５からもゼロ基準電圧が出力される。 FIG. 2 is a diagram for explaining the operation, in which voltage monitor points are added to FIG. First, consider the case where infrared rays are not incident. Description will be made with attention paid to the pixel 1 in the Nth column. It is assumed that the current flowing through the pixel 1 is I1, the voltage of the pixel drive power supply 10 is Vcc, the resistance of the selection switch 9 is Rsw, and the voltage drop of the drive line up to the N column is Vrn. Since the constant current source 6 and the constant current source 7 pass substantially the same current, the same current I1 as that of the pixel 1 also flows through the reference pixel 2. The voltages VA and VB at nodes A and B are respectively
VA = Vcc-I1 * (N + 1) * Rsw (1)
VB = Vcc-I1 * (N + 1) * Rsw-Vrn (2)
It becomes. When there is no incident infrared ray and the forward voltage of the diode of the pixel 1 at a certain element temperature is Vn, the voltage VC of the node C is
VC = Vcc-I1 * (N + 1) * Rsw-Vrn-Vn (3)
It becomes. Next, the description will be given with reference to the reference pixel 2. Since the current flowing through the reference pixel 2 is the same current I1 as the pixel 1, the forward voltage of the diode of the reference pixel 2 is also Vn, and the voltage V (30A) of the input terminal 30A of the bias voltage circuit is
V (30A) = Vcc-I1 * (N + 1) * Rsw-Vn (4)
It becomes. The voltage V (30B) of the output terminal 30B is controlled to be equal to V (30A) by a bias voltage circuit described later. Therefore, the voltage at the output terminal 30B becomes equal as shown in the equation (4). Since the voltage drop of the bias line 11 is substantially the same as that of the drive line 3 of the pixel 1, the voltage VD of the node D is
VD = V (30B) −Vrn = V (30A) −Vrn (5)
And substituting equation (4) for this,
VD = Vcc-I1 * (N + 1) * Rsw-Vn-Vrn (6)
And becomes equal to the voltage of the node C. As a result, the differential integration circuit 14 outputs a zero reference voltage indicating no infrared detection, and the horizontal drive circuit 15 also outputs a zero reference voltage.

次に、赤外線が入射された場合を考えると、赤外線によって画素１のダイオードが温められてダイオードの順方向電圧が低下する。この低下する電圧をΔＶ１とすると、画素１のダイオードの順方向電圧はＶｎ−ΔＶ１となる。Ｎ列目の差動積分回路のノードＣの電圧は、（３）式にΔＶ１を加えたものとなる。一方、参照画素２は赤外線に対して無感度なので、参照画素２のダイオードの順方向電圧はＶｎから変化しない。上述したように、バイアス電圧回路３０は参照画素２のダイオードの順方向電圧に基づいた電圧であるＶ（３０Ａ）と等しい電圧をバイアス電圧として出力する。このバイアス電圧は駆動線３と実質的に電圧降下の等しいバイアス線１１を介してＮ列目の差動積分回路に供給されるので、ノードＤの電圧は（６）式のままである。したがって、差動積分回路１４の差動入力端子対間にΔＶ１が印加され、このΔＶ１を積分増幅することで、駆動線の電圧降下によるオフセット分布と無関係に対象物の赤外線画像を得ることができる。したがって、本実施の形態は従来と同様に駆動線３と等しい電圧降下を有する駆動線１１により、駆動線の電圧降下によるオフセット分布をキャンセルした赤外線画像を得ることができる。 Next, considering the case where infrared rays are incident, the diode of the pixel 1 is warmed by the infrared rays and the forward voltage of the diode is lowered. If this decreasing voltage is ΔV1, the forward voltage of the diode of the pixel 1 is Vn−ΔV1. The voltage at the node C of the Nth column differential integration circuit is obtained by adding ΔV1 to the equation (3). On the other hand, since the reference pixel 2 is insensitive to infrared rays, the forward voltage of the diode of the reference pixel 2 does not change from Vn. As described above, the bias voltage circuit 30 outputs a voltage equal to V (30 A) that is a voltage based on the forward voltage of the diode of the reference pixel 2 as the bias voltage. Since this bias voltage is supplied to the N-th column differential integration circuit via the bias line 11 having substantially the same voltage drop as that of the drive line 3, the voltage at the node D remains in the formula (6). Therefore, ΔV1 is applied between the differential input terminal pair of the differential integration circuit 14, and by integrating and amplifying this ΔV1, an infrared image of the object can be obtained regardless of the offset distribution due to the voltage drop of the drive line. . Therefore, in the present embodiment, an infrared image in which the offset distribution due to the voltage drop of the drive line is canceled can be obtained by the drive line 11 having a voltage drop equal to that of the drive line 3 as in the prior art.

バイアス電圧回路３０の動作について説明する。バイアス電圧回路３０は差動増幅器１６の出力でＰＭＯＳトランジスタ１７を制御し、そのＰＭＯＳトランジスタ１７の出力が差動増幅器１６の非反転端子に入力されフィードバックループが構成されるので、非反転端子の電圧と反転端子の電圧は等しくなるように動作する。バイアス電圧回路３０の反転端子及び非反転端子はそれぞれ端子３０Ａ及び端子３０Ｂに接続されているので、Ｖ（３０Ａ）＝Ｖ（３０Ｂ）となる。まず、Ｖ（３０Ａ）＝Ｖ（３０Ｂ）＝Ｖｓ１となっている場合に、差動増幅器１６はＰＭＯＳトランジスタ１７がバイアス線１１に駆動線３と同じＩ１×（Ｎ＋１）の電流を供給するように、ＰＭＯＳトランジスタ１７のゲート電極に中間電位となる電圧Ｖｓｔを出力している。この定常状態から参照画素２が環境温度によって温められると、参照画素２の順方向電圧が下がり、その分だけ差動増幅器１６の反転端子に入力される電圧が非反転端子の入力電圧より上るので、差動増幅器１６の出力電圧は入力電圧差に応じて徐々に降下する。このときＰＭＯＳトランジスタ１７は、強くＯＮすることでＯＮ抵抗が低下するので、Ｖ（３０Ｂ）は徐々に上昇する。Ｖ（３０Ｂ）が上ると差動増幅器１６の入力電圧差が小さくなるので、差動増幅器１６の出力電圧は変化が小さくなりながら低くなる。このような動作を繰り返し、差動増幅器１６の出力電圧が一定値のＶｄｎになったところで、Ｖ（３０Ａ）＝Ｖ（３０Ｂ）＝Ｖｓ２となる。容量１８はＶ（３０Ｂ）が急激に変化して不安定になることを防いでいる。 The operation of the bias voltage circuit 30 will be described. The bias voltage circuit 30 controls the PMOS transistor 17 by the output of the differential amplifier 16, and the output of the PMOS transistor 17 is input to the non-inverting terminal of the differential amplifier 16 so that a feedback loop is formed. And the voltage at the inverting terminal operate to be equal. Since the inverting terminal and the non-inverting terminal of the bias voltage circuit 30 are connected to the terminal 30A and the terminal 30B, respectively, V (30A) = V (30B). First, when V (30A) = V (30B) = Vs1, the differential amplifier 16 causes the PMOS transistor 17 to supply the same current I1 × (N + 1) as that of the drive line 3 to the bias line 11. The voltage Vst, which is an intermediate potential, is output to the gate electrode of the PMOS transistor 17. When the reference pixel 2 is warmed by the ambient temperature from this steady state, the forward voltage of the reference pixel 2 decreases, and the voltage input to the inverting terminal of the differential amplifier 16 is higher than the input voltage of the non-inverting terminal. The output voltage of the differential amplifier 16 gradually decreases according to the input voltage difference. At this time, since the ON resistance of the PMOS transistor 17 is lowered by being strongly turned on, V (30B) gradually increases. When V (30B) rises, the input voltage difference of the differential amplifier 16 becomes small, so that the output voltage of the differential amplifier 16 becomes low while the change is small. Such an operation is repeated, and when the output voltage of the differential amplifier 16 becomes a constant value Vdn, V (30A) = V (30B) = Vs2. The capacitor 18 prevents V (30B) from changing suddenly and becoming unstable.

参照画素２の順方向電圧が上がった場合は、差動増幅器１６の反転端子に入力される電圧が非反転端子の入力電圧より下がるので、差動増幅器１６の出力電圧は入力電圧差に応じて徐々に上昇する。このときＰＭＯＳトランジスタ１７は、弱くＯＮするようになることでＯＮ抵抗が上昇するので、Ｖ（３０Ｂ）は徐々に降下する。Ｖ（３０Ｂ）が下がると差動増幅器１６の入力電圧差が小さくなるので、差動増幅器１６の出力電圧は変化が小さくなりながら高くなる。このような動作を繰り返し、差動増幅器１６の出力電圧が一定値のＶｕｐになったところで、Ｖ（３０Ａ）＝Ｖ（３０Ｂ）＝Ｖｓ３となる。 When the forward voltage of the reference pixel 2 rises, the voltage input to the inverting terminal of the differential amplifier 16 falls below the input voltage of the non-inverting terminal, so that the output voltage of the differential amplifier 16 depends on the input voltage difference. Rise gradually. At this time, since the PMOS transistor 17 is turned on weakly and the ON resistance is increased, V (30B) gradually decreases. When V (30B) decreases, the input voltage difference of the differential amplifier 16 decreases, so the output voltage of the differential amplifier 16 increases while the change decreases. Such an operation is repeated, and when the output voltage of the differential amplifier 16 reaches a constant value Vup, V (30A) = V (30B) = Vs3.

したがって、バイアス電圧回路３０は、参照画素２が検出する温度によって変化する信号電圧に応じて、この参照画素２からの信号電圧とバイアス電圧を等しくなるように制御することができる。本実施の形態のバイアス電圧回路３０は、従来のバイアス電源が素子の温度と無関係な電圧を供給するのとは異なり、参照画素２が検出する温度を反映した電圧を供給することができる。 Therefore, the bias voltage circuit 30 can control the signal voltage from the reference pixel 2 to be equal to the bias voltage in accordance with the signal voltage that changes depending on the temperature detected by the reference pixel 2. The bias voltage circuit 30 of the present embodiment can supply a voltage reflecting the temperature detected by the reference pixel 2, unlike the conventional bias power supply that supplies a voltage that is independent of the temperature of the element.

次に外部の環境温度とダイオードの自己加熱による温度によるノイズをキャンセルできることを説明する。まず赤外線が入射していない場合を考える。参照画素２は画素１から赤外線吸収構造を除いた構造となっているので、両画素のダイオードの温度が同一であれば、両画素のダイオードの順方向電圧も同一となる。画素１と参照画素２は同一チップ内にあるので、同一の環境温度であり、両画素のダイオードの順方向電圧は同一となる。また、画素１の自己加熱による熱は電流が継続して流れることで発生するので、本実施の形態のように画素１と参照画素２が同一のタイミングで同一の電流で駆動されることで、両画素の自己加熱による温度上昇は同一となる。これにより両画素のダイオードの順方向電圧も同一となる。ダイオードの順方向電圧は、温度が上昇しΔＶ２だけ低下すると、初期の順方向電圧ＶｎからＶｎ−ΔＶ２となる。画素１の信号を読み出すＮ列目の差動積分回路のノードＣの電圧は、（３）式にΔＶ２を加えたものとなる。一方、参照画素２からの信号電圧、即ち入力端子３０Ａの電圧Ｖ（３０Ａ）も（４）式にΔＶ２を加えたものとなる。差動増幅器１６の反転端子にも画素２からΔＶ２だけ増加した電圧が入力され、非反転端子の電圧よりΔＶ２だけ高くなるので、差動増幅器１６の出力は徐々に降下する。それに応じてＰＭＯＳトランジスタ１７のＯＮ抵抗が低下することで、非反転端子の電圧であるバイアス電圧もΔＶ２だけ増加して一定値となる。このようにＮ列目の差動積分回路のノードＤの電圧は（６）式にΔＶ２を加えたものとなるので、ノードＣの電圧とノードＤの電圧は等しくなる。したがって、差動積分回路１４で減算処理をすることで、外部の環境温度とダイオードの自己加熱による温度によるノイズをキャンセルすることができる。ノードＤの電圧はバイアス線１１の電圧降下、外部の環境温度及びダイオードの自己加熱を反映している。そして、この電圧をノードＣの電圧から差し引いた電圧を差動積分回路１４が積分することにより、駆動線３の電圧降下、外部の環境温度及びダイオードの自己加熱の影響を全てキャンセルできる。赤外線が入射した場合は、画素１だけが赤外線による温度変化を受けて、画素１のダイオードの順方向電圧だけが変化し、差動積分回路１４は差動入力端子対間の電圧差に応じて積分増幅するので、環境温度とダイオードの自己加熱によるノイズを減らした赤外線画像を得ることができる。 Next, it will be described that noise due to external environmental temperature and temperature due to self-heating of the diode can be canceled. First, consider the case where infrared rays are not incident. Since the reference pixel 2 has a structure in which the infrared absorption structure is removed from the pixel 1, if the temperature of the diodes of both pixels is the same, the forward voltage of the diodes of both pixels is also the same. Since the pixel 1 and the reference pixel 2 are in the same chip, they have the same ambient temperature, and the forward voltages of the diodes of both pixels are the same. In addition, since the heat due to the self-heating of the pixel 1 is generated when the current continuously flows, the pixel 1 and the reference pixel 2 are driven with the same current at the same timing as in the present embodiment. The temperature rise due to self-heating of both pixels is the same. As a result, the forward voltages of the diodes of both pixels are the same. The forward voltage of the diode changes from the initial forward voltage Vn to Vn−ΔV2 when the temperature rises and decreases by ΔV2. The voltage at the node C of the Nth column differential integration circuit for reading out the signal of the pixel 1 is obtained by adding ΔV2 to the equation (3). On the other hand, the signal voltage from the reference pixel 2, that is, the voltage V (30A) of the input terminal 30A is obtained by adding ΔV2 to the equation (4). A voltage increased by ΔV2 is input from the pixel 2 to the inverting terminal of the differential amplifier 16 and becomes higher by ΔV2 than the voltage of the non-inverting terminal, so that the output of the differential amplifier 16 gradually drops. Accordingly, the ON resistance of the PMOS transistor 17 is lowered, so that the bias voltage, which is the voltage at the non-inverting terminal, is also increased by ΔV2 to a constant value. As described above, the voltage at the node D of the differential integration circuit in the Nth column is obtained by adding ΔV2 to the equation (6), so that the voltage at the node C is equal to the voltage at the node D. Therefore, by performing the subtraction process in the differential integration circuit 14, noise due to the external environmental temperature and the temperature due to the self-heating of the diode can be canceled. The voltage at the node D reflects the voltage drop of the bias line 11, the external environmental temperature, and the self heating of the diode. Then, the differential integration circuit 14 integrates the voltage obtained by subtracting this voltage from the voltage at the node C, thereby canceling all the influences of the voltage drop of the drive line 3, the external environment temperature, and the diode self-heating. When infrared rays are incident, only the pixel 1 receives a temperature change due to the infrared rays, and only the forward voltage of the diode of the pixel 1 changes, and the differential integration circuit 14 responds to the voltage difference between the differential input terminal pair. Since integral amplification is performed, it is possible to obtain an infrared image in which the ambient temperature and noise due to self-heating of the diode are reduced.

次に差動積分回路１４の構成について説明する。図３は差動積分回路の回路図である。図４は差動電圧電流変換アンプ２４の回路図である。図３及び図４は本件出願人が先に特許出願（特開２００２−１８８９５９号公報）したものである。 Next, the configuration of the differential integration circuit 14 will be described. FIG. 3 is a circuit diagram of the differential integration circuit. FIG. 4 is a circuit diagram of the differential voltage / current conversion amplifier 24. 3 and 4 are those previously filed by the present applicant (Japanese Patent Laid-Open No. 2002-188959).

図３に示す差動積分回路は、定電流源６の両端電圧と定電流源１２の両端電圧を入力側に接続した差動電圧電流変換アンプ２４と、差動電圧電流変換アンプ２４の出力側に接続された積分容量２５と、積分容量２５を周期的に電圧Ｖrefにリセットするように接続されたリセットトランジスタ２６で構成された積分回路部を備える。２７は積分後の出力をホールドするサンプルホールド回路で、バッファ２８を介して出力する。図４に示す差動電圧電流変換アンプ２４は、ＭＯＳトランジスタＱ１乃至Ｑ５からなる差動入力のカレントミラー回路である。差動積分回路１４は、従来の差動増幅器と同等のトランジスタ数で積分回路部を構成しているので、従来と同等のフリッカノイズで積分増幅を行うことができる。 The differential integration circuit shown in FIG. 3 includes a differential voltage / current conversion amplifier 24 in which the voltage across the constant current source 6 and the voltage across the constant current source 12 are connected to the input side, and the output side of the differential voltage / current conversion amplifier 24. And an integration circuit unit composed of a reset transistor 26 connected so as to periodically reset the integration capacitor 25 to the voltage Vref. A sample and hold circuit 27 holds the output after integration, and outputs it through the buffer 28. The differential voltage / current conversion amplifier 24 shown in FIG. 4 is a differential input current mirror circuit including MOS transistors Q1 to Q5. Since the differential integration circuit 14 forms an integration circuit unit with the same number of transistors as that of the conventional differential amplifier, it is possible to perform integral amplification with flicker noise equivalent to that of the conventional differential amplifier.

本実施の形態では、従来のＮ＋１個の差動増幅器（差動増幅器１０２とＮ個の差動増幅器１０３）を１個の差動増幅器１６だけにしたので、差動増幅器のフリッカノイズを大幅に削減できる。したがって、画素信号読み出し系の回路を簡単化したことで、画素信号読み出し系でのフリッカノイズの重畳を減らすことができ、高感度の赤外線検出画像が得られる。 In the present embodiment, the conventional N + 1 differential amplifiers (the differential amplifier 102 and the N differential amplifiers 103) are only one differential amplifier 16, so that the flicker noise of the differential amplifier is greatly reduced. Can be reduced. Therefore, by simplifying the pixel signal readout system circuit, it is possible to reduce the overlap of flicker noise in the pixel signal readout system and obtain a highly sensitive infrared detection image.

尚、ＭＯＳトランジスタのフリッカノイズは、酸化膜中のキャリアの捕獲と放出が原因とされており、埋め込みチャネル型のＰＭＯＳトランジスタは、表面チャネル型のＮＭＯＳトランジスタに比べてフリッカノイズが小さいので、ＰＭＯＳトランジスタを使用する方が適している。容量１８の容量値は、ＰＭＯＳトランジスタ出力の安定を向上させるもので、動作周波数を考慮して差動積分回路１４のそれぞれの差動入力端子におけるフリッカノイズを含むノイズ成分を同等にするように定めることができる。 The flicker noise of the MOS transistor is caused by the trapping and emission of carriers in the oxide film, and the buried channel type PMOS transistor has a smaller flicker noise than the surface channel type NMOS transistor. It is better to use The capacitance value of the capacitor 18 improves the stability of the output of the PMOS transistor, and is determined so that the noise components including the flicker noises at the respective differential input terminals of the differential integration circuit 14 are equal in consideration of the operating frequency. be able to.

また、バイアス電圧回路３０の駆動トランジスタとしてＰＭＯＳトランジスタを使用した場合で説明したが、バイポーラトランジスタを使用することもできる。電流パスに酸化膜が関係しないバイポーラトランジスタはフリッカノイズをＭＯＳトランジスタより小さくできるので、さらに熱型赤外線検出回路を高感度化することができる。以下に説明する。 Further, although the case where a PMOS transistor is used as the drive transistor of the bias voltage circuit 30 has been described, a bipolar transistor can also be used. Bipolar transistors that do not involve an oxide film in the current path can make flicker noise smaller than that of MOS transistors, so that the thermal infrared detection circuit can be made more sensitive. This will be described below.

図５は、この発明で用いるバイアス電圧回路の他の一例を示す回路図である。図において同一の記号は同一或いは相当するものであり、１７はＰＮＰバイポーラトランジスタ、１８はＰＮＰバイポーラトランジスタ１７の出力に接続される容量である。入力端子３０Ａは差動増幅器１６の反転端子に接続され、出力端子３０Ｂは差動増幅器１６の非反転端子に接続される。３０Ｃは差動増幅器１６の出力モニター点である。ＰＮＰバイポーラトランジスタ１７のエミッタ電極には画素駆動電源１０が接続され、ベース電極は差動増幅器１６の出力が接続され、コレクタ電極からバイアス電圧を端子３０Ｂに出力する。 FIG. 5 is a circuit diagram showing another example of the bias voltage circuit used in the present invention. In the figure, the same symbols are the same or equivalent, 17 is a PNP bipolar transistor, and 18 is a capacitor connected to the output of the PNP bipolar transistor 17. The input terminal 30A is connected to the inverting terminal of the differential amplifier 16, and the output terminal 30B is connected to the non-inverting terminal of the differential amplifier 16. 30C is an output monitoring point of the differential amplifier 16. The pixel drive power supply 10 is connected to the emitter electrode of the PNP bipolar transistor 17, the output of the differential amplifier 16 is connected to the base electrode, and a bias voltage is output from the collector electrode to the terminal 30B.

次に動作について説明する。Ｖ（３０Ａ）＝Ｖ（３０Ｂ）＝Ｖｓ１となっている場合に、差動増幅器１６はバイアス線１１に駆動線３と同じＩ１×（Ｎ＋１）の電流を供給するように、ＰＮＰバイポーラトランジスタ１７のベース電極に中間電位となる電圧Ｖｓｔを出力している。図で示す矢印の向きの電圧差ΔＶ３を正として、この電圧差が端子３０Ａ、３０Ｂ間に入力されると、Ｖ（３０Ｃ）は上昇する。ＰＮＰバイポーラトランジスタ１７のエミッタ・ベース間電圧が低くなり、ＰＮＰバイポーラトランジスタ１７は弱くＯＮするようになることでエミッタ・コレクタ間の抵抗が上昇するので、Ｖ（３０Ｂ）は徐々に降下する。Ｖ（３０Ｂ）が降下すると差動増幅器１６の入力電圧差が小さくなるので、差動増幅器１６の出力電圧は変化が小さくなりながら高くなる。このような動作を繰り返し、差動増幅器１６の出力電圧が一定値のＶｕｐになったところで、Ｖ（３０Ａ）＝Ｖ（３０Ｂ）＝Ｖｓ２となる。電圧差ΔＶ３が負の場合は、上記の正の場合と逆の関係になるだけで、差動増幅器１６の出力電圧がＶｓｔより低い一定値のＶｄｎになったところで、Ｖ（３０Ａ）＝Ｖ（３０Ｂ）＝Ｖｓ３となる。したがって、駆動トランジスタとしてＰＮＰバイポーラトランジスタを使用した場合も、バイアス電圧回路３０は、入力端子に入力された電圧と等しくなるようにバイアス電圧を制御することができる。 Next, the operation will be described. When V (30A) = V (30B) = Vs1, the differential amplifier 16 supplies the same current I1 × (N + 1) as that of the drive line 3 to the bias line 11, so that the PNP bipolar transistor 17 A voltage Vst that is an intermediate potential is output to the base electrode. When the voltage difference ΔV3 in the direction of the arrow shown in the figure is positive and this voltage difference is input between the terminals 30A and 30B, V (30C) rises. Since the emitter-base voltage of the PNP bipolar transistor 17 is lowered and the PNP bipolar transistor 17 is turned ON weakly, the resistance between the emitter and the collector increases, so that V (30B) gradually decreases. When V (30B) decreases, the input voltage difference of the differential amplifier 16 decreases, so that the output voltage of the differential amplifier 16 increases while the change decreases. Such an operation is repeated, and when the output voltage of the differential amplifier 16 reaches a constant value Vup, V (30A) = V (30B) = Vs2. When the voltage difference ΔV3 is negative, the relationship is merely opposite to the above positive case. When the output voltage of the differential amplifier 16 becomes a constant value Vdn lower than Vst, V (30A) = V ( 30B) = Vs3. Therefore, even when a PNP bipolar transistor is used as the drive transistor, the bias voltage circuit 30 can control the bias voltage to be equal to the voltage input to the input terminal.

実施の形態２．
実施の形態１では、参照画素２の１列を画素エリアに隣接して配置した場合で説明したが、参照画素２を１つ使用した場合でも、信号読み出し系の回路自体でフリッカノイズの重畳を最小限に抑えて、高感度の熱型赤外線検出回路を得ることができる。また、実施の形態１に比べ自己加熱によるノイズ重畳を厳密に考慮しなくても良い場合に適用できる。 Embodiment 2. FIG.
In the first embodiment, the case where one row of reference pixels 2 is arranged adjacent to the pixel area has been described. However, even when one reference pixel 2 is used, flicker noise is superimposed by the signal readout circuit itself. A highly sensitive thermal infrared detection circuit can be obtained with a minimum. Further, the present invention can be applied when it is not necessary to strictly consider noise superposition due to self-heating as compared with the first embodiment.

図６は、この発明の実施の形態２における電圧読み出し方式の熱型赤外線検出回路の回路図である。実際の画素はＭ行Ｎ列（Ｍ、Ｎは自然数）の画素が配列されているが、説明を簡単化するために、画素エリアに３行Ｎ列の画素１を配置した図を示した。図において、図１と同一の記号は同一或いは相当するものでる。１９は選択スイッチ９と実質的に同一の抵抗となるスイッチであり、ゲート電極に回路電源電圧Ｖｄｄが印加され、実質的に同一の電圧降下を発生する。２０はバイアス電圧回路３０の入力端子３０Ａに接続された容量である。容量２０の容量値は、入力電圧の急激な変化を防ぎバイアス電圧回路３０の出力の安定を向上させるもので、動作周波数との兼ね合いで定めることができる。動作周波数を考慮したノイズの帯域（１Ｈｚから２０ｋＨｚ）で考えた場合、例えば容量２０及び容量１８の容量をそれぞれ０．１ｕＦ及び５０ｕＦにすると、差動積分回路１４のそれぞれの差動入力端子におけるフリッカノイズを含むノイズ電圧を容量がない場合に比べて約３３％低減することができた。 FIG. 6 is a circuit diagram of a voltage readout type thermal infrared detection circuit according to Embodiment 2 of the present invention. Although actual pixels are arranged in M rows and N columns (M and N are natural numbers), in order to simplify the description, a diagram in which pixels 1 in 3 rows and N columns are arranged in the pixel area is shown. In the figure, the same symbols as those in FIG. 1 are the same or equivalent. Reference numeral 19 denotes a switch having substantially the same resistance as that of the selection switch 9, and the circuit power supply voltage Vdd is applied to the gate electrode to generate substantially the same voltage drop. Reference numeral 20 denotes a capacitor connected to the input terminal 30 A of the bias voltage circuit 30. The capacitance value of the capacitor 20 prevents the sudden change of the input voltage and improves the stability of the output of the bias voltage circuit 30 and can be determined in consideration of the operating frequency. When considering the noise band (1 Hz to 20 kHz) in consideration of the operating frequency, for example, if the capacitance of the capacitor 20 and the capacitor 18 is 0.1 uF and 50 uF, respectively, the flicker at each differential input terminal of the differential integration circuit 14 The noise voltage including noise could be reduced by about 33% compared to the case where there was no capacity.

図７は動作を説明する図で、図６に電圧モニター点を書き加えたものである。まず赤外線が入射していない場合を考える。Ｎ列目の画素１に注目して説明する。画素１に流れる電流をＩ１、画素駆動電源１０の電圧をＶｃｃ、選択スイッチ９の抵抗をＲｓｗ、Ｎ列までの駆動線３の電圧降下をＶｒｎとする。定電流源６と定電流源７は実質的に同一の電流を流すので、参照画素２にも画素１と同じ電流Ｉ１が流れる。ノードＡ及びＢの電圧ＶＡ、ＶＢはそれぞれ、
ＶＡ＝Ｖｃｃ−Ｉ１×Ｎ×Ｒｓｗ（７）
ＶＢ＝Ｖｃｃ−Ｉ１×Ｎ×Ｒｓｗ−Ｖｒｎ（８）
となる。入射赤外線がなく、ある素子温度における画素１のダイオードの順方向電圧をＶｎとすると、ノードＣの電圧ＶＣは、
ＶＣ＝Ｖｃｃ−Ｉ１×Ｎ×Ｒｓｗ−Ｖｒｎ−Ｖｎ（９）
となる。次に参照画素２に注目して説明する。参照画素２に流れる電流は、画素１と同じ電流Ｉ１であるから、参照画素２のダイオードの順方向電圧もＶｎであり、バイアス電圧回路の入力端子３０Ａの電圧Ｖ（３０Ａ）は、
Ｖ（３０Ａ）＝Ｖｃｃ−Ｖｎ（１０）
となる。出力端子３０Ｂの電圧Ｖ（３０Ｂ）は、バイアス電圧回路３０によって、Ｖ（３０Ａ）と等しくなるように制御されるので、出力端子３０Ｂの電圧は（１０）式で示したもと等しくなる。バイアス線１１の電圧降下は、画素１の駆動線３と実質的に同一であるため、ノードＤの電圧ＶＤは、
ＶＤ＝Ｖ（３０Ｂ）−Ｉ１×Ｎ×Ｒｓｗ−Ｖｒｎ
＝Ｖ（３０Ａ）−Ｉ１×Ｎ×Ｒｓｗ−Ｖｒｎ（１１）
であり、これに（１０）式を代入すると、
ＶＤ＝Ｖｃｃ−Ｖｎ−Ｉ１×Ｎ×Ｒｓｗ−Ｖｒｎ（１２）
となり、ノードＣの電圧と等しくなる。これにより差動積分回路１４は赤外線非検出を示すゼロ基準電圧を出力し、水平駆動回路１５からもゼロ基準電圧が出力される。 FIG. 7 is a diagram for explaining the operation, in which voltage monitor points are added to FIG. First, consider the case where infrared rays are not incident. Description will be made with attention paid to the pixel 1 in the Nth column. It is assumed that the current flowing through the pixel 1 is I1, the voltage of the pixel drive power supply 10 is Vcc, the resistance of the selection switch 9 is Rsw, and the voltage drop of the drive line 3 up to the N column is Vrn. Since the constant current source 6 and the constant current source 7 pass substantially the same current, the same current I1 as that of the pixel 1 also flows through the reference pixel 2. The voltages VA and VB at nodes A and B are respectively
VA = Vcc−I1 × N × Rsw (7)
VB = Vcc-I1 * N * Rsw-Vrn (8)
It becomes. When there is no incident infrared ray and the forward voltage of the diode of the pixel 1 at a certain element temperature is Vn, the voltage VC of the node C is
VC = Vcc-I1 * N * Rsw-Vrn-Vn (9)
It becomes. Next, the description will be given with reference to the reference pixel 2. Since the current flowing through the reference pixel 2 is the same current I1 as the pixel 1, the forward voltage of the diode of the reference pixel 2 is also Vn, and the voltage V (30A) of the input terminal 30A of the bias voltage circuit is
V (30A) = Vcc-Vn (10)
It becomes. Since the voltage V (30B) of the output terminal 30B is controlled by the bias voltage circuit 30 so as to be equal to V (30A), the voltage of the output terminal 30B becomes equal to that shown by the equation (10). Since the voltage drop of the bias line 11 is substantially the same as that of the drive line 3 of the pixel 1, the voltage VD of the node D is
VD = V (30B) -I1 * N * Rsw-Vrn
= V (30A) -I1 * N * Rsw-Vrn (11)
And substituting equation (10) for this,
VD = Vcc-Vn-I1 * N * Rsw-Vrn (12)
And becomes equal to the voltage of the node C. As a result, the differential integration circuit 14 outputs a zero reference voltage indicating no infrared detection, and the horizontal drive circuit 15 also outputs a zero reference voltage.

次に、赤外線が入射された場合を考えると、赤外線によって画素１のダイオードが温められてダイオードの順方向電圧が低下する。この低下する電圧をΔＶ１とすると、画素１のダイオードの順方向電圧はＶｎ−ΔＶ１となる。Ｎ列目の差動積分回路のノードＣの電圧は、（９）式にΔＶ１を加えたものとなる。一方、参照画素２は赤外線に対して無感度なので、参照画素２のダイオードの順方向電圧Ｖｎは変化しない。上述したように、バイアス電圧回路３０は参照画素２のダイオードの順方向電圧に基づいた電圧であるＶ（３０Ａ）と等しい電圧をバイアス電圧として出力する。このバイアス電圧は駆動線３と実質的に電圧降下の等しいバイアス線１１を介してＮ列目の差動積分回路に供給さるので、ノードＤの電圧は（１２）式のままである。したがって、差動積分回路１４の差動入力端子対間にΔＶ１が印加され、このΔＶ１を積分増幅することで、実施の形態１と同様に駆動線３と等しい電圧降下を有する駆動線１１により、駆動線の電圧降下によるオフセット分布と無関係に対象物の赤外線画像を得ることができる。 Next, considering the case where infrared rays are incident, the diode of the pixel 1 is warmed by the infrared rays and the forward voltage of the diode is lowered. If this decreasing voltage is ΔV1, the forward voltage of the diode of the pixel 1 is Vn−ΔV1. The voltage at the node C of the Nth column differential integration circuit is obtained by adding ΔV1 to the equation (9). On the other hand, since the reference pixel 2 is insensitive to infrared rays, the forward voltage Vn of the diode of the reference pixel 2 does not change. As described above, the bias voltage circuit 30 outputs a voltage equal to V (30 A) that is a voltage based on the forward voltage of the diode of the reference pixel 2 as the bias voltage. Since this bias voltage is supplied to the N-th column differential integration circuit via the bias line 11 having substantially the same voltage drop as that of the drive line 3, the voltage at the node D remains in the equation (12). Therefore, ΔV1 is applied between the differential input terminal pair of the differential integration circuit 14, and by integrating and amplifying this ΔV1, the drive line 11 having a voltage drop equal to that of the drive line 3 as in the first embodiment is used. An infrared image of the object can be obtained regardless of the offset distribution due to the voltage drop of the drive line.

本実施の形態は、自己加熱による温度上昇によるノイズ重畳を厳密に考慮しなくても良い場合を考えるので、実施の形態１の参照画素２とは異なるものを使用することができる。参照画素２は１つであり、実施の形態１に比べて配置する場所の自由度が高いので、参照画素２の構造変更がある程度自由にできる。本実施の形態では、画素１は駆動線３で選択された場合のみ電流が流れるが、参照画素２は画像撮像動作中に電流が流れ続けるので、画素１に比べて自己加熱の影響が大きくなる。そこで、参照画素２の構造は実施の形態１とは異なり、自己加熱によって発生する熱を逃がす構造を採用することで、自己加熱の影響を極力抑えることができる。例えば、参照画素２の断熱構造は無くさず、図８の赤外線吸収構造１１０６を取り除いた部分に、放熱用の金属層を設けることで参照画素２の熱抵抗を下げることができる。このようにすることで、画素１と参照画素２は、同一の環境温度を受け、異なる自己加熱による熱が発生してもダイオード自体の温度を同等にできる。 Since this embodiment considers the case where it is not necessary to strictly consider noise superposition due to temperature rise due to self-heating, a different pixel from the reference pixel 2 of the first embodiment can be used. Since the number of reference pixels 2 is one and the degree of freedom of arrangement is higher than that in the first embodiment, the structure of the reference pixels 2 can be freely changed to some extent. In the present embodiment, current flows only when the pixel 1 is selected by the drive line 3, but since the current continues to flow during the image capturing operation of the reference pixel 2, the influence of self-heating is greater than that of the pixel 1. . Therefore, unlike the first embodiment, the structure of the reference pixel 2 can suppress the influence of self-heating as much as possible by adopting a structure that releases heat generated by self-heating. For example, the heat insulating structure of the reference pixel 2 is not lost, and the heat resistance of the reference pixel 2 can be lowered by providing a heat dissipation metal layer in a portion where the infrared absorption structure 1106 of FIG. 8 is removed. By doing in this way, the pixel 1 and the reference pixel 2 receive the same environmental temperature, and even if the heat | fever by different self-heating generate | occur | produces, the temperature of diode itself can be made equivalent.

画素１と参照画素２の環境温度によるダイオードの順方向電圧の低下をΔＶ４とし、画素１と参照画素２の自己加熱によるダイオードの順方向電圧の低下をそれぞれΔＶ５１とΔＶ５２とする。ここで赤外線が入射していない場合を考えると、Ｎ列目の差動積分回路のノードＣの電圧ＶＣは、（９）式にΔＶ４とΔＶ５１を加えたものであり、
ＶＣ＝Ｖｃｃ−Ｉ１×Ｎ×Ｒｓｗ−Ｖｒｎ−Ｖｎ＋ΔＶ４＋ΔＶ５１（１３）
となる。一方、Ｎ列目の差動積分回路のノードＤの電圧ＶＤは、（１２）式にΔＶ４とΔＶ５２を加えたものであり、
ＶＤ＝Ｖｃｃ−Ｖｎ−Ｉ１×Ｎ×Ｒｓｗ−Ｖｒｎ＋ΔＶ４＋ΔＶ５２（１４）
となる。次に赤外線が入射した場合は、画素１のダイオードの順方向特性がΔＶ１低下すると、ノードＣの電圧は（１３）式にΔＶ１が加わり、差動増幅器１４の入力端子対間にΔＶ１＋ΔＶ５１−ΔＶ５２の電圧が印加されるので、このΔＶ１＋ΔＶ５１−ΔＶ５２を積分増幅する。即ち、外部の環境温度によるノイズΔＶ４は実施の形態１と同様にキャンセルでき、自己加熱による温度上昇によるノイズ重畳はΔＶ５１−ΔＶ５２のように緩和できる。したがって、外部の環境温度によるノイズを減らし、ダイオードの自己加熱によるノイズを緩和した赤外線画像を得ることができる。 A decrease in the forward voltage of the diode due to the environmental temperature of the pixel 1 and the reference pixel 2 is denoted by ΔV4, and a decrease in the forward voltage of the diode due to the self-heating of the pixel 1 and the reference pixel 2 is denoted by ΔV51 and ΔV52, respectively. Considering the case where infrared rays are not incident, the voltage VC at the node C of the N-th column differential integration circuit is obtained by adding ΔV4 and ΔV51 to the equation (9).
VC = Vcc−I1 × N × Rsw−Vrn−Vn + ΔV4 + ΔV51 (13)
It becomes. On the other hand, the voltage VD at the node D of the differential integration circuit in the Nth column is obtained by adding ΔV4 and ΔV52 to the equation (12).
VD = Vcc−Vn−I1 × N × Rsw−Vrn + ΔV4 + ΔV52 (14)
It becomes. Next, when infrared rays are incident, when the forward characteristic of the diode of the pixel 1 is decreased by ΔV1, the voltage at the node C is added with ΔV1 to the equation (13), and ΔV1 + ΔV51−ΔV52 is added between the input terminal pair of the differential amplifier 14. Since a voltage is applied, this ΔV1 + ΔV51−ΔV52 is integrated and amplified. That is, the noise ΔV4 due to the external environmental temperature can be canceled as in the first embodiment, and the noise superposition due to the temperature rise due to self-heating can be mitigated as ΔV51−ΔV52. Therefore, it is possible to obtain an infrared image in which noise due to external environmental temperature is reduced and noise due to self-heating of the diode is reduced.

上記の参照画素２の構造変更に加えて、参照画素２の熱抵抗と積分時間を調整することで、ダイオードの自己加熱によるノイズをさらに減らした赤外線画像を得ることができる。画素１と参照画素２は一定の電流で駆動されるので、消費電流によるジュール熱は一定である。画素１は断熱構造であり、ジュール熱によって徐々に温度上昇するが、駆動終了時、即ち積分終了時までのジュール熱による温度上昇特性は毎回同一である。したがって、特定の積分時間中における画素１のジュール熱による温度上昇特性を積分して平均をとった温度上昇と同等となるように、参照画素２の熱抵抗を設計することで、特定の積分時間におけるダイオードの自己加熱によるノイズを減らした赤外線画像を得ることができる。 In addition to the structural change of the reference pixel 2 described above, by adjusting the thermal resistance and integration time of the reference pixel 2, an infrared image in which noise due to self-heating of the diode is further reduced can be obtained. Since the pixel 1 and the reference pixel 2 are driven with a constant current, the Joule heat due to the consumption current is constant. The pixel 1 has a heat insulating structure and gradually rises in temperature due to Joule heat, but the temperature rise characteristics due to Joule heat until the end of driving, that is, the end of integration are the same each time. Therefore, by designing the thermal resistance of the reference pixel 2 so as to be equivalent to the temperature rise obtained by integrating the temperature rise characteristics due to the Joule heat of the pixel 1 during the specific integration time, a specific integration time is obtained. Infrared images can be obtained with reduced noise due to self-heating of diodes.

尚、バイアス電圧回路３０はＰＭＯＳトランジスタを使用したものを示したが、実施の形態１で示した他のバイアス電圧回路も適用できる。また、参照画素２の構造を放熱用の金属層を設ける場合で説明したが、参照画素の断熱構造を無くすことでも、画素１に比べて多く発生する自己加熱による熱を逃がすことができるので、自己加熱によるノイズを減らすことができる。 Although the bias voltage circuit 30 uses a PMOS transistor, the other bias voltage circuit shown in the first embodiment can be applied. In addition, the structure of the reference pixel 2 has been described in the case where a metal layer for heat dissipation is provided. However, even if the heat insulating structure of the reference pixel is eliminated, heat generated by self-heating that is generated more than the pixel 1 can be released. Noise due to self-heating can be reduced.

尚、実施の形態１及び２では、差動増幅回路は、１段階の差動積分回路で説明したが、従来の差動増幅器１段と水平駆動回路内の積分回路にした場合であっても構わない。どちらの場合でも従来の２段階の差動増幅構成と異なり１段階の差動増幅構成にできるので、フリッカノイズの重畳を減らすことができ、高感度の赤外線検出画像が得られる。また、バイアス電圧を画素駆動電源１０から生成する場合で説明したが、画素駆動電源１０の電圧以上の電圧を発生する他の電源であっても、同様の効果が得られる。 In the first and second embodiments, the differential amplifier circuit has been described as a single-stage differential integration circuit. However, even when the conventional differential amplifier is one stage and the integration circuit in the horizontal drive circuit is used. I do not care. In either case, unlike the conventional two-stage differential amplification configuration, a one-stage differential amplification configuration can be achieved, so flicker noise superposition can be reduced and a highly sensitive infrared detection image can be obtained. Further, although the case where the bias voltage is generated from the pixel drive power supply 10 has been described, the same effect can be obtained even with another power supply that generates a voltage higher than the voltage of the pixel drive power supply 10.

この発明の実施の形態１における熱型赤外線検出回路の回路図である。It is a circuit diagram of the thermal type infrared detection circuit in Embodiment 1 of this invention. この発明の実施の形態１の動作を説明する図である。It is a figure explaining operation | movement of Embodiment 1 of this invention. この発明の差動積分回路の回路図である。It is a circuit diagram of the differential integration circuit of this invention. この発明の差動電圧電流変換アンプの回路図である。It is a circuit diagram of the differential voltage-current conversion amplifier of this invention. この発明で用いるバイアス電圧回路の他の一例を示す回路図である。It is a circuit diagram which shows another example of the bias voltage circuit used by this invention. この発明の実施の形態２における熱型赤外線検出回路の回路図である。It is a circuit diagram of the thermal type infrared detection circuit in Embodiment 2 of this invention. この発明の実施の形態２の動作を説明する図である。It is a figure explaining operation | movement of Embodiment 2 of this invention. 従来の赤外線固体撮像回路の画素構造を示す断面図及び斜視図である。It is sectional drawing and perspective view which show the pixel structure of the conventional infrared solid-state imaging circuit. 従来の熱型赤外線検出回路の回路図である。It is a circuit diagram of the conventional thermal type infrared detection circuit.

Explanation of symbols

１画素、２参照画素、３駆動線、４信号線、５参照信号線、８垂直走査回路、１０画素駆動電源、１１バイアス線、１４差動積分回路、１５水平駆動回路、１６差動増幅器、１７駆動トランジスタ、３０バイアス電圧回路、３０Ａバイアス電圧回路の入力端子、３０Ｂバイアス電圧回路の出力端子。 1 pixel, 2 reference pixels, 3 drive lines, 4 signal lines, 5 reference signal lines, 8 vertical scanning circuit, 10 pixel drive power supply, 11 bias line, 14 differential integration circuit, 15 horizontal drive circuit, 16 differential amplifier, 17 driving transistor, 30 bias voltage circuit, input terminal of 30A bias voltage circuit, output terminal of 30B bias voltage circuit.

Claims

Pixels that are arranged in a matrix in the pixel area and that are composed of thermal infrared sensors that are sensitive to infrared and temperature;
A reference pixel arranged in the column direction and sensitive to temperature but not sensitive to infrared;
A plurality of drive lines connecting each pixel of each row and the anode of the reference pixel;
A plurality of signal lines connected to the cathode of each pixel in each column;
A reference signal line connecting the cathode of each reference pixel;
A vertical scanning circuit that sequentially selects the driving lines and connects a pixel driving power source to the selected driving lines;
A bias line disposed in parallel to the drive line and having substantially the same resistance as the drive line and supplied with substantially the same current;
A horizontal drive circuit that sequentially selects the signal lines and outputs a voltage of the selected signal line via a differential amplifier circuit;
A bias voltage circuit that receives the voltage of the reference signal line, generates a voltage equal to the input voltage, and applies the voltage to the bias line;
The thermal infrared detection circuit, wherein the differential amplifier circuit amplifies a difference between a voltage of the bias line and a voltage of the signal line.

The bias voltage circuit has a first input terminal connected to the input terminal of the bias voltage circuit and a second input terminal connected to the output terminal of the bias voltage circuit, and an output of the differential amplifier. 2. The thermal infrared detection circuit according to claim 1, further comprising a feedback loop extending from the terminal to the second input terminal through a transistor connecting a power source to a bias line.

The first input terminal of the differential amplifier is an inverting terminal;
A second input terminal of the differential amplifier is a non-inverting terminal;
The feedback loop is configured by a PMOS transistor having an output of the differential amplifier connected to a gate electrode, and an output of a drain electrode of the PMOS transistor being connected to the non-inverting terminal. The thermal infrared detection circuit according to 1.

The first input terminal of the differential amplifier is an inverting terminal;
A second input terminal of the differential amplifier is a non-inverting terminal;
The feedback loop is configured by a PNP bipolar transistor having an output of the differential amplifier connected to a base electrode, and an output of a collector electrode of the PNP bipolar transistor connected to the non-inverting terminal. Item 3. The thermal infrared detection circuit according to Item 2.

2. The thermal type according to claim 1, wherein the pixel has a heat insulating structure and an infrared absorption structure, and the reference pixel has substantially the same structure as the pixel except that the pixel does not have the infrared absorption structure. Infrared detection circuit.

Pixels that are arranged in a matrix in the pixel area and that are composed of thermal infrared sensors that are sensitive to infrared and temperature;
A reference pixel that is sensitive to temperature but not sensitive to infrared;
A plurality of drive lines connecting the anodes of each pixel in each row;
A plurality of signal lines connected to the cathode of each pixel in each column;
A vertical scanning circuit that sequentially selects the driving lines and connects a pixel driving power source to the selected driving lines;
A bias line disposed in parallel to the drive line and having substantially the same resistance as the drive line and supplied with substantially the same current;
A horizontal drive circuit that sequentially selects the signal lines and outputs a voltage of the selected signal line via a differential amplifier circuit;
A bias voltage circuit that receives a voltage from the cathode of the reference pixel, generates a voltage equal to the input voltage, and applies the voltage to the bias line;
The thermal infrared detection circuit, wherein the differential amplifier circuit amplifies a difference between a voltage of the bias line and a voltage of the signal line.