JP2007285764A - Semiconductor device and its self-test failure detection method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To perform a quality decision test of ADC (analog-to-digital converter) without complicating the control system by dispensing with an additional external circuit. <P>SOLUTION: The semiconductor device 10 comprises the ADC 1, the determination circuit 2; the channel selection circuit 3, the test signal generator circuit 4, switches SW1 to SWn, switches SWn+1 to SWn+m, input terminals Pin1 to Pinn; and the output terminal Pout. When the ADC 1 is inputted with any of input signal among the input signals S<SB>IN1</SB>to S<SB>INn</SB>of analogue signal outputted from the sensor through the input terminal Pin1 to Pinn usually works, any of switch SWn+1 to SWn+m makes "ON", when any of the input signals S<SB>INn+1</SB>to S<SB>INn+m</SB>which is the signal of the digital side electric source voltage DVcc potentiometric split input signal S<SB>INn+1</SB>to S<SB>INn+m</SB>the quality determination test for the DUT (device under test) is performed. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an analog / digital converter.

  Analog-to-digital conversion generally converts an analog data signal expressed in voltage into a digital format, and expressing it as a digital value corresponding to a specific analog input is called “quantization”. The analog-to-digital converter (hereinafter referred to as ADC (Analog-to-Digital Converter)) includes a Nyquist sampling circuit type successive approximation type, integral type, parallel comparison type, pipeline type, or folding type, There are ΔΣ, ΔM, MASH (cascade), or higher-order ΔΣ of the oversampling circuit system. ADC is widely used in the field of measuring instruments, the field of communication such as CODEC, the field of audio such as DVD, the field of radio such as ISDN, the field of video, the high-speed communication field, or the automotive field such as airbags, power steering and engine control. Yes.

  In an ADC mounted on a semiconductor device such as a microcomputer, a processor, or a SoC (System on a chip), not only a quality determination test at a shipping stage by a semiconductor tester but also a quality determination test after shipment is very important. If the ADC enters an abnormal operation state due to some external factor or wear mode after shipment, the semiconductor device cannot operate normally, and it is difficult to determine whether the ADC is the cause of the failure. For this reason, various circuits (including an ADC BIST (Built in Self Test) circuit) and a test method have been proposed for the ADC pass / fail judgment test (see, for example, Patent Document 1).

However, in the ADC test circuit and test method described in Patent Document 1 and the like, a selection means such as a selector or a test signal is generated for selecting an operation state used in an application and an operation state for ADC check. For example, it is necessary to provide test signal generation means such as a semiconductor tester. For this reason, it is necessary to add an external circuit, and there is a problem that the control system becomes complicated. In addition, the selection means such as a selector has a problem in that it slows down the ADC conversion speed in order to slow down the transmission of the analog input signal. In addition, there is a problem that the number of analog input terminals installed outside the semiconductor required for the application is reduced.
Japanese Patent Laying-Open No. 2001-345699 (page 9, FIG. 11)

  The present invention provides a semiconductor device and a self-test failure detection method thereof that can perform a pass / fail judgment test of an ADC without adding an external circuit and without complicating a control system.

  In order to achieve the above object, a semiconductor device of one embodiment of the present invention is connected to a first high-potential-side power supply and a first low-potential-side power supply, and the first high-potential-side power supply voltage or the first A test signal generation circuit that outputs a voltage obtained by stepping down the high-potential-side power supply voltage as a test voltage signal, first channel selection means for inputting an analog signal through a terminal, and selecting and outputting the signal, and the test voltage signal being input The same as the first high-potential-side power supply, the second channel selection means for selective output, the channel selection circuit for outputting the channel selection signal for performing the selective output control of the first and second channel selection means, Alternatively, the high-level reference voltage and the low-level reference voltage are connected to the second high-potential-side power source and the second low-potential-side power source having a voltage higher than that, and the selected output from the first channel selection means The analog signal to be selected and the test voltage signal selected and output from the second channel selection means are input, and the test voltage signal selected based on the channel selection signal is input to perform AD during a pass / fail judgment test. An analog / digital converter that outputs a conversion signal; and a determination circuit that inputs the AD conversion signal and determines whether an AD conversion value of the AD conversion signal is within a predetermined range. To do.

  In order to achieve the above object, a self-test failure detection method for a semiconductor device according to one embodiment of the present invention is connected to a first high-potential side power source and a first low-potential side power source, and A test signal generation circuit that outputs a potential-side power supply voltage or a voltage obtained by stepping down the first high-potential-side power supply voltage as a test voltage signal, and an analog signal and a channel selection signal that performs selective output control of the test voltage signal are output. A high-level reference voltage and a low-level reference voltage connected to a channel selection circuit and a second high-potential side power source and a second low-potential side power source having the same or higher voltage as the first high-potential side power source An analog / digital converter that inputs the analog signal to be selected and output and the test voltage signal and outputs an AD conversion signal; and a determination circuit that inputs the AD conversion signal; A method for detecting a failure in a self-test of a semiconductor device, wherein the test voltage signal is input to the analog-to-digital converter based on the channel selection signal when the analog-to-digital converter is in a pass / fail test. And a step of inputting an AD conversion signal output from the analog / digital converter to a determination circuit and determining whether an AD conversion value of the AD conversion signal is within a predetermined range. It is characterized by that.

  According to the present invention, it is possible to provide a semiconductor device and a self-test failure detection method thereof that do not require the addition of an external circuit and can perform an ADC quality determination test without complicating the control system.

  Embodiments of the present invention will be described below with reference to the drawings.

  First, a semiconductor device and its self-test failure detection method according to Embodiment 1 of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram illustrating a semiconductor device. In this embodiment, the presence / absence of a failure of one ADC (Analog-to-Digital Converter) is detected.

  As shown in FIG. 1, the semiconductor device 10 includes an ADC 1, a determination circuit 2, a channel selection circuit 3, a test signal generation circuit 4, a switch SW1, a switch SW2,... Switch SWn, a switch SWn + 1,. , Input terminal Pin1, input terminal Pin2,..., Input terminal Pinn, and output terminal Pout. Here, the semiconductor device 10 is a microcomputer, and the ADC 1 is a Nyquist sampling circuit type successive approximation ADC.

An analog signal output from a sensor (not shown) is input to each of the n input terminals Pin1, Pin2,. The input signal _{S IN1} is an analog signal to the input terminal Pin1, the input signal _{S IN2} is an analog signal to an input terminal Pin2, the input signal _{S INn} is an analog signal is inputted to the input terminal Pinn.

Channel selection circuit 3, the switch SW1, the switch SW2, ... switch SWn, switch SWn + 1, generating a channel selection signal _{S SEL} to "ON" one of ... the switch SWn + m.

Switch SW1 is provided between the input terminal Pin1 and ADC1, a SPST (Single Pole Single Throw) switch as the channel selection means of the input signal _{S IN1,} the channel selection signal _{S SEL} outputted from the channel selection circuit 3 Based on this, the input signal _SIN1 is selectively output.

Switch SW2 is provided between the input terminal Pin2 and ADC1, the input signal is an SPST switch as channel selection means _{S IN2,} the input signal based on the channel selection signal _{S SEL} outputted from the channel selection circuit 3 _{S IN2} Is selected and output.

Switch SWn is provided between the input terminal Pinn and ADC1, a SPST switch as channel selection means of the input signal _{S INn,} the input signal based on the channel selection signal _{S SEL} outputted from the channel selection circuit 3 _{S INn} Is selected and output.

  The ADC 1 is connected to an analog high potential side power source AVcc and an analog low potential side power source AVss as a ground potential, and is further connected to a high level reference voltage VrefH and a low level reference voltage VrefL that determine the dynamic range of the AD conversion input.

The test signal generating circuit 4 is connected to the digital high potential power source DVcc and the digital low potential power source DVss as the ground potential, and has, for example, a resistance dividing circuit, and between the digital high potential side power source and the digital low potential side power source DVss. Are divided into resistors (including DVcc values), and are output as m types of input signals S _{INn + 1} ... Input signal S _{INn + m} .

  Here, the digital high potential side power supply DVcc, the digital low potential side power supply DVss, the analog high potential side power supply AVcc, the analog low potential side power supply AVss, the high level reference voltage VrefH, and the low level reference voltage VrefL are independent power systems. It is. The digital high-potential-side power supply DVcc and the digital low-potential-side power supply DVss are power supplies that are supplied to a digital circuit provided in the semiconductor device 10, such as a logic circuit or a CPU (Central Processing Unit).

Input signals S _{INn + 1} (test voltage signal),... input signal S _{INn + m} (test voltage signal) output from the test signal generation circuit 4 are input to the m switches SWn + _1,. .

Switch SWn + 1 is provided between the test signal generation circuit 4 and ADC1, the input signal is an SPST switch as channel selection means _{S INn + 1,} the input based on the channel selection signal _{S SEL} outputted from the channel selection circuit 3 signal Select and output _{SINn + 1} .

The switch SWn + m is provided between the test signal generation circuit 4 and the _{ADC 1} and is an SPST switch as a channel selection unit for the input signal S _{INn + m.} The switch SWn + m is an input signal based on the channel selection signal S _SEL output from the channel selection circuit 3. Select and output _{SINn + m} .

The ADC 1 is provided between the switch SW1, the switch SW2,..., The switch SWn, the switch SWn + 1,. Based on the channel selection signal _SSEL of the channel selection circuit 3, one of the switch SW1, the switch SW2,..., The switch SWn, the switch SWn + 1, the switch SWn + m is “ON”, the input signal S _IN1 , the input signal _{Any one of} S _IN2 ,..., Input signal S _INn , input signal S _{INn + 1} ... Input signal S _{INn + m} is selected and input as input signal S _IN , and AD converted AD conversion signal Sdc is output.

The ADC 1 normally operates when an input signal S _IN1 , an input signal S _IN2 ,..., An input signal S _INn is input via the input terminal Pin 1, the input terminal Pin _{2 ,.} When any one of SWn + 1,..., Switch SWn + m is “ON” and any one of the input signals S _{INn + 1} ..., Input signal S _{INn + m} is input, a _{pass / fail} judgment test is performed as a DUT (Device under Test).

  Here, the analog high potential side power source AVcc and the analog low potential side power source AVss are power sources supplied to, for example, an analog input / output circuit or an analog circuit including the ADC 1 provided in the semiconductor device 10.

When the voltage level of the input signal S _{INn + 1} is Vts1, the voltage level of the input signal S _{INn + 2} is Vts2, and similarly the voltage level of the input signal S _{INn + m} is Vtsm.
AVcc, VrefH ≧ DVcc ≧ Vts1>Vts2>Vts3>...>Vtsm> AVss, VrefL, DVss (1)
It is represented by

  For example, the analog high potential side power supply voltage AVcc, the high level reference voltage VrefH, the digital high potential side power supply DVcc are set to 5 V, the analog low potential side power supply AVss, the digital low potential side power supply DVss, and the low level reference voltage VrefL are set to the ground potential. ing. The digital high potential side power supply DVcc may be set to 3.3V.

  The determination circuit 2 is provided between the ADC 1 and the output terminal Pout, and outputs an AD conversion signal Sdc to an internal circuit (not shown) of the semiconductor device 10 during normal operation, for example. The determination circuit 2 includes, for example, a register that stores each AD conversion signal Sdc and a comparison circuit that compares a predetermined conversion standard value. The ADC 1 performs a pass / fail determination test within a range of the predetermined conversion standard value. The result of comparison is output to the output terminal.

  Here, the configuration of the determination circuit 2 is, for example, a circuit including a CPU and a program (not shown) provided in the semiconductor device 10, and the comparison is performed by the CPU and the program instead of the comparison circuit configured by hardware. The AD conversion value of Sdc may be determined and output to the output terminal Pout.

The output terminal Pout outputs the determination result signal performed by the determination circuit 2 to the outside. That is, a result indicating whether each determination signal with respect to the AD conversion signal of each S _INj (j = n + 1 to n + m) is a good determination or at least one abnormality determination is output. The semiconductor device 10 or a system including the semiconductor device 10 can perform an operation corresponding to the abnormal operation of the system based on the determination signal.

  Next, the ADC itself is in an abnormal state due to some external factor or wear mode after shipment, or the power supply voltage (AVcc, AVss) and the reference voltage (VrefH, VrefL) to the ADC are not a predetermined value but an abnormal state About the fault detection of the ADC that performs confirmation without using a semiconductor tester or the like whether or not the off-leakage current of the switch SW1, the switch SW2,..., The switch SWn is not a predetermined value but an abnormal state. This will be described with reference to FIG. FIG. 2 is a flowchart showing a self-test failure detection method for a semiconductor device.

  In this flow, every time a RESET signal (not shown) for resetting the operation state of the semiconductor device 10 is released, a pass / fail judgment test of the ADC 1 is performed. The RESET signal may be input from the outside of the semiconductor device 10 or may be a signal from a power-on reset circuit built in the semiconductor device 10.

  As shown in FIG. 2, first, a RESET signal (not shown) to the semiconductor device 10 is released, and the semiconductor device 10 starts operating with the RESET state as an initial state. That is, the CPU in the semiconductor device 10 activates a program for the pass / fail judgment test of the ADC 1 (step S1).

Next, a channel selection signal _SSEL for selecting a signal output from the test signal generation circuit 4 based on a program is generated. For example, the channel of the input signal S _{INn + 1} is selected and input to the _{ADC 1} as the input signal S _IN (step S2). Subsequently, the input signal S _{INn + 1 that} is an analog signal (voltage level Vts1) is quantized by the _{ADC 1} and output to the determination circuit 2 as an AD conversion signal Sdc _{n + 1} (step S3).

Then, it is determined whether the AD conversion signal Sdc _{n + 1} is within a predetermined conversion standard value range by the determination circuit 2 (step S4). If the AD conversion value Sdc _{n + 1} is within a predetermined range, the ADC ₁ is determined to be operating normally with respect to the AD conversion. If it is out of range, it is determined as an abnormal operation. Here, the determination circuit 2 may be a circuit that is determined by CPU software support. Alternatively, hardware for performing size comparison or the like may be incorporated in the determination circuit 2 and determination may be made using the result.

Next, when it is determined that the operation is normal, it is determined whether or not all the channels from the test signal generation circuit 4 have been selected (step S5). If there is an unselected channel, the next channel, for example, the next input signal S _{INn + 2} is selected and input to the _{ADC 1} as the input signal S _IN , and the determination process from step S2 to step S5 is repeated. This process is repeated until all the channels from the test signal generation circuit 4 are selected as long as it is determined as normal operation. When conversion of all channels is determined to be normal operation, the ADC 1 is determined to be normal operation (step S6).

  If at least one AD conversion value is outside the predetermined range in step S4, which is an AD conversion value determination step, the ADC 1 is determined to be in an abnormal operation (step S7). The determination circuit 2 outputs a determination result of normal operation or abnormal operation.

  If it is determined that the operation is normal, the program for the pass / fail determination test of the ADC 1 is terminated, and the next program to be operated is executed. If it is determined that the operation is abnormal, a processing program prepared in advance (for example, resetting the system to stop the operation) is executed (step S8).

  Here, the predetermined conversion standard value may be stored in a program executed by the CPU, for example. Alternatively, it may be read and set from the outside of the semiconductor device 10. Alternatively, it may be pre-made by hardware.

  Here, the end of the selection of all channels (step S5) is confirmed after the end of the AD conversion value determination (step S4). However, the determination of the AD conversion value (step S4) and the selection of the next channel (step S4) are performed. Step S2) and AD conversion (step S3) may be partially performed in parallel. Alternatively, the AD conversion value may be determined after all the channels from the test signal generation circuit 4 are selected and the conversion is completed. The channel selection, AD conversion, and AD conversion value determination are controlled using the CPU and program, but may be controlled by a sequential circuit.

  In the flowchart of FIG. 2, the program for starting the pass / fail judgment test of the ADC 1 is started every time the RESET signal (not shown) to the semiconductor device 10 is released. However, the present invention is not limited to this. is not. Even when the semiconductor device 10 is in operation, the flow from step S2 to step S7 can be incorporated into the program, and the program for the pass / fail judgment test can be started at an arbitrary timing or at an arbitrary interval. .

As described above, in the semiconductor device of this embodiment, the ADC 1, the determination circuit 2, the channel selection circuit 3, the test signal generation circuit 4, the switches SW1 to SWn, the switches SWn + 1 to SWn + m, the input terminals Pin1 to Pinn, and the output terminal Pout are provided. Is provided. Channel selection circuit 3 generates a channel selection signal _{S SEL} to "ON" to one of the switches SW1 to SWn, switch SWn + 1 to SWn + m. The _ADC 1 normally operates when any of the input signals S _{IN1 to} S _INn that are analog signals output from the sensor is input via the input terminals Pin1 to Pinn, and any of the switches SWn + 1 to SWn + m is “ON”. Then, when any one of the input signals S _{INn + 1 to} S _{INn + m} , which is a signal obtained by resistance-dividing the digital high-potential-side power supply DVcc, is input, a _{pass / fail} judgment test is performed as a DUT. The determination circuit 2 receives the AD conversion signal Sdc output from the ADC 1, outputs the AD conversion signal Sdc to an internal circuit (not shown) of the semiconductor device 10, for example, during normal operation, and outputs the AD conversion signal Sdc during a pass / fail determination test of the ADC 1. The AD conversion value is determined and a determination signal is output to the output terminal.

  For this reason, it is not necessary to add an external circuit and the ADC itself, the power supply voltage (AVcc, AVss) and the reference voltage (VrefH, VrefL) to the ADC or the switch SW1, the switch SW2 without complicating the control system. ... It can be judged whether the off-leakage current of the switch SWn is good or bad. Further, since the circuit configuration can be simplified as compared with the ADC BIST circuit, an increase in chip area can be suppressed. Furthermore, it is possible to suppress a decrease in the number of analog input external terminals required in the application.

  In this embodiment, a successive approximation ADC is used as the ADC 1, but an Nyquist sampling circuit type ADC such as a parallel comparison type or a series parallel type or an oversampling type ADC such as ΔΣ or higher-order ΔΣ is used. It may be used. Further, instead of the SPST switch, a transfer gate composed of an Nch MOS transistor, a Pch MOS transistor, or an Nch MOS transistor / Pch MOS transistor may be used as the channel selection means for the input signal.

  Next, a semiconductor device according to Embodiment 2 of the present invention will be described with reference to the drawings. FIG. 3 is a block diagram illustrating the semiconductor device. In this embodiment, the presence or absence of a failure of one ADC is detected without using a test signal generation circuit.

  In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

  As shown in FIG. 3, the semiconductor device 10a includes an ADC 1, a determination circuit 2, a channel selection circuit 3a, a switch SW1, a switch SW2,... Switch SWn, a switch SWn + 1, an input terminal Pin1, an input terminal Pin2,. An input terminal Pinn and an output terminal Pout are provided.

Channel selection circuit 3a, the switch SW1, the switch SW2, · · · switch SWn, generates a channel selection signal _{S SEL} to "ON" to any one of the switches SWn + 1.

The switch SWn + 1 receives the digital high potential side power supply DVcc voltage as the input signal _{SINn + 1} . Switch SWn + 1 is the SPST switch as channel selection means of the input signal _{S INn + 1,} selects and outputs the input signal _{S INn + 1} based on the channel selection signal _{S SEL} outputted from the channel selection circuit 3.

The ADC 1 is provided between the switch SW1, the switch SW2,..., The switch SWn, the switch SWn + 1, and the determination circuit 2. The ADC 1 is an analog high potential power source AVcc, an analog low potential power source AVss as a ground potential, and a high level reference voltage. VrefH and a low level reference voltage VrefL are supplied. Based on the channel selection signal _{S SEL} channel selection circuit 3a, the switch SW1, the switch SW2, · · · switch SWn, one of the switches SWn + 1 is "ON", the input signal _{S IN1,} the input signal _S IN2, · · · _Either the input signal S _INn or the input signal S _{INn + 1} is selected and input as the input signal S _IN , and an AD converted AD signal Sdc is output.

The ADC 1 normally operates when an input signal S _IN1 , an input signal S _IN2 ,..., An input signal S _INn is input via the input terminal Pin 1, the input terminal Pin _{2 ,.} When SWn + 1 is “ON” and the input signal _{SINn + 1} is input, a _{pass / fail} judgment test is performed as a DUT.

  Here, the analog high potential side power source AVcc and the analog low potential side power source AVss are power sources supplied to, for example, an analog input / output circuit or an analog circuit including the ADC 1 provided in the semiconductor device 10.

Since the voltage level of the input signal S _{INn + 1} is DVcc,
AVcc, VrefH>DVcc> AVss, VrefL, DVss ... Equation (2)
It is represented by

  For this reason, as in the case of the first embodiment, the digital high potential power source DVcc can be used as an intermediate potential between the high level reference voltage VrefH and the low level reference voltage VrefL without using the test signal generation circuit. . For example, the analog high potential power supply voltage AVcc and the high level reference voltage VrefH are 5 V, the analog low potential power supply AVss, the digital low potential power supply DVss and the low level reference voltage VrefL are the ground potential, and the digital high potential power supply DVcc is 3. It is set to 3V.

As described above, in the semiconductor device of this embodiment, the ADC 1, the determination circuit 2, the channel selection circuit 3a, the switches SW1 to SWn, the switch SWn + 1, the input terminals Pin1 to Pinn, and the output terminal Pout are provided. Channel selection circuit 3a generates a channel selection signal _{S SEL} to the switch SW1 to SWn, one of the switches SWn + 1 "ON". The _ADC 1 normally operates when any of the input signals S _{IN1 to} S _INn that are analog signals output from the sensor is input via the input terminals Pin1 to Pinn, the switch SWn + 1 is turned “ON”, and the digital high When the input signal _{SINn + 1,} which is the potential side power supply DVcc voltage, is input, a _{pass / fail} judgment test is performed as a DUT. The determination circuit 2 receives the AD conversion signal Sdc output from the ADC 1, outputs the AD conversion signal Sdc to an internal circuit (not shown) of the semiconductor device 10 a during normal operation, for example, and outputs the AD conversion signal Sdc during a pass / fail determination test of the ADC 1. The AD conversion value is determined and a determination signal is output to the output terminal.

  For this reason, the addition of an external circuit and a test signal generation circuit are unnecessary, and the quality of the ADC can be determined more simply than in the first embodiment without complicating the control system. Further, since the circuit configuration can be simplified as compared with the ADC BIST circuit, an increase in chip area can be suppressed. Furthermore, it is possible to suppress a decrease in the number of analog input external terminals required in the application.

  Next, a semiconductor device according to Embodiment 3 of the present invention will be described with reference to the drawings. FIG. 4 is a block diagram illustrating the semiconductor device. In this embodiment, the presence / absence of failure of two ADCs is detected.

  In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

  4, the semiconductor device 10b includes ADC 1a, ADC 1b, determination circuit 2a, channel selection circuit 3b, test signal generation circuit 4, switch SW11, switch SW12,... Switch SW1n, switch SW1n + 1,. Switch SW1n + m, switch SW21, switch SW22, ... switch SW2k, switch SW2n + 1, ... switch SW2n + m, input terminal Pin11, input terminal Pin12, ... input terminal Pin1n, input terminal Pin21, input terminal Pin22, ... An input terminal Pin2k and an output terminal Pout are provided. Here, the semiconductor device 10b is a microcomputer, and the ADCs 1a and 1b are Nyquist sampling circuit type successive approximation ADCs.

  An analog signal output from a sensor (not shown) is input to each of the n input terminals Pin11, the input terminal Pin12,..., the input terminal Pin1n, and the k input terminals Pin21, the input terminal Pin22,. Is done.

Input signal _{S IN11} is an analog signal to the input terminal Pin11 is, the input signal _{S IN12} is an analog signal to the input terminal PIN12, the input signal _{S IN1n} an analog signal to the input terminal Pin1n is, the input terminal Pin21 is input signal _{S IN21} is an analog signal, the input signal _{S IN22} is an analog signal to the input terminal Pin22, to the input terminal Pin2k input signal _{S IN2k} an analog signal is input, respectively.

The channel selection circuit 3b is one of a switch SW11, a switch SW12,..., A switch SW1n, a switch SW1n + 1,..., A switch SW1n + m, a switch SW21, a switch SW22, a switch SW2k, a switch SW2n + 1,. A channel selection signal S _SEL for turning ON is generated.

Switch SW11 is provided between the input terminal Pin11 and ADC1a, the input signal is an SPST switch as channel selection means _{S IN11,} the input signal based on the channel selection signal _{S SEL} outputted from the channel selection circuit 3b _{S IN11} Is selected and output.

Switch SW12 is provided between the input terminal Pin12 and ADC1a, the input signal is an SPST switch as channel selection means _{S IN12,} the input signal based on the channel selection signal _{S SEL} outputted from the channel selection circuit 3b _{S IN12} Is selected and output.

Switch SW1n is provided between the input terminal Pin1n and ADC1a, the input signal is an SPST switch as channel selection means _{S IN1n,} the input signal based on the channel selection signal _{S SEL} outputted from the channel selection circuit 3b _{S IN1n} Is selected and output.

Switch SW21 is provided between the input terminal Pin21 and ADC1b, the input signal is an SPST switch as channel selection means _{S IN21,} the input signal based on the channel selection signal _{S SEL} outputted from the channel selection circuit 3b _{S IN21} Is selected and output.

Switch SW22 is provided between the input terminal Pin22 and ADC1b, the input signal is an SPST switch as channel selection means _{S IN22,} the input signal based on the channel selection signal _{S SEL} outputted from the channel selection circuit 3b _{S IN22} Is selected and output.

Switch SW2k is provided between the input terminal Pin2n and ADC1b, the input signal is an SPST switch as channel selection means _{S IN2k,} the input signal based on the channel selection signal _{S SEL} outputted from the channel selection circuit 3b _{S IN2k} Is selected and output.

The test signal generation circuit 4 is the same as the circuit of the first embodiment, and is connected to the digital high potential side power supply DVcc and the digital low potential side power supply DVss as the ground potential. Signals (including DVcc values) obtained by resistance division between DVcc and digital low-potential power supply DVss are output as m types of input signals S _{INn + 1} ... Input signal S _{INn + m} .

An input signal S _{INn + 1} ... input signal S _{INn + m} output from the test signal generation circuit 4 is input to each of the m switches SW1n + 1,..., switch SW1n + m.

Switch SW1n + 1 is provided between the test signal generation circuit 4 and ADC1a, the input signal is an SPST switch as channel selection means _{S INn + 1,} the input based on the channel selection signal _{S SEL} outputted from the channel selection circuit 3b signal Select and output _{SINn + 1} .

Switch SW1n + m is provided between the test signal generation circuit 4 and ADC1a, the input signal is an SPST switch as channel selection means _{S INn + m,} the input based on the channel selection signal _{S SEL} outputted from the channel selection circuit 3b signal Select and output _{SINn + m} .

The ADC 1a is provided between the switch SW11, the switch SW12,..., The switch SW1n, the switch SW1n + 1,..., The switch SW1n + m, and the determination circuit 2a, and the analog high potential side power source AVcc1 and the analog low potential side as the ground potential The power supply AVss1, the high level reference voltage VrefH1, and the low level reference voltage VrefL1 are supplied. Based on the channel selection signal _{S SEL} channel selection circuit 3b, a switch SW11, switch SW12, ... switch SW1n, switch SW1n + 1, either ... switch SW1n + m is "ON", the input signal _{S IN11,} the input signal _{Any one of} S _IN12 ,..., Input signal S _IN1n , input signal S _{INn + 1,} ..., Input signal S _{INn + m} is selectively input as input signal S _INA , and AD converted AD conversion signal Sdc 1 is output.

The ADC 1a normally operates when the input signal S _IN11 , the input signal S _IN12 ,..., The input signal S _IN1n is input via the input terminal Pin11, the input terminal Pin12,. When any one of SW1n + 1,..., Switch SW1n + m is “ON” and any one of input signals S _{INn + 1} ... Input signal S _{INn + m} is input, a _{pass / fail} judgment test is performed as a DUT.

An input signal S _{INn + 1} ... input signal S _{INn + m} output from the test signal generation circuit 4 is input to each of the m switches SW2n + 1,..., switch SW2n + m.

Switch SW2n + 1 is provided between the test signal generation circuit 4 and ADC1b, the input signal is an SPST switch as channel selection means _{S INn + 1,} the input based on the channel selection signal _{S SEL} outputted from the channel selection circuit 3b signal Select and output _{SINn + 1} .

Switch SW2n + m is provided between the test signal generation circuit 4 and ADC1b, the input signal is an SPST switch as channel selection means _{S INn + m,} the input based on the channel selection signal _{S SEL} outputted from the channel selection circuit 3b signal Select and output _{SINn + m} .

The ADC 1b is provided between the switch SW21, the switch SW22,..., The switch SW2k, the switch SW2n + 1,..., The switch SW2n + m, and the determination circuit 2a, and the analog high potential side power source AVcc2 and the analog low potential side as the ground potential The power supply AVss2, the high level reference voltage VrefH2, and the low level reference voltage VrefL2 are supplied. Based on the channel selection signal _{S SEL} channel selection circuit 3b, a switch SW21, switch SW22, ... switch SW2k, switch SW2n + 1, either ... switch SW2n + m is "ON", the input signal _{S IN21,} the input signal _{Any one of} S _IN22 ,..., Input signal S _IN2k , input signal S _{INn + 1} ... Input signal S _{INn + m} is selected and input as input signal S _INB , and AD converted AD conversion signal Sdc 2 is output.

The ADC 1b normally operates when an input signal S _IN21 , an input signal S _IN22 ,..., An input signal S _IN2k is input via an input terminal Pin21, an input terminal Pin22,. When any of SW2n + 1,..., Switch SW2n + m is “ON” and any of input signal S _{INn + 1} ... Input signal S _{INn + m} is input, a _{pass / fail} judgment test is performed as a DUT.

  Here, the analog high potential side power source AVcc1, the analog high potential side power source AVcc2, the analog low potential side power source AVss1, and the analog low potential side power source AVss2 include the ADC 1a and ADC 1b provided in the semiconductor device 10, for example. It is a power source supplied to an analog input / output circuit or an analog circuit.

When the voltage level of the input signal S _{INn + 1} is Vts1, the voltage level of the input signal S _{INn + 2} is Vts2, and the voltage level of the input signal S _{INn + m} is Vtsm,
AVcc1, AVcc2, VrefH1, VrefH2 ≧ DVcc ≧ Vts1> Vts2 ...>Vts2m> AVss1, AVss2,,
VrefL1, VrefL2, DVss ............ Formula (3)
It is represented by

  For example, the analog high potential power supply voltages AVcc1 and AVcc2, the high level reference voltages VrefH1 and VrefH2, the digital high potential power supply DVcc are 5V, the analog low potential power supplies AVss1 and AVss2, the digital low potential power supply DVss, and the low level reference voltage VrefL1. , VrefL2 is set to the ground potential. The digital high potential side power supply DVcc may be set to 3.3V.

  The determination circuit 2a is provided between the ADCs 1a and 1b and the output terminal Pout, and outputs AD conversion signals Sdc1 and Sdc2 to an internal circuit (not shown) of the semiconductor device 10b, for example, during normal operation. Then, the determination circuit 2a compares, for example, a register that stores the AD conversion signals Sdc1 and Sdc2 in each ADC with respect to the same input voltage from the test signal generation circuit 4, and a difference between the two and a predetermined difference standard value. And a comparison circuit for performing a pass / fail judgment test of the ADC 1a and the ADC 1b, and outputting a comparison result as to whether or not it is within a predetermined difference standard value range to the output terminal Pout.

  Here, the configuration of the determination circuit 2a is, for example, a circuit including a CPU and a program (not shown) provided in the semiconductor device 10b, and a comparison is performed by the CPU and the program instead of the difference calculation circuit and the comparison circuit configured by hardware. The AD conversion values of the AD conversion signals Sdc1 and Sdc2 may be determined and output to the output terminal Pout.

The output terminal Pout outputs the determination result signal performed by the determination circuit 2a to the outside. That is, a result indicating whether each determination signal with respect to the AD conversion signal of each S _INj (j = n + 1 to n + m) is a good determination or at least one abnormality determination is output. The semiconductor device 10b or a system including the semiconductor device 10b can perform an operation corresponding to the abnormal operation of the system based on the determination signal.

  Next, regarding the detection of failure of two ADCs provided in the semiconductor device, the two ADCs themselves are in an abnormal state or some power supply voltage (AVcc1, AVcc2) due to some external factor or wear mode after shipment. , AVss1, AVss2) and the reference voltages (VrefH1, VrefH2, VrefL1, VrefL2) are not predetermined values but are in an abnormal state, or switch SW11, switch SW12,... Switch SW1n, switch SW21, switch SW22,. .. ADC failure detection such as confirmation of whether the off-leakage current of the switch SW2k is not a predetermined value but an abnormal state will be described with reference to FIG. FIG. 5 is a flowchart showing a self-test failure detection method for a semiconductor device.

  In this flow, every time a RESET signal (not shown) for releasing the operation state of the semiconductor device 10b is released, a pass / fail judgment test of the ADC 1 is performed. The RESET signal may be input from the outside of the semiconductor device 10b, or may be a signal from a power-on reset circuit built in the semiconductor device 10b.

  As shown in FIG. 5, first, a RESET signal (not shown) to the semiconductor device 10b is released, and the semiconductor device 10b starts operating with the RESET state as an initial state. That is, the CPU in the semiconductor device 10b starts a program for the pass / fail judgment test of the ADCs 1a and 1b (step S1).

Next, a channel selection signal _SSEL for selecting a signal output from the test signal generation circuit 4 based on a program is generated. Here, the channel selection signal _{S SEL} is generated so that the same voltage is selected as the input signal to ADC1a and ADC1b. For example, the input signal _{S INn + 1} the selected channel is input to ADC1a as the input signal _{S INA,} ADC1b any input signal _{S INn + 1} is the selected channel is input to ADC1b as the input signal _{S INB} (step S20).

Subsequently, the input signal that is the selected analog signal (voltage level Vts1), for example, _{SINn + 1,} is quantized by the ADC 1a, is output to the determination circuit 2a as the AD conversion signal Sdc1, and is also quantized by the ADC 1b. The converted signal Sdc2 is output to the determination circuit 2a (step S21).

Then, the AD conversion signals Sdc1 and Sdc2 are compared in AD conversion value by the determination circuit 2a. Specifically, it is determined whether or not the difference between the AD conversion value of ADC 1a and the AD conversion value of ADC 1b is within a predetermined range (step S22). If the ADC 1a and the ADC 1b are normal, it may be considered that the difference is about the characteristic difference between the ADCs. Therefore, if the difference between the AD conversion value of the ADC 1a and the AD conversion value of the ADC 1b is within a predetermined range, the ADC 1a and the ADC 1b are determined to be normal operations with respect to the AD conversion of the input signal S _{INn + 1} . If it is out of range, it is determined as an abnormal operation.

  Here, the determination circuit 2a may be a circuit that is determined by CPU software support. Alternatively, the determination circuit 2 may be incorporated with hardware that performs a size comparison with the difference calculation circuit and the determination may be performed using the result.

Next, when it is determined that the operation is normal, it is determined whether or not all the channels from the test signal generation circuit 4 have been selected (step S23). If there is an unselected channel, the next channel, for example, the next input signal S _{INn + 2} is selected, input to the ADC 1a as the input signal S _INA , and input to the ADC 1b as the input signal S _INB . The decision process is repeated. This process is repeated until all the channels from the test signal generation circuit 4 are selected as long as it is determined as normal operation. When conversion of all channels is determined to be normal operation, ADC 1a and ADC 1b are determined to be normal operation.

The determination circuit 2a outputs a determination result of normal operation or abnormal operation.

  If the normal operation is determined, the program for the pass / fail determination test of the ADC 1a and ADC 1b is terminated, and the next program to be operated is executed (step S24).

  When it is determined that the operation is abnormal (step S25), a processing program prepared in advance (for example, resetting the system to stop the operation) is executed (step S26).

  Here, the standard value of the predetermined difference may be stored in a program executed by the CPU, for example. Alternatively, it may be read and set from the outside of the semiconductor device 10b. Alternatively, it may be pre-made by hardware.

  In the flowchart of FIG. 5, the program for starting the pass / fail judgment test of the ADC 1a and ADC 1b is started every time the RESET signal (not shown) to the semiconductor device 10b is released. However, the present invention is not limited to this. It is not something. Even when the semiconductor device 10b is operating, the flow from step S20 to step S25 can be incorporated into the program, and the program for the pass / fail judgment test can be started at an arbitrary timing or at an arbitrary interval. .

As described above, in the semiconductor device of this embodiment, the ADC 1a, ADC 1b, determination circuit 2a, channel selection circuit 3b, test signal generation circuit 4, switches SW11 to SW1n, switches SW1n + 1 to SW1n + m, switches SW21 to SW2k, switches SW2n + 1 to SW2n + m, input terminals Pin11 to Pin1n, input terminals Pin21 to Pin2k, and an output terminal Pout are provided. Channel selection circuit 3b, the switch SW11 to SW1n, generates a switch SW1n + 1 to SW1n + m, the switch SW21 to SW2k, channel selection signal _{S SEL} to "ON" to any one of the switches SW2n + 1 to SW2n + m. ADC1a via the input terminal Pin11 to Pin1n, any of the input signal _{S IN11} to _{S IN1n} is an analog signal output from the sensor is operating normally when entered, either switch SW1n + 1 to SW1n + m is "ON Then, when any one of the input signals S _{INn + 1 to} S _{INn + m} , which is a signal obtained by resistance-dividing the digital high-potential-side power supply DVcc, is input, a _{pass / fail} judgment test is performed as a DUT. ADC1b via the input terminal Pin21 to Pin2k, any of the input signal _{S IN21} to _{S IN2k} is an analog signal output from the sensor is operating normally when entered, either switch SW2n + 1 to SW2n + m is "ON Then, when any one of the input signals S _{INn + 1 to} S _{INn + m} , which is a signal obtained by resistance-dividing the digital high-potential-side power supply DVcc, is input, a _{pass / fail} judgment test is performed as a DUT. The determination circuit 2a receives the AD conversion signal Sdc1 output from the ADC 1a and the AD conversion signal Sdc2 output from the ADC 1b, and outputs the AD conversion signals Sdc1 and Sdc2 to an internal circuit (not shown) of the semiconductor device 10b, for example, during normal operation. The AD conversion values of the AD conversion signals Sdc1 and Sdc2 are determined during the pass / fail determination test of the ADC 1a and ADC 1b, and a determination signal is output to the output terminal.

  For this reason, it is not necessary to add an external circuit, and it is possible to determine whether or not a plurality of ADCs are good without complicating the control system. Further, since the circuit configuration can be simplified as compared with the ADC BIST circuit, an increase in chip area can be suppressed. Furthermore, it is possible to suppress a decrease in the number of analog input terminals required in the application.

  In this embodiment, the presence or absence of two ADC faults is tested. However, the number of ADCs is not necessarily limited to two, and is applied to j (where j is an integer of 2 or more) ADCs. it can.

  Next, a self-test failure detection method for a semiconductor device according to Embodiment 4 of the present invention will be described with reference to the drawings. FIG. 6 is a flowchart showing a self-test failure detection method for a semiconductor device. In this embodiment, when an abnormality determination is made, a step different from that of the third embodiment is added and detected so that it can be determined which of the two ADCs of the semiconductor device is operating abnormally.

  In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

  As shown in FIG. 6, the steps up to step 21 are the same as those in the third embodiment, and the description thereof is omitted. The determination circuit 2a not only determines whether the difference between the AD conversion value of the ADC 1a and the AD conversion value of the ADC 1b is within a predetermined range, but also converts each AD conversion value Sdc1 and Sdc2 to a predetermined conversion. It is determined whether the value is within the standard value range.

  The AD conversion signal Sdc1 from the ADC 1a and the AD conversion signal Sdc2 from the ADC 1b are output to the determination circuit 2a, and the determination circuit 2a determines whether the AD conversion signal Sdc1 and the AD conversion signal Sdc2 are within a predetermined conversion standard value range. Performed (step 27). If the AD conversion value is within a predetermined range, the ADC 1a and ADC 1b are determined as normal operations with respect to the AD conversion, and if they are out of the range, they are determined as abnormal operations.

Next, when it is determined that the operation is normal, the AD conversion signals Sdc1 and Sdc2 are compared in AD conversion value by the determination circuit 2a. Specifically, it is determined whether or not the difference between the AD conversion value of ADC 1a and the AD conversion value of ADC 1b is within a predetermined range (step S22). If the ADC 1a and the ADC 1b are normal, it may be considered that the difference is about the characteristic difference between the ADCs. Therefore, if the difference between the AD conversion value of the ADC 1a and the AD conversion value of the ADC 1b is within a predetermined range, the ADC 1a and the ADC 1b are determined to be normal operations with respect to the AD conversion of the input signal S _{INn + 1} . If it is out of range, it is determined as an abnormal operation. Subsequent steps are the same as those in the third embodiment, and the description thereof is omitted.

  As described above, in the self-test failure detection method for a semiconductor device according to this embodiment, the difference between the AD conversion value of the ADC 1a and the AD conversion value of the ADC 1b, and whether the AD conversion values of the ADC 1a and ADC 1b are within a predetermined range are determined. Is done. Therefore, it is possible to determine whether the difference between the AD conversion value of the ADC 1a and the AD conversion value of the ADC 1b is within a predetermined range, and it is possible to determine which of the two ADCs of the semiconductor device is operating abnormally. .

  In this embodiment, the presence or absence of two ADC faults is tested. However, the number of ADCs is not necessarily limited to two, and is applied to j (where j is an integer of 2 or more) ADCs. it can.

  Next, a semiconductor device according to Embodiment 5 of the present invention will be described with reference to the drawings. FIG. 7 is a block diagram illustrating a semiconductor device. In this embodiment, the presence / absence of failure of two ADCs is detected without using the test signal generation circuit used in the third embodiment.

  Hereinafter, the same reference numerals are given to the same components as those in the third embodiment, and the description of the components is omitted, and only different portions will be described.

  As shown in FIG. 7, the semiconductor device 10c includes an ADC 1a, an ADC 1b, a determination circuit 2a, a channel selection circuit 3c, a switch SW11, a switch SW12,..., A switch SW1n, a switch SW1n + 1, a switch SW21, a switch SW22,. A switch SW2k, a switch SW2n + 1, an input terminal Pin11, an input terminal Pin12,..., An input terminal Pin1n, an input terminal Pin21, an input terminal Pin22,..., An input terminal Pin2k, and an output terminal Pout are provided.

Channel selection circuit 3c is generated switch SW11, switch SW12, · · · switch SW1n, switch SW1n + 1, switch SW21, switch SW22, · · · switch SW2k, a channel selection signal _{S SEL} to "ON" to any one of the switches SW2n + 1 To do.

The switch SW1n + 1 receives the digital high potential side power supply DVcc voltage as the input signal _{SINn + 1} . Switch SW1n + 1 is the SPST switch as channel selection means of the input signal _{S INn + 1,} the input signal _{S INn + 1} selectively outputs based on the channel selection signal _{S SEL} outputted from the channel selection circuit 3c.

The ADC 1a is provided between the switch SW11, the switch SW12,..., The switch SW1n, the switch SW1n + 1, and the determination circuit 2a. The ADC 1a is an analog high potential power source AVcc1, an analog low potential power source AVss1 as a ground potential, and a high level reference voltage. VrefH1 and a low level reference voltage VrefL1 are supplied. Based upon the channel selection signal _{S SEL} channel selection circuit 3c, a switch SW11, switch SW12, · · · switch SW1n, either switch SW1n + 1 is "ON", the input signal _{S IN11,} the input signal _{S IN12,} · · · _{Either the} input signal S _IN1n or the input signal S _{INn + 1} is selected and input as the input signal S _INA , and the AD converted AD signal Sdc1 is output.

The ADC 1a normally operates when the input signal S _IN11 , the input signal S _IN12 ,..., The input signal S _IN1n is input via the input terminal Pin11, the input terminal Pin12,. When SW1n + 1 is “ON” and the input signal _{SINn + 1} is input, a _{pass / fail} judgment test is performed as a DUT.

The switch SW2n + 1 receives the digital high potential side power supply DVcc voltage as the input signal _{SINn + 1} . Switch SW2n + 1 is the SPST switch as channel selection means of the input signal _{S INn + 1,} the input signal _{S INn + 1} selectively outputs based on the channel selection signal _{S SEL} outputted from the channel selection circuit 3c.

The ADC 1b is provided between the switch SW21, the switch SW22,..., The switch SW2k, the switch SW2n + 1, and the determination circuit 2a, and includes the analog high potential power source AVcc2, the analog low potential power source AVss2 as the ground potential, and the high level reference voltage. VrefH2 and a low level reference voltage VrefL2 are supplied. Based on channel selection signal _{S SEL} channel selection circuit 3c, a switch SW21, switch SW22, · · · switch SW2k, either switch SW2n + 1 is "ON", the input signal _{S IN21,} the input signal _{S IN22,} · · · _Either the input signal S _IN2n or the input signal S _{INn + 1} is selected and input as the input signal S _INB , and an AD converted AD conversion signal Sdc2 is output.

The ADC 1b normally operates when an input signal S _IN21 , an input signal S _IN22 ,..., An input signal S _IN2k is input via an input terminal Pin21, an input terminal Pin22,. When SW2n + 1 is "ON" and the input signal _{SINn + 1} is input, a _{pass / fail} judgment test is performed as a DUT.

The voltage level of the input signal S _{INn + 1} is Dvcc,
AVcc1, AVcc2, VrefH1, VrefH2>DVcc> AVss1, AVss2, VrefL1, VrefL2, DVss
・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Formula (3)
It is represented by

  For example, the analog high potential side power supply voltages AVcc1 and AVcc2 and the high level reference voltages VrefH1 and VrefH2 are 5V, the analog low potential side power sources AVss1 and AVss2, the digital low potential side power supply DVss and the low level reference voltages VrefL1 and VrefL2 are the ground potential, digital The high potential side power supply DVcc is set to an intermediate potential, for example, 3.3V.

  The determination circuit 2a receives the AD conversion signal Sdc1 output from the ADC 1a and the AD conversion signal Sdc2 output from the ADC 1b, and outputs the AD conversion signals Sdc1 and Sdc2 to an internal circuit (not shown) of the semiconductor device 10c, for example, during normal operation. Then, the AD conversion values of the AD conversion signals Sdc1 and Sdc2 are determined during the pass / fail determination test of the ADC 1a and ADC 1b, and a determination signal is output to the output terminal.

  Here, an example of a flowchart for detecting a failure of two ADCs provided in a semiconductor device corresponds to the case where the number of channels = 1 in FIGS. 5 to 6 of the flowchart example of the third embodiment. Specifically, the stage of “end of all channel selection” is not necessary.

As described above, in the semiconductor device of this embodiment, the ADC 1a, the ADC 1b, the determination circuit 2a, the channel selection circuit 3b, the switches SW11 to SW1n, the switch SW1n + 1, the switches SW21 to SW2k, the switch SW2n + 1, the input terminals Pin11 to Pin1n, the input terminal Pins 21 to 2k and an output terminal Pout are provided. Channel selection circuit 3b, the switch SW11 to SW1n, switch SW1n + 1, the switches SW21 to SW2k, generates a channel selection signal _{S SEL} to "ON" to any one of the switches SW2n + 1. ADC1a via the input terminal Pin11 to Pin1n, any of the input signal _{S IN11} to _{S IN1n} is an analog signal output from the sensor is operating normally when the inputted switch SW1n + 1 is "ON", Digital High When the input signal _{SINn + 1,} which is the potential side power supply DVcc voltage, is input, a _{pass / fail} judgment test is performed as a DUT. ADC1b via the input terminal Pin21 to Pin2k, any of the input signal _{S IN21} to _{S IN2k} is an analog signal output from the sensor is operating normally when the inputted switch SW2n + 1 is "ON", Digital High When the input signal _{SINn + 1,} which is the potential side power supply DVcc, is input, a _{pass / fail} judgment test is performed as a DUT. The determination circuit 2a receives the AD conversion signal Sdc1 output from the ADC 1a and the AD conversion signal Sdc2 output from the ADC 1b, and outputs the AD conversion signals Sdc1 and Sdc2 to an internal circuit (not shown) of the semiconductor device 10 during normal operation, for example. The AD conversion values of the AD conversion signals Sdc1 and Sdc2 are determined during the pass / fail determination test of the ADC 1a and ADC 1b, and a determination signal is output to the output terminal.

  For this reason, the addition of an external circuit and a test signal generation circuit are unnecessary, and it is possible to perform the pass / fail judgment of a plurality of ADCs more simply than in the third embodiment without complicating the control system. Further, since the circuit configuration can be simplified as compared with the ADC BIST circuit, an increase in chip area can be suppressed. Furthermore, it is possible to suppress a decrease in the number of analog input terminals required in the application.

  The present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the spirit of the invention.

  For example, in the embodiment, a microcomputer provided with one or more ADCs has been described. However, the present invention can be applied to an ADC provided in a processor, a SoC (System on a chip), or the like.

The present invention can be configured as described in the following supplementary notes.
(Supplementary Note 1) A test voltage signal is connected to the first high potential side power source and the first low potential side power source, and a voltage obtained by stepping down the first high potential side power source voltage or the first high potential side power source voltage is used. A test signal generation circuit that outputs a signal, a channel selection circuit that outputs a channel selection signal for performing a selective output control of the analog signal and the test voltage signal, and a second voltage having the same or higher voltage than the first high-potential-side power supply. Are connected to the high-potential-side power source and the second low-potential-side power source, supplied with the first high-level reference voltage and the first low-level reference voltage, and inputted with the analog signal and the test voltage signal to be selectively output The first analog-digital converter that outputs the first AD conversion signal, the third high-potential-side power supply and the third low-potential-side voltage having the same or higher voltage than the first high-potential-side power supply Connect to power The second high level reference voltage and the second low level reference voltage are supplied, and the analog signal to be selectively output and the test voltage signal are input to output a second AD conversion signal. A self-test failure detection method for a semiconductor device having an analog / digital converter and a determination circuit for inputting the first and second AD conversion signals, wherein the analog / digital converter performs the pass / fail test. Based on the channel selection signal, the same test voltage signal is input to the first and second analog / digital converters, and AD conversion is performed on each of the first and second analog / digital converters. And a step of inputting to a determination circuit and determining whether a difference between an AD conversion value of the first AD conversion signal and an AD conversion value of the second AD conversion signal is within a predetermined range. Self-test failure detection method of the semiconductor device.

(Supplementary Note 2) A test voltage signal is connected to the first high potential side power source and the first low potential side power source, and a voltage obtained by stepping down the first high potential side power source voltage or the first high potential side power source voltage is used. A test signal generation circuit that outputs a signal, a channel selection circuit that outputs a channel selection signal for performing a selective output control of the analog signal and the test voltage signal, and a second voltage having the same or higher voltage than the first high-potential-side power supply. Are connected to the high-potential-side power source and the second low-potential-side power source, supplied with the first high-level reference voltage and the first low-level reference voltage, and inputted with the analog signal and the test voltage signal to be selectively output The first analog-digital converter that outputs the first AD conversion signal, the third high-potential-side power supply and the third low-potential-side voltage having the same or higher voltage than the first high-potential-side power supply To power The second high level reference voltage and the second low level reference voltage are supplied, and the analog signal to be selectively output and the test voltage signal are input to output a second AD conversion signal. A self-test failure detection method for a semiconductor device having an analog / digital converter and a determination circuit for inputting the first and second AD conversion signals, wherein the analog / digital converter performs the pass / fail test. Based on the channel selection signal, the same test voltage signal is input to the first and second analog / digital converters, and AD conversion is performed on each of the first and second analog / digital converters. A step of inputting to the determination circuit and determining whether the AD conversion value of the first AD conversion signal and the AD conversion value of the second AD conversion signal are within a predetermined range; A step of inputting two AD conversion signals to a determination circuit and determining whether a difference between an AD conversion value of the first AD conversion signal and an AD conversion value of the second AD conversion signal is within a predetermined range; A self-test failure detection method for a semiconductor device comprising:

(Supplementary Note 3) A first switch that inputs an analog signal through a terminal and selectively outputs the first switch, a second switch that inputs and selectively outputs a first high-potential-side power supply voltage as the test voltage signal, A channel selection circuit for outputting a channel selection signal for performing selective output control of the first and second switches, a second high-potential-side power supply having a voltage equal to or higher than that of the first high-potential-side power supply, and a second The analog signal selected and output from the first switch and the test voltage signal selected and output from the second switch are connected to the low potential side power source An analog / digital converter that inputs the test voltage signal selected based on the channel selection signal and outputs an AD conversion signal in a pass / fail judgment test; Semiconductor device said type AD conversion signal, AD conversion value of the AD conversion signal; and a decision circuit for judging whether it is within a predetermined range.

(Supplementary Note 4) The first high-potential-side power source and the first low-potential-side power source, the first switch for inputting and selectively outputting the first analog signal via the terminal, and the second switch via the terminal A second switch for inputting and selectively outputting an analog signal; a third switch for inputting and selectively outputting the first high-potential-side power supply voltage as a test voltage signal; and the first high-potential-side power supply voltage Is input as the test voltage signal and is selectively output, a channel selection circuit that outputs a channel selection signal for performing selection output control of the first to fourth switches, and the first high potential side A first high-level reference voltage and a first low-level reference voltage connected to a second high-potential-side power supply and a second low-potential-side power supply having a voltage equal to or higher than that of the power supply; Selected output from switch 1 The first analog signal and the test voltage signal selected and output from the third switch are input, and the test voltage signal selected based on the channel selection signal is input during a pass / fail judgment test. A first analog-digital converter that outputs a first AD conversion signal; a third high-potential-side power supply having a voltage equal to or higher than the first high-potential-side power supply; and a third low-potential side The second analog signal and the fourth channel selection means, which are connected to a power source and supplied with a second high-level reference voltage and a second low-level reference voltage and selectively output from the second channel selection means. The test voltage signal selected and output from is input, and in the pass / fail judgment test, the test voltage signal selected based on the channel selection signal is input and a second AD conversion signal is input. The second analog / digital converter to be output and the first and second AD conversion signals are input during the pass / fail judgment test, and the AD conversion value of the first AD conversion signal and the second AD conversion are input. Determination whether the AD conversion value of the signal is within a predetermined range, or the difference between the AD conversion value of the first AD conversion signal and the AD conversion value of the second AD conversion signal is within the predetermined range A semiconductor device comprising: a determination circuit that determines whether or not.

1 is a block diagram showing a semiconductor device according to Embodiment 1 of the present invention. 4 is a flowchart showing a self-test name detection method for a semiconductor device according to Embodiment 1 of the present invention. FIG. 6 is a block diagram illustrating a semiconductor device according to a second embodiment of the invention. FIG. 6 is a block diagram illustrating a semiconductor device according to a third embodiment of the present invention. 10 is a flowchart showing a self-test name detection method for a semiconductor device according to Example 3 of the invention. 10 is a flowchart showing a self-test name detection method for a semiconductor device according to Example 4 of the invention. FIG. 9 is a block diagram illustrating a semiconductor device according to a fifth embodiment of the present invention.

Explanation of symbols

1, 1a, 1b ADC (Analog-to-Digital Converter)
2, 2a Determination circuit 3, 3a, 3b, 3c Channel selection circuit 4 Test signal generation circuit AVcc, AVcc1, AVcc2 Analog high potential side power supply AVss, AVss1, AVss2 Analog low potential side power supply DVcc Digital high potential side power supply DVss Digital low potential side power Pin1, Pin2, Pinn, Pin11, Pin12, Pin1n, Pin21, Pin22, Pin2k input terminal Pout output terminal Sdc, Sdc1, Sdc2 AD converted signal _{S IN, S IN1, S IN2} , S INn, S INn + 1, S INn + m, _{S INA, S INB, S IN11} , S IN12, S IN1n, S IN21, S IN22, S IN2k, S INn + 1, S INn + m input signal _{S SEL} channel selection signals SW1, SW2, SWn, SW + 1, SWn + m, SW11, SW12, SW1n, SW1n + 1, SW1n + m, SW21, SW22, SW2k, SW2n + 1, SW2n + m switch VrefH, VrefH1, VrefH2 high level reference voltage VrefL, VrefL1, VrefL2 low level reference voltage

Claims (5)

A test connected to the first high potential side power source and the first low potential side power source and outputting a voltage obtained by stepping down the first high potential side power source voltage or the first high potential side power source voltage as a test voltage signal. A signal generation circuit;
First channel selection means for inputting an analog signal via a terminal and selecting and outputting the analog signal;
Second channel selection means for inputting and selectively outputting the test voltage signal;
A channel selection circuit for outputting a channel selection signal for performing selection output control of the first and second channel selection means;
Connected to a second high potential side power source and a second low potential side power source having the same voltage as or higher than the first high potential side power source, and supplied with a high level reference voltage and a low level reference voltage, The analog signal selected and output from the first channel selection means and the test voltage signal selected and output from the second channel selection means are input, and are selected based on the channel selection signal during a pass / fail judgment test. An analog / digital converter that inputs the test voltage signal and outputs an AD conversion signal;
A determination circuit that inputs the AD conversion signal and determines whether an AD conversion value of the AD conversion signal is within a predetermined range;
A semiconductor device comprising: First channel selection means for inputting an analog signal via a terminal and selecting and outputting the analog signal;
Second channel selection means for inputting the first high-potential-side power supply voltage as a test voltage signal and selectively outputting it;
A channel selection circuit for outputting a channel selection signal for performing selection output control of the first and second channel selection means;
Connected to a second high potential side power source and a second low potential side power source having the same voltage as or higher than the first high potential side power source, and supplied with a high level reference voltage and a low level reference voltage, The analog signal selected and output from the first channel selection means and the test voltage signal selected and output from the second channel selection means are input, and are selected based on the channel selection signal during a pass / fail judgment test. An analog / digital converter that inputs the test voltage signal and outputs an AD conversion signal;
A determination circuit that inputs the AD conversion signal and determines whether an AD conversion value of the AD conversion signal is within a predetermined range;
A semiconductor device comprising: A test connected to the first high potential side power source and the first low potential side power source and outputting a voltage obtained by stepping down the first high potential side power source voltage or the first high potential side power source voltage as a test voltage signal. A signal generation circuit;
First channel selection means for inputting and selectively outputting a first analog signal via a terminal;
Second channel selection means for inputting a second analog signal via a terminal and selectively outputting the second analog signal;
Third channel selection means for inputting and selectively outputting the test voltage signal;
Fourth channel selection means for inputting and selectively outputting the test voltage signal;
A channel selection circuit for outputting a channel selection signal for performing selection output control of the first to fourth channel selection means;
The first high-level reference voltage and the first low-level reference are connected to a second high-potential side power source and a second low-potential side power source having the same voltage as or higher than the first high-potential side power source. A voltage is supplied, and the first analog signal selected and output from the first channel selection means and the test voltage signal selected and output from the third channel selection means are input, and during a pass / fail judgment test, A first analog-to-digital converter that inputs the test voltage signal selected based on the channel selection signal and outputs a first AD conversion signal;
The second high-level reference voltage and the second low-level reference are connected to a third high-potential side power source and a third low-potential side power source having the same voltage as or higher than the first high-potential side power source. Voltage is supplied, and the second analog signal selected and output from the second channel selection means and the test voltage signal selected and output from the fourth channel selection means are input, and during a pass / fail judgment test, A second analog-to-digital converter that inputs the test voltage signal selected based on the channel selection signal and outputs a second AD conversion signal;
In the pass / fail judgment test, the first and second AD conversion signals for the same test voltage signal of the test signal generation circuit are input, and the AD conversion value of the first AD conversion signal and the second AD conversion signal are input. Whether the AD conversion value of the first AD conversion signal is within a predetermined range, or whether the difference between the AD conversion value of the first AD conversion signal and the AD conversion value of the second AD conversion signal is within the predetermined range A determination circuit for determining
A semiconductor device comprising: A first high potential side power source and a first low potential side power source;
First channel selection means for inputting and selectively outputting a first analog signal via a terminal;
Second channel selection means for inputting a second analog signal via a terminal and selectively outputting the second analog signal;
Third channel selection means for inputting the first high-potential-side power supply voltage as a test voltage signal and selectively outputting the test voltage signal;
Fourth channel selection means for inputting and selectively outputting the first high-potential-side power supply voltage as the test voltage signal;
A channel selection circuit for outputting a channel selection signal for performing selection output control of the first to fourth channel selection means;
The first high-level reference voltage and the first low-level reference are connected to a second high-potential side power source and a second low-potential side power source having the same voltage as or higher than the first high-potential side power source. A voltage is supplied, and the first analog signal selected and output from the first channel selection means and the test voltage signal selected and output from the third channel selection means are input, and during a pass / fail judgment test, A first analog-to-digital converter that inputs the test voltage signal selected based on the channel selection signal and outputs a first AD conversion signal;
The second high-level reference voltage and the second low-level reference are connected to a third high-potential side power source and a third low-potential side power source having the same voltage as or higher than the first high-potential side power source. Voltage is supplied, and the second analog signal selected and output from the second channel selection means and the test voltage signal selected and output from the fourth channel selection means are input, and during a pass / fail judgment test, A second analog-to-digital converter that inputs the test voltage signal selected based on the channel selection signal and outputs a second AD conversion signal;
In the pass / fail judgment test, the first and second AD conversion signals are input, and the AD conversion value of the first AD conversion signal and the AD conversion value of the second AD conversion signal are within a predetermined range. Or a determination circuit for determining whether a difference between an AD conversion value of the first AD conversion signal and an AD conversion value of the second AD conversion signal is within a predetermined range;
A semiconductor device comprising: A test connected to the first high potential side power source and the first low potential side power source and outputting a voltage obtained by stepping down the first high potential side power source voltage or the first high potential side power source voltage as a test voltage signal. A signal generation circuit; a channel selection circuit that outputs a channel selection signal that performs selection output control of the analog signal and the test voltage signal; and a second high voltage that is the same as or higher than the first high-potential-side power supply. Connected to the potential side power source and the second low potential side power source, supplied with the high level reference voltage and the low level reference voltage, inputs the analog signal and the test voltage signal to be selectively output, and outputs an AD conversion signal A self-test failure detection method for a semiconductor device having an analog / digital converter and a determination circuit for inputting the AD conversion signal,
During the pass / fail test of the analog / digital converter,
Inputting the test voltage signal to the analog-to-digital converter based on the channel selection signal, and performing AD conversion;
Inputting an AD conversion signal output from the analog / digital converter to a determination circuit, and determining whether an AD conversion value of the AD conversion signal is within a predetermined range;
A self-test failure detection method for a semiconductor device, comprising:

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