DE112017007828T5 - Signal processing device and test method - Google Patents

Abstract

A signal processing device (10) contains an A / D converter (14), a test signal feeder (12), a determiner (15) and an output device (16). The A / D converter (14) converts an analog signal into a digital signal and outputs the digital signal. The test signal feeder (12) supplies an analog test signal, which corresponds to a test bit pattern, to the A / D converter (14). When a level of the analog test signal supplied to the A / D converter (14) switches, the determiner (15) determines whether a value of a bit to be tested of the digital signal output from the A / D converter (14) after switching the level of the analog test signal. The output device (16) outputs a result of the determination by the determiner (15).

Description

Technical field

The present disclosure relates to a signal processing device and a test method.

State of the art

A system that includes both analog and digital circuits uses converters, such as an A / D converter and a D / A converter, to convert an analog signal to a digital signal and vice versa. Failure of converters in such a system prevents the system from achieving normal conversion processing of an analog signal and a digital signal, making normal operation of the system difficult. Therefore, accurate detection of the converter failure is desirable.

Various test methods for detecting the failure of the converter are proposed. For example, Patent Literature 1 proposes a technique for detecting an error by inputting an analog test signal into an A / D converter and determining whether the data output from the A / D converter is within a range of predetermined conversion standard values. However, this test method has trouble detecting an error in a case where lower data bits output from the A / D converter are set to 1 or 0 unchanged and the data contains a small amount of noise.

On the other hand, Patent Literature 2 discloses a technique for inputting a plurality of reference voltages into an A / D converter and for determining whether an actual output value and a normal output value match. This technique also enables the detection of an error in which certain data bits output by the A / D converter are set to 0 or 1.

Citation list

Patent literature

• Patent Literature 1: Untested Japanese Patent Application Kokai, Publication No. 2007-285764
• Patent Literature 2: Untested Japanese Patent Application Kokai, Publication No. H8-56160

Summary of the invention

Technical problem

As described above, the technique of Patent Literature 1 has difficulty detecting an error in which certain bits of a digital data item are set to 1 or 0.

In addition, the technique of Patent Literature 2 detects an error by determining whether the actual output value of the A / D converter and the normal output value match, and is thus able to recognize the error but not able to detect one Identify type of error. For example, if an error occurs with certain bits of data set to 0 or 1, for example, although the technique allows detection of the error, further analysis of the output values is required to determine if the error is an error with certain bits of data set are.

Similar problems arise when testing a D / A converter.

The present disclosure is made in view of the aforementioned problems, and an object of the present disclosure is to enable easy detection of an error in which values of certain bits are set.

the solution of the problem

• ein A/D-Umwandlungsmittel zum Umwandeln eines analogen Signals in ein digitales Signal und zum Ausgeben des digitalen Signals;
• ein Zuführmittel zum Zuführen eines einem Testbitmuster entsprechenden analogen Testsignals zu dem A/D-Umwandlungsmittel;
• ein Bestimmungsmittel zum Bestimmen, wenn ein Pegel des analogen Testsignals, das dem A/D-Umwandlungsmittel zugeführt wird, umschaltet, ob ein Wert eines zu testenden Bits des von dem A/D-Umwandlungsmittel ausgegebenen digitalen Signals nach dem Umschalten des Pegels des analogen Testsignals umschaltet; und
• ein Ausgabemittel zum Ausgeben eines Ergebnisses der Bestimmung durch das Bestimmungsmittel.

To solve the aforementioned problems, a signal processing device of the present disclosure includes:

• A / D converting means for converting an analog signal into a digital signal and outputting the digital signal;
• supply means for supplying an analog test signal corresponding to a test bit pattern to the A / D converting means;
• determining means for determining when a level of the analog test signal supplied to the A / D converting means switches whether a value of a bit of the digital signal output from the A / D converting means to be tested after switching the level of the analog test signal toggles; and
• an output means for outputting a result of the determination by the determination means.

Advantageous effects of the invention

According to the present disclosure, a determination is made whether a value is one testing bits of the digital signal obtained by converting an analog test signal and output from the A / D converting means switches according to the level of the analog test signal. This configuration enables the occurrence of an error in which a value of a bit is set to be detected based on an output value from the A / D converting means without comparing an input value and the output value from the A / D converting means, thereby making a easy detection of an error in which a value of a bit is fixed.

Figure list

• 1 10 is a block diagram of a signal processing device according to Embodiment 1 of the present disclosure;
• 2nd Fig. 12 is a diagram showing an example of a pattern table stored in a memory of 1 is saved.
• 3rd FIG. 14 is a flowchart of test processing performed by the signal processing device according to Embodiment 1;
• 4A shows the flag and a change in the values in the flag immediately after initialization;
• 4B shows the flag and a change in values in the flag in which all bit values of data output from an A / D converter are switched;
• 4C shows the flag and a change in the values in the flag in which the least significant data bit output from the A / D converter is set to zero;
• 4D shows the flag and a change in values in the flag in which the least significant bit is set to 1;
• 5A Fig. 1 is a first diagram showing another example of the pattern table according to Embodiment 1;
• 5B Fig. 2 is a second diagram showing still another example of the pattern table according to Embodiment 1;
• 5C Fig. 3 is a third diagram showing still another example of the pattern table according to Embodiment 1;
• 6 10 is a block diagram of a signal processing device according to Embodiment 2 of the present disclosure;
• 7 FIG. 14 is a flowchart of test processing performed by the signal processing device according to Embodiment 2;
• 8th 10 is a block diagram of a signal processing device according to Embodiment 3 of the present disclosure;
• 9 FIG. 14 is a flowchart of test processing performed by the signal processing device according to Embodiment 3;
• 10th 10 is a block diagram of a signal processing device according to Embodiment 4 of the present disclosure;
• 11 FIG. 14 is a flowchart of operational test processing performed by the signal processing device according to Embodiment 4;
• 12th FIG. 10 is a flowchart of test processing performed by a signal processing device according to Embodiment 5 of the present disclosure;
• 13 10 is a block diagram of a signal processing device according to Embodiment 6 of the present disclosure;
• 14 FIG. 14 is a diagram showing an example of a pattern table according to Embodiment 7 of the present disclosure;
• 15 FIG. 11 is a flowchart of test processing performed by a signal processing device according to Embodiment 7;
• 16 10 is a block diagram of a signal processing device according to Embodiment 8 of the present disclosure;
• 17th FIG. 4 is a block diagram of a signal processing device according to modification 1 of the present disclosure; and
• 18th FIG. 4 is a block diagram of a signal processing device according to modification 2 of the present disclosure.

Description of embodiments

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings.

Embodiment 1

A signal processing device 10th according to the present embodiment, has an A / D conversion function for converting an analog signal into a digital signal and outputting the digital signal by an A / D converter, and a test function for performing an operational test of an A / D converter by supplying Test signals to the A / D converter and monitoring of changes in a value of each data bit output from the A / D converter.

Hereinafter, an operation of the A / D converter for converting an analog input signal into a digital signal and for outputting the digital signal is referred to as a normal operation, and an operation for testing the A / D converter is referred to as a test operation. In the following description, the signal can be either a voltage signal or a current signal.

As in 1 shown includes the signal processing device 10th an input port 101 , into which an analog signal is input, an output connector 102 for outputting a converted digital signal, a memory 11 that stores data, a test signal feeder 12th , which generates an analog test signal, which is used for the operational test, a selector 13 that one into an A / D converter 14 selects the signal to be input, the A / D converter 14 , which serves as an A / D conversion means, a determiner 15 that determines whether the A / D converter 14 fails, and an output means 16 which outputs information indicating that the A / D converter 14 fails.

The input port 101 is a connector for inputting an analog signal from the outside from the signal processing device 10th to be converted into a digital signal. A temperature sensor, an illuminance sensor, a speed sensor and other sensors or a device that outputs an analog signal, for example, are connected to the input terminal 101 connected. A DC voltage that falls in a range from -10 V to +10 V or a DC current that falls in a range from 0 mA to 20 mA, for example, is input to the input terminal 101 entered.

The output connector 102 is a terminal for outputting values of bits of the digital signal by the signal processing device 10th can be converted in parallel. A device by the signal processing device 10th Output signals used is with the output connector 102 connected. The output connector 102 outputs, for example, a 16-bit digital signal that indicates an integer in the range of -32,768 to +32,767, or a 15-bit digital signal that indicates an integer in the range of 0 to 32,767.

The memory 11 contains a non-volatile memory such as an electrically erasable programmable read-only memory (EEPROM) and a flash memory. The memory 11 stores various data from the signal processing device 10th be used. The data contains a sample table 111 used to generate an analog test signal for testing the A / D converter 14 is used. Although the present disclosure is not limited, the memory functions 11 as a storage medium in the claims.

The sample table 111 is a list containing two predetermined test bit patterns. Each of the test bit patterns is used to determine whether there are values of bits from the A / D converter 14 change output digital signal without being fixed. As in the example of 2nd shown is the sample table 111 according to the present embodiment, a list with two test bit patterns. These test bit patterns are determined such that each bit of all the bits to be tested has a value that is complementary to a value of the corresponding bit. That is, a value of one test bit pattern is set so that it is its own complement to the value of the other test bit pattern.

When performing the test operation, the test signal feeder generates 12th analog test signals that correspond to the test bit patterns and delivers the analog test signals via the selector 13 to the A / D converter. Although this does not limit the present disclosure, the test signal feeder functions 12th as feed means in the claims.

In particular, the test signal feeder contains 12th a test signal generation module 121 . The test signal generation module 121 contains a D / A converter circuit for generating analog test signals from the test bit patterns of the pattern table 111 . The test signal generation module 121 has conversion properties that enable conversion that is opposite to conversion by conversion properties of the A / D converter 14 is achieved. Such conversion properties enable the test signal generation module 121 to generate an analog test signal with a signal level that corresponds to the A / D converter 14 causes digital signals to be output from memory 11 correspond to read test bit patterns. The test signal feeder 12th reads from the sample table 111 the test bit patterns sequentially to generate the analog test signals. In this way, the test signal feeder changes 12th a signal level of the analog test signal, thereby giving a value of each bit of the A / D converter 14 output digital signal is switched. The test signal feeder 12th gives the generated analog test signal to the selector 13 out.

The selector selects during normal operation 13 an analog signal to be converted, which from the outside via the input connection 101 is supplied, and supplies the analog signal to the A / D converter 14 . The selector chooses when performing the test 13 that from the test signal provider 12th supplied analog test signal and carries the analog signal to the A / D converter 14 to. In the following description, in order to distinguish it clearly from the analog test signal, the input connection 101 supplied analog signal also expressed as a non-test signal.

The A / D converter 14 serves as an A / D converter circuit. The A / D converter 14 discretizes and quantizes an input analog signal with a predetermined sampling period and resolution, converts the discretized and quantized analog signal into a digital signal, and outputs the digital signal to the output terminal 102 and the determiner 15 out. The A / D converter converts during normal operation 14 a non-test signal from the selector 13 is supplied, ie an analog signal to be converted, which is sent from the outside via the input connection 101 is delivered into a digital signal and outputs the digital signal. The A / D converter converts when the test operation is carried out 14 that of the selector 13 supplied analog test signal into a digital signal and outputs the digital signal. That from the A / D converter 14 The digital signal output during the test operation must be provided that the A / D converter 14 works normally, have a value that corresponds to the value of the test bit pattern from which the supplied analog test signal, generated by the test signal feeder 12th , comes from. Although this does not limit the present disclosure, the A / D converter functions 14 in the claims as the A / D converting agent.

The determiner 15 contains a microprocessor unit (MPU). The determiner 15 determines whether values of bits contained in the digital signal are obtained by converting the analog test signal and from the A / D converter 14 output, switch when a level of the analog test signal switches. In order to determine whether an error occurs with a value of a bit fixed, the determiner determines 15 for each bit of a plurality of bits of the digital data element to be tested, whether a value of the bit is different before or after switching the level of the analog test signal. The level of the analog test signal corresponds to the test bit patterns, and thus the determiner determines 15 whether a bit value of the digital signal switches when the test bit pattern corresponding to the analog test signal switches. A method of performing the determination is described below. To make the determination is the determiner 15 provided with a flag containing data showing whether the value of each bit contained in the digital signal has been switched. The flag is described in detail below. Although this does not limit the present disclosure, the determiner functions 15 as a determining means in the claims.

The output device 16 includes, for example, a network interface controller (NIC) that enables communication with external devices over a network, and a light emitting diode (LED) or a buzzer. The output device 16 gives a result of the determination by the determination device 15 out. Especially when the determination device 15 determines that an error occurs in which a value of a bit is set, the output device outputs 16 Information from a fault of the A / D converter 14 specify. This information can be data that shows the details of the error and can be output as a LED light or as a buzzer warning sound. Although this does not limit the present disclosure, the output device functions 16 as the output device in the claims.

The control 17th contains an MPU, read-only memory (ROM) and random access memory (RAM). The control 17th centrally controls each component of the signal processing device through its MPU 10th , using the RAM as a work area to put one in the ROM or memory 11 run the saved program. The control 17th can also be used as the determining device 15 and the output device 16 serve.

Next, the signal processing device 10th processing performed with reference to the 3rd and 4th described. During normal operation of the signal processing device 10th initiates the control 17th the selector 13 that to the input connector 101 select the supplied analog signal.

This enables the signal processing device 10th , a normal conversion process for converting the input port 101 supplied analog signal into a digital signal through the A / D converter 14 and outputting the digital signal from the output terminal 102 perform.

On the other hand, the control system leads 17th to test operation of the A / D converter 14 one in 3rd test processing shown by. This test processing starts at a predetermined time.

Although all of the following operations are under the control of the controller 17th this control is not mentioned every time to facilitate understanding. In the test processing, the signal processing device selects 10th the analog test signal as one in the A / D converter 14 signal to be entered (step S1 ). In particular, the selector 13 caused that by that Test signal feeder 12th output analog test signal.

Next, the signal processing device initializes 10th the one with the determiner 15 equipped flag (step S2 ). The flag is data that indicates whether a value of each bit is in that of the A / D converter 14 output digital signal is included, has switched. A flag according to the present embodiment is formed as hardware in that two latch arrays are included. The method of obtaining the flag is not limited to this method, and the flag can be obtained by software as a flag field.

A flag initialization process involves assigning a value of “FFFFh” to a first latch and a value of “0000h” to a second latch. 4A shows a state of the flag immediately after completion of the initialization. The value of "FFFFh" indicates a 16-bit pattern in which all bit values are 1, and the last "h" of this value indicates that the value is expressed in hexadecimal.

Next, the signal processing device chooses 10th a first test bit pattern of the pattern table 111 off (step S3 ). In particular, the test signal feeder reads 12th from memory 11 a first in the pattern table 111 included test bit pattern. The test signal feeder 12th reads, for example, a test bit pattern of "11 ... 11" from the pattern table 111 in 2nd .

Next, the signal processing device generates 10th an analog test signal with a level that corresponds to the selected test bit pattern and supplies the analog test signal to the A / D converter 14 (Step S4 ). In particular, the test signal generation module generates 121 of the test signal feeder 12th by performing D / A conversion, an analog signal that the A / D converter 14 causes a digital signal to be output that is equal to the selected test bit pattern. For example, the test signal generation module generates 121 in step S4 who made the step S3 follows in which the first test bit pattern of 2nd is selected, an analog test signal that the A / D converter 14 causes a digital signal from "11 ... 11" to be output.

Next, the signal processing device updates 10th the flag according to a bit value of that from the A / D converter 14 output digital signal (step S5 ). In particular, the determiner updates 15 a value of the first latch array using an AND operation result between an output value from the A / D converter 14 and the value of the first latch array and updates a value of the second latch array using a result of an OR operation between the output value of the A / D converter 14 and the value of the second latch array. For example, if an analog test signal with a level corresponding to the first test bit pattern of 2nd is generated and the A / D converter 14 works normally, the value of the first latch array is updated to "FFFFh" as a result of the AND operation and the value of the second latch array is updated to "FFFFh" as a result of the OR operation. On the other hand, if, for example, the A / D converter 14 works abnormally and causes a value of the least significant data bit to be output by the A / D converter 14 is set to zero, the value of the first latch array is updated to "FFFEh" due to the AND operation, and the value of the second latch array is updated to "FFFEh" due to the OR operation.

Next, the signal processing device determines 10th whether the currently selected test bit pattern is the last test bit pattern (step S6 ). In particular, the determiner determines 15 whether a test bit pattern that the last number in the pattern table 111 assigned is selected.

If it is determined that the currently selected test bit pattern is not the last bit pattern (no in step S6 ), selects the signal processing device 10th the next test bit pattern (step S7 ). In particular, the test signal feeder reads 12th a test bit pattern to which the next number is assigned from the pattern table 111 of memory 11 . For example, the test signal feeder reads 12th a test bit pattern of "00 ... 00" as a second bit pattern after reading the in 2nd shown first test bit pattern.

After the step S7 repeats the signal processing device 10th the processes in and after the step S4 . This repetition enables the subsequent generation of analog test signals, each one of which is in the pattern table 111 included test bit pattern, which allows the flag to be updated whenever the level of the analog test signal changes. For example, if an analog test signal with a level corresponding to the second test bit pattern of 2nd is generated and the A / D converter 14 works normally, the value of the first latch array as a result of the AND operation is updated to "0000h" and the value of the second latch array as a result of the OR operation to "FFFFh", as in 4B shown.

For example, if the A / D converter 14 works abnormally and causes a value of the least significant bit (LSB) to be that of the A / D converter 14 output data is set to zero, the value of the first latch array is updated to "0000h" as a result of the AND operation and the The value of the second latch array is updated to “FFFEh” as a result of the OR operation, as in 4C is shown. If the value of the least significant bit is set to 1, the value of the first latch array as a result of the AND operation is updated to "0001h" and the value of the second latch array as a result of the OR operation is updated to "FFFFh" as in 4D is shown. Such a comparison of the value of the first latch array and the value of the second latch array makes it possible to determine a case in which a value of the bit is set to 1 and a case in which a value of the bit is set to zero .

When determining in step S6 that the currently selected test bit pattern is the last test bit pattern (yes in step S6 ), determines the signal processing device 10th for each bit to be tested whether a value of the bit changes after the level of the analog test signal has changed (step S8 ). In other words, the signal processing device determines 10th for each bit to be tested whether a value of the bit has become both 1 and 0. In particular, the determiner determines 15 by determining whether the value of the first latch array is "0000h" and the value of the second latch array is "FFFFh", as in 4B It is shown whether each value of the bit to be tested contains the bits contained in the digital signal from the A / D converter 14 is included, is a value different from that before changing the level of the analog test signal. For example, if the flag is in a state that is in 4B is shown, it is determined that all values of bits have been switched. If the flag is in a state that is in 4C or 4D is shown, a determination is made that the value of the least significant bit has not switched.

After determining that all values of the bits have switched (yes in step S8 ), selects the signal processing device 10th the non-test signal as one in the A / D converter 14 signal to be entered (step S9 ). In particular, the selector chooses 13 the non-test signal by controlling a switching device for switching a transmission line of a signal and for connecting the input terminal 101 with the A / D converter 14 out. At this point, the output device 16 Output display information that the A / D converter 14 works normally. Then the signal processing device ends 10th the test processing.

On the other hand, the signal processing device gives 10th after determining that values of certain bits to be tested have not been switched (No in step S8 ), an error signal (step S10 ). In particular, the output device gives 16 a result of the determination by the determiner 15 out. From the output device 16 Output information may include information that indicates that the A / D converter 14 fails, information indicating a position of a bit contained in the digital signal and the value of which is fixed, and information indicating whether the fixed value is 1 or zero. Then the signal processing device ends 10th the test processing. The signal processing device 10th can after step S10 the non-test signal as one in the A / D converter 14 Select the signal to be entered.

As described above, the signal processing device determines 10th for each bit in that of the A / D converter 14 output digital signal is included whether a value of the bit switches to a level of the analog test signal. This configuration enables detection of the occurrence of an error in which a bit value of the A / D converter 14 is set, without an input value and an output value of the A / D converter 14 to compare, which enables easy detection of an error in which the value of the bit is fixed.

The determiner also uses 15 a first latch array that is ANDed and a second latch array that is ORed as a flag that indicates whether each bit is fixed. A value of the flag differs depending on whether the bit value is switched or the bit value is fixed. Thus, the signal processing device gives 10th an error signal only if the value of the bit is fixed. Therefore, an error in which a bit value is set leads to an output of an error signal regardless of whether an actual output value of the A / D converter 14 is normal or not. Such a configuration enables the detection accuracy of an error in which a bit value is fixed to be improved.

The memory also saves 11 predetermined test bit patterns, and the test signal feeder 12th generates analog test signals, each with a level that corresponds to the corresponding test bit pattern. Such a configuration enables only by storing suitable test bit patterns in advance in the memory 11 the generation of suitable analog test signals, which enables the test processing to be carried out.

To save the pattern table 111 in the store 11 different techniques can be used. For example, a pre-made analog circuit can serve as the memory 11 serve. Reaching the memory function 11 with the analog circuit is relatively simple, especially if the width of the test bit pattern is small or that Number of test bit patterns is small. Such a configuration enables the saving of capacity of memory elements in the signal processing device 10th are included, or the omission of the storage elements.

In addition, the sample table 111 not on that in 2nd limited example shown. If, for example, sample tables 111 used in the 5A , 5B and 5C the performance of the test operation of the A / D converter can also be shown 14 be achieved.

The sample table 111 of 5A contains two test bit patterns similar to the example of the pattern table from 2nd . The bit values of these test bit patterns are complementary to one another.

The sample table 111 of 5B contains three test bit patterns. As in 5B shown is a sample table 111 containing three or more test bit patterns contain test bit patterns that cause the value of each bit to be tested to become both zero and 1. The same applies to a sample table 111 , which contains two test bit patterns and in this case the bit values of the two test bit patterns, as described above, must be complementary to one another. Although 5B an example of the sample table 111 shows which is used when the A / D converter 14 outputs an 8-bit digital signal is one such pattern table 111 applicable in other cases regardless of the number of bits contained in the digital signal.

Although in the 2nd , 5A and 5B shown test bit pattern, test bit pattern for testing all bits of the A / D converter 14 output digital data element, the bits to be tested can be assigned to certain bits of the A / D converter 14 output digital data element may be limited, for example limited to the lower 8 bits. In such a case, the pattern table 111 Store two test bit patterns, the bit patterns of which are complementary to each other only in the lower 8 bits, as in 5C shown. In this case, a simple bit-wise evaluation of the flag to be tested is sufficient with regard to the flag.

Embodiment 2

Next, Embodiment 2 will be described with a focus on differences from Embodiment 1 described above. Components that have the same or corresponding configurations as those in Embodiment 1 are given the same reference numerals. Although a case of direct use of in the store 11 stored test bit patterns for a test operation in Embodiment 1, in the present embodiment, a plurality of test bit patterns are obtained by performing arithmetic processing on a plurality of digital data elements to generate analog test signals.

In the present embodiment, the memory stores 11 several digital data elements 112 , as in 1 shown. The digital data elements 112 are, for example, equal to the test bit patterns in the pattern table 111 according to embodiment 1 (see 2nd ) are included.

The test signal feeder 12th contains an addition module 122 . The addition module 122 contains an adder for adding a specific digital value. The addition module 122 reads the digital data element 112 from memory 11 and adds an offset value to a value by the digital data element 112 is shown. The offset value can be a value that is predetermined and stored in an auxiliary memory, or a fixed value of the design of the adding circuit. Then there is the addition module 122 a test bit pattern to the test signal generation module 121 which indicates a sum obtained by adding the offset. The test signal generation module 121 generates an analog test signal based on that from the addition module 122 output test bit pattern. Although not limiting the present disclosure, the addition module functions 122 as the addition agent in the claims.

Next, the signal processing device 10th performed test processing with reference to FIG 7 described. As in 7 shown, the test processing according to the present embodiment includes the processes similar to those in the steps S1 - S2 according to embodiment 1.

After the step S2 reads the addition module 122 a first digital data element 112 from memory 11 (Step S21 ). If the multitude of digital data elements 112 same as in 2nd test bit patterns shown is the first digital data element 112 equal to the first test bit pattern of 2nd . The multitude of digital data elements 112 can however be read in any order.

The test signal feeder delivers next 12th an analog test signal with a level corresponding to the test bit pattern, which is obtained by adding the offset value to the read digital data element 112 is obtained (step S22 ). In particular, the test signal generation module generates 121 by performing D / A conversion, an analog signal that the A / D converter 14 causes a digital signal to be output that corresponds to that of the addition module 122 output test bit pattern corresponds. If the value is set to zero, the test bit pattern is equal to the read digital data element 112 .

Next is the signal processing device 10th one step S5 which is similar to that of Embodiment 1. After the step S5 determines the signal processing device 10th whether the current digital data item 112 the last one in memory 11 stored digital data element 112 is (step S23 ).

If the determination in step S23 is negative (no in step S23 ), creates the addition module 122 a new test bit pattern by reading the next digital data element 112 and adding an offset value (step S24 ). This offset value is the same as the offset value in step S22 after step S21 is used.

After the step S24 repeats the signal processing device 10th the processes in and after the step S22 . Thus, every time the offset value becomes the digital data item 112 is added to generate a test bit pattern, an analog test signal is generated at a level corresponding to the test bit pattern.

If the determination in step S23 is positive (yes in step S23 ), leads the signal processing device 10th Processes similar to those in the steps S8 - S10 of embodiment 1 by.

As described above, the test signal feeder contains 12th the signal processing device 10th the addition module 122 , and analog test signals are generated that match the test bit patterns by the addition module 122 can be obtained by adding a fixed offset value to different digital data elements 112 is added. Such a configuration makes it possible to switch between different types of sets of test bit patterns that are used when carrying out the test operation only by suitably setting the offset value. For example, if the majority of digital data items 112 same as in 5C test bit patterns shown, changing the offset value is sufficient to change the bits to be tested. Similarly, if the plurality of digital data items 112 same as in 2nd shown test bit patterns, changing the offset value is sufficient to change bits to be tested, for example to obtain test bit patterns which correspond to those shown in FIG 5C correspond to the test bit patterns shown.

Embodiment 3

Next, Embodiment 3 will be described with a focus on differences from Embodiment 2 described above. Components that have the same or corresponding configurations as those in Embodiment 2 are given the same reference numerals. As in 8th shown includes a signal processing device 10th according to the present embodiment, an adjuster 18th which differentiates the present embodiment from the embodiment 2.

Embodiment 2 described above is based on the premise that the A / D converter 14 has constant conversion properties. Even if a level of an analog signal is sent to the A / D converter 14 is constant, a value can be obtained from the A / D converter 14 output digital signal actually change due to various factors such as temperature drift. When such a change occurs, it can be difficult to adequately detect an error with a bit value set. The signal processing device 10th according to the present embodiment compensates for the change described above using the adjuster 18th and causes the A / D converter 14 to output a digital signal suitable for the operational test. The signal processing device 10th according to the present embodiment will be described below.

The function of the adjuster 18th is achieved by an MPU. The adjuster 18th sets the offset value so that there is a difference between a value obtained by the addition module 122 outputted test bit pattern is displayed, and a value of that from the A / D converter 14 output digital signal becomes 0. In particular, the adjuster compares 18th a test bit pattern after adding the offset value with a value of a digital signal obtained by converting an analog test signal according to the test bit pattern and from the A / D converter 14 is issued. Then the adjuster corrects 18th the offset value based on the comparison such that the difference becomes 0, causing the A / D converter 14 is caused to output a digital signal that is equal to the original test bit pattern. The adjuster functions without any particular restriction 18th as an adjusting means in the claims.

Next, the signal processing device 10th performed test processing with reference to FIG 9 described. As in 9 shown, the test processing according to the present embodiment includes processes similar to those in the steps S1 - S2 and S21 - S22 according to Embodiment 2.

After the step S22 determines the signal processing device 10th whether a difference between a current test bit pattern and a value of a digital signal from the A / D converter 14 output is equal to or greater than a threshold (step S31 ). In particular, the adjuster determines 18th whether there is a difference between a value by one from the addition module 122 outputted test bit pattern is displayed, and a value of a digital signal obtained by converting an analog test signal generated based on the test bit pattern and from the A / D converter 14 output is equal to or greater than a predetermined threshold. The threshold can be zero or a non-zero value.

If a determination is made that the difference is not equal to or greater than the threshold value (no in step S31 ), the processing goes through the signal processing device 10th to step S5 about. On the other hand, if it is determined that the difference is equal to or greater than the threshold (Yes in step S31 ), the signal processing device 10th the offset value to reduce the difference (step S32 ). In particular, the adjuster corrects 18th the offset value by reducing a difference obtained by decreasing from the value of that obtained by the A / D converter 14 output digital signal of the value of that from the addition module 122 output test bit pattern.

Then the signal processing device performs 10th processing in and after the step S5 of embodiment 2 by.

As described above, the signal processing device includes 10th the adjuster 18th that sets the offset value. By the adjuster 18th setting the offset value causes the A / D converter 14 outputs a digital signal suitable for the test, whereby the signal processing device 10th can diagnose exactly whether bit values are fixed.

Embodiment 4

Next, Embodiment 4 will be described with a focus on differences from Embodiment 1 described above. Components that have the same or corresponding configurations as those in Embodiment 1 are given the same reference numerals. As in 10th shown includes a signal processing device 10th a timer according to the present embodiment 19th for performing regular test processing that differentiates the present embodiment from embodiment 1.

To perform the operation test of the A / D converter in Embodiment 1 described above 14 to perform, an analog test signal is supplied to the A / D converter, which is different from the non-test signal, which is from the input connection 101 the signal processing device 10th is entered. Thus, the signal processing device 10th not realize their intrinsic performance. However, the operational test does not have to be performed when switching a bit value from one of the A / D converters 14 output digital signal can be detected in a state in which the non-test signal is supplied. An example of omitting regular test processing in such a case is made with reference to FIG 10th and 11 described.

The timer 19th contains a crystal oscillator or an oscillator circuit. The timer 19th outputs to the test signal generation module 121 in a predetermined cycle a trigger signal indicating a start time of the test. For example, the cycle is 8 hours, 24 hours, or a week. However, a different cycle can also be used.

Next, the signal processing device 10th operational test processing performed with reference to FIG 11 described. The operational test processing can be performed after the signal processing device is turned on 10th begin or may be following an instruction from a user of the signal processing device 10th kick off.

In the operational test processing, the signal processing device selects 10th the non-test signal as one in the A / D converter 14 signal to be entered (step S41 ). Next is the signal processing device 10th a flag initialization process (step S42 ). The initialization process is equivalent to the initialization process in step S2 who in 3rd of embodiment 1 is shown.

Next, the signal processing device updates 10th the flag according to a bit value of a digital signal, which is from the A / D converter 14 is output to correspond to the non-test signal (step S43 ). In particular, the determiner updates 15 the values of the two latch arrays using a value of the digital signal obtained by converting the non-test signal and from the A / D converter 14 is issued. In particular, the determiner updates 15 a value of the first latch array using an AND operation result between one of the A / D converter 14 output value and the value of the first latch array and updates a value of the second latch array using a result of an OR operation between that of the A / D converter 14 output value and the value of the second latch array.

Next, the signal processing device determines 10th whether the current time is the start time of the test processing (step S44 ). In particular, the test signal feeder determines 12th whether the timer 19th has issued the trigger signal.

When determining that the current time is not the start time of the test processing (No in step S44 ), the signal processing device repeats 10th the execution of the processes in and after step S43 . Thus, the flag is generated using the digital signal from the A / D converter 14 based on the non-test signal being output, updated repeatedly. Typically, the level of the non-test signal changes from moment to moment, and therefore the flag must be updated based on a plurality of the non-test signals, each of which has a different level.

On the other hand, if it is determined that the current time is the start time of the test processing (Yes in step S44 ), determines the signal processing device 10th for each bit to be tested whether a value of the bit differs before or after the level of the non-test signal changes (step S45 ). In other words, the signal processing device 10th determines for each bit to be tested whether a value of the bit becomes both 1 and zero. In particular, the determiner determines 15 by determining whether the value of the first latch array is "0000h" and the value of the second latch array is "FFFFh", as in 4B shown whether a value of each bit to be tested of the bits in the by the A / D converter 14 output digital signal are included, switches.

If the determination in step S45 is positive (yes in step S45 ), the processing goes through the signal processing device 10th to step S42 over without the test processing from step S46 is carried out. Thus, an operational test using the non-test signal is carried out repeatedly.

On the other hand, if the determination in step S45 is negative (no in step S45 ), leads the signal processing device 10th the test processing by (step S46 ). The test processing is the same as in 3rd shown processing series.

Next, the signal processing device determines 10th whether an error signal in the test processing of step S46 is output (step S47 ). If it is determined that no error signal is being output (No in step S47 ), the signal processing device repeats 10th processing in and after step S42 . When determining that an error signal is being output (Yes in step S47 ), the signal processing device ends 10th the operational test processing.

As described above, the test signal feeder generates 12th periodically an analog test signal and supplies the analog test signal to the A / D converter 14 . Thus, the test processing is carried out periodically. Therefore, the detection of an error can be achieved in a relatively short time when the A / D converter 14 fails.

The determiner also determines 15 whether values of bits contained in the digital signal are obtained by converting the non-test signal and from the A / D converter 14 are output, switched, and the test signal feeder 12th omits the generation of the next analog test signal if it is determined that a value of the bit is switched based on the non-test signal. Such a configuration enables a fault in the A / D converter to be recognized 14 based on the non-test signal and enables the reduction to the signal processing device 10th applied load by omitting the execution of the test processing.

Embodiment 5

Next, Embodiment 5 will be described with a focus on differences from Embodiment 4 described above. Components that have the same or corresponding configurations as those in Embodiment 4 are given the same reference numerals. Since the test processing of Embodiment 4 is equivalent to that of Embodiment 1, the same reference numerals as in Embodiment 1 are used for the test processing.

In embodiment 4 described above, analog test signals each having a level corresponding to the corresponding test bit pattern of the plurality of test bit patterns are generated in a similar order as in embodiment 1. However, when values of certain bits of the bits are to be switched when the signal under test can be detected in a state in which the non-test signal is passed to the A / D converter 14 there is no need to generate analog test signals using test bit patterns to switch the values of the particular bits. An intensive test can thus be carried out for one or more bits whose changes in value cannot be detected based on the non-test signal. Such test processing is described below.

As in 12th shown, a process is similar to the process in step S1 of embodiment 1 performed in the test processing of the present embodiment. Next, the signal processing device relates 10th on the flag (step S51 ). In particular, the test signal generation module relates 121 to values of the first latch array and the second latch array.

Next, the signal processing device chooses 10th based on the non-test signal a first test bit pattern that corresponds to a value that is not from the A / D converter 14 is output (step S52 ). In particular, the test signal generation module extracts 121 one or more test bit patterns to be tested from the pattern table 111 referring to values of the first latch array and the second latch array and selects the first test bit pattern of the extracted test bit pattern.

Here, the switching of a value with respect to bits is recorded in which the corresponding value of the first latch array changes from the initial value 1 to zero and the corresponding value of the second latch array changes from the initial value zero to 1. Thus, test bit patterns to be tested are test bit patterns for testing the switching of bits other than the bits whose change in value has already been detected. In other words, the test bit patterns to be tested are obtained by using test bit patterns to test the previously diagnosed bits from the pattern table 111 be excluded. For example, if the lower 2 bits are using the pattern table of 5B diagnosed, a test using the first test bit pattern can be omitted. In this case, the test signal generation module extracts 121 the second bit pattern and the third bit pattern. Such extraction of test bit patterns is accomplished by extracting test bit patterns that cause each of the undiagnosed bits to assume a value of 1 and test bit patterns that cause each of the undiagnosed bits to assume a value of zero. Since the diagnosed bits only have to assume a value of 1 or zero, test bit patterns which cause values of both 1 and zero to be output for the diagnosed bits are not adopted.

After the step S52 guides the signal processing device 10th steps similar to the steps S4 - S10 of embodiment 1. The "last test bit pattern" in step S6 is the last test bit pattern in step S52 extracted test bit pattern. The "next test bit pattern" in step S7 is the next bit pattern in the sequential selection of the in step S52 extracted bit patterns in the order of the smallest number bit pattern.

As described above, the determiner determines 15 whether values of bits in that of the A / D converter 14 output digital signal are included to switch based on both an analog test signal and a non-test signal. The test signal feeder also generates 12th analog test signals after test bit patterns have been excluded, based on the determination by the determiner 15 based on the non-test signal need not be used. If the non-test signal contains a value that corresponds to a test bit pattern of the pattern table, the test signal feeder fails to generate an analog test signal based on the test bit pattern. In other words, the test signal feeder omits 12th supplying an analog test signal corresponding to a test bit pattern of a plurality of test bit patterns when switching values of all the bits to be tested by the test bit pattern can be detected based on a determination using a non-test signal, thereby shortening a time for performing the test processing is enabled.

In the present embodiment, an extraction of some of the test bit patterns from the pattern table 111 achieved with reference to a flag. Such an extraction of certain test bit patterns from the pattern table 111 can be achieved, for example, by recording a non-test signal and excluding a test bit pattern corresponding to the recorded non-test signal.

Embodiment 6

Next, Embodiment 6 will be described with a focus on differences from Embodiment 1 described above. Components that have the same or corresponding configurations as those in Embodiment 1 are given the same reference numerals. As in 13 shown, a signal processing device differs 10th according to the present embodiment from embodiment 1 in that it includes two A / D converters.

In the above-described embodiment 1 is a test circuit which is the test signal feeder 12th and the determiner 15 contains, arranged for an A / D converter. However, a test circuit that is provided for common use by a plurality of A / D converters can be arranged to efficiently perform the operation test with a compact configuration. An example of the arrangement of a test circuit for two A / D converters is described below.

The signal processing device 10th includes an input port 103 to the one Signal is entered from the outside, an output connector 104 to output a signal to the outside and an A / D converter 142 which serves as an A / D converter unit.

The input port 103 is the input port 101 equivalent and the output connector 104 is the output connector 102 equivalent to. Thus, a 2-channel analog signal is input to the signal processing device 10th entered and the signal processing device 10th outputs a 2-channel digital signal.

The selector 13 selects one in the A / D converter 142 Signal to be entered from an analog test signal or from the input connector 103 input signal and passes the selected signal to the A / D converter 142 to.

The A / D converter 142 outputs a digital signal obtained by converting the input signal to the output terminal 104 and the determiner 15 out. Test operations for each of the A / D converters 14 and 142 can be done separately. In such a case, the selector chooses 13 the A / D converter 14 or the A / D converter 142 and delivers an analog test signal to the selected A / D converter. The test signal feeder 12th supposed to be the A / D converter 14 and the A / D converter 142 supply an analog test signal by setting a supply target of the analog test signal between the A / D converter 14 and the A / D converter 142 toggles. This is the operational test of the A / D converter 142 executed at a time different from the time when the operation test of the A / D converter 14 is performed. On the other hand, the test operations for each of the A / D converters 14 and 142 run at the same time. In such a case, the determiner performs 15 the two tests in parallel. When the two tests are performed in parallel, the first latch array and the second latch array are used to diagnose an output from the A / D converter 14 are used, and a third latch array and a fourth latch array are used to diagnose an output from the A / D converter 142 used.

The output device 16 has a configuration similar to that of Embodiment 1. The output device 16 according to the present embodiment, can output information indicating which of the A / D converters 14 and 142 fails.

The signal processing device 10th contains the A / D converter 14 and 142 , as described above, and it is determined whether values of bits contained in a digital signal output by these converters are set. Such a configuration enables the detection of an error, regardless of which of the two A / D converters 14 and 142 fails.

Although in the present embodiment, a case of arranging two A / D converters 14 and 142 , the detection of an error can be achieved in the same manner as in the present embodiment in a case of arranging three or more A / D converters.

Embodiment 7

Next, Embodiment 7 will be described with a focus on differences from Embodiment 1 described above. Components that have the same or corresponding configurations as those in Embodiment 1 are given the same reference numerals. A signal processing device 10th according to the present embodiment uses a pattern table 111 of 14 which differentiates the present embodiment from the embodiment 1.

The above embodiment 1 describes an example of testing whether switching a bit value of one of the A / D converter 14 output digital signal occurs by testing each bit separately to detect an error. Failures of an A / D converter, however, involve an error in which a value of a particular output bit changes simultaneously with a change in the values of bits adjacent to the particular bit. Thus, a configuration that enables detection of such an error further improves the detection accuracy of an A / D converter failure. An example of detecting an error in which a value of one bit changes simultaneously with a change of a value of another bit is specifically described below.

As in 14 shown, contain test bit patterns in a pattern table 111 according to the present embodiment, each contain a bit with a value that differs from the values of other bits of the corresponding bit pattern. When performing an operation test of the A / D converter 14 using the pattern table 111 generates the test signal feeder 12th analog test signals, each of which is successively shifted to the corresponding test bit pattern in an order in which a position of a bit that has a different value than the other bits corresponds to the adjacent digit. The example in 14 describes a case of generating analog test signals so that the number of a bit, which is the only bit with the value 1 in the corresponding bit pattern, rises successively from the least significant bit to the adjacent number. Then the digit of a bit, which is the only bit, shifts that has the value zero in the corresponding bit pattern, successively from the least significant bit to the adjacent digit.

Next, the signal processing device 10th performed test processing with reference to FIG 15 described. The test processing includes processes similar to those in the steps S1 - S8 of 3rd according to the embodiment. A flag used in the test processing contains flag data, in addition to the first latch array and the second latch array, which indicate whether switching of values of certain bits affected by changes in the values of the other bits occurs. The flag data can be implemented in hardware by a latch circuit or as a flag field in software.

In step S5 updates the signal processing device 10th a flag that contains flag data. In particular, the determiner determines 15 every time step S5 is executed whether one from the pattern table 111 selected test bit pattern is equal to one from the A / D converter 14 output digital signal. If these values differ from each other, the determiner updates 15 the flag data by adding, as data indicating an error in which a value of one bit changes simultaneously with a change of a value of another bit, data indicating a position of a bit of the selected pattern table 111 Show the only digit with a value of 1 or zero below that from the sample table 111 selected test bit pattern, and a position of a bit with the same value as that of the single digit with a value of 1 or zero of the selected test bit pattern.

If the determination in step S8 is positive (yes in step S8 ), determines the signal processing device 10th whether a change in a value of one bit occurs in connection with a change in a value of another bit (step S71 ). In particular, the determiner relates 15 on the flag data and determines whether the flag data contains data indicating an error in which a value of one bit changes along with a change in a value of another bit.

When determining that a change in value of one bit associated with a change in value of another bit does not occur (No in step S71 ), the processing goes through the signal processing device 10th to step S9 about. On the other hand, if it is determined that a change in a value of one bit occurs along with a change in a value of another bit (Yes in step S71 ), gives the signal processing device 10th an error signal (step S10 ). The one in step S10 after a positive determination in step S71 Output information contains information related to an error in which a value of one bit changes simultaneously with a change in a value of another bit. The information related to the error may include information indicating the occurrence of the error and a position of a bit that changes along with a change in a value of another bit.

As described above, the signal processing device enables 10th the detection of an error in which there is a value of a particular bit of bits contained in a digital signal from the A / D converter 14 is included, along with a change in a value of another bit changes, in addition to the detection of an error in certain bits to fix. Such an error can be caused, for example, by crosstalk noise.

For example, one of the A / D converters 14 output digital signal have a malfunction, so that a value of the second least significant bit always becomes equal to a value of the least significant bit. If such an error occurs, the selection of the first test bit pattern results when using the pattern table 111 of 2nd , to output a digital signal with a value of "11 ... 11" from the A / D converter 14 and selecting the second test bit pattern to output a digital signal with a value of "00 ... 00" from the A / D converter 14 . Thus, the detection of an error in which a value of one bit changes simultaneously with a change of a value of another bit cannot be achieved.

On the other hand, the use of the pattern table allows 111 according to the present embodiment, detecting an error in which a value of certain bits changes concurrently with a change in the values of bits adjacent to the specific bit, in addition to detecting an error in which certain bits are fixed. This enables an improvement in the detection rate of an error occurring in the A / D converter 14 occurs.

Although the present embodiment describes a case of generating analog test signals so that one Position of a bit that is the only bit that has a value of zero or 1 in the corresponding bit pattern, successively shifts to the adjacent digit, analog test signals can be generated, for example, such that a position of a bit that has the only bit a value of zero or 1 in the corresponding bit pattern, is successively shifted down to the adjacent digit. That is, the test signal feeder 12th only need analog test signals to the A / D converter 14 so that a position of a bit, which is the only bit with a value of 1 or zero in the corresponding test bit pattern, shifts between these successive bit patterns one by one.

Embodiment 8

Next, Embodiment 8 will be described with a focus on differences from Embodiment 1 described above. The same or corresponding configurations as those in the embodiment 1 are denoted by the same reference numerals. As in 16 shown comprises a signal processing device 30th according to the present embodiment, a D / A converter, and performs an operational test of the D / A converter that detects the present embodiment from the signal processing device 10th differs according to embodiment 1.

Embodiment 1 described above enables detection of an error in which certain values of bits contained in a digital signal output from an A / D converter are fixed. On the other hand, a D / A converter may have an error in which changes in the values of bits contained in a digital signal input to the D / A converter do not affect an output value because an input value is set to 1 or zero and the digital signal is not recognized correctly. An example of detection of an error in which the value of the bit contained in the digital signal input to the D / A converter is set is described below.

The signal processing device 30th includes a D / A converter that converts a digital signal to an analog signal and outputs the analog signal that has a function of outputting an analog signal to the outside by converting a digital signal input from the outside by the D / A converter is provided. Furthermore, the signal processing device 30th performs an operation test of the D / A converter by monitoring a value output from the D / A converter after a test signal is supplied to the D / A converter, and thus a function for accurately detecting an error of the D / A Converter if the D / A converter fails.

The signal processing device 30th includes an input port 301 , into which a digital signal is input from the outside, an output terminal 302 to output an analog signal to the outside, a memory 31 which stores various data, a test signal feeder 32 which generates a digital test signal which is used to test the operation of the D / A converter 34 is used and the digital test signal to the D / A converter 34 feeds the D / A converter 34 that serves as a D / A converter, an A / D converter 35 which has an A / D conversion on one of the D / A converter 34 output analog signal performs a determiner 36 , which determines whether the D / A converter 34 fails, and an output device 37 that outputs information indicating an error of the D / A converter 34 Show. Although this does not limit the present disclosure, the D / A converter functions 34 as a D / A converter in the claims.

The input port 301 is a connector for parallel input of values of bits of a 1-channel digital signal. The input port 301 is connected, for example, to a sensor or device that outputs a digital signal. For example, a 16-bit digital signal that indicates an integer that falls in the range of -32,768 to +32,767 is inserted into the input port 301 entered.

The output connector 302 is a connector for outputting a 1-channel analog signal. An actuator or device used by the signal processing device 30th Output signals used is with the output connector 302 connected. The output connector 302 outputs, for example, a DC voltage falling in a range from -10 V to +10 V as an analog signal.

The memory 31 has a similar configuration as the memory 11 according to embodiment 1 and stores a pattern table 311 that of the pattern table 111 is similar according to embodiment 1.

The test signal feeder 32 reads the test bit pattern of the pattern table one after the other 311 from memory 31 and sends the read test bit patterns as digital test signals to the selector 33 out.

The selector 33 contains a switching device. The selector 33 selects a signal that consists of a digital test signal or an analog signal from the input connector 301 into the D / A converter 34 is to be entered and passes the selected signal to the D / A converter 34 to. One from the selector 33 as a signal selected from a digital test signal is suitably expressed as a non-test signal.

The D / A converter 34 is a so-called D / A converter circuit. The D / A converter 34 outputs to the output connector 302 and the A / D converter 35 an analog signal obtained by converting the supplied digital signal. The A / D converter 35 is a so-called A / D converter circuit. The A / D converter 35 converts from D / A converter 34 output analog signal in a digital signal and gives the digital signal to the determiner 36 out.

The determiner 36 has the same configuration as the determiner 15 according to embodiment 1, and the output device 37 has the same configuration as the output device 16 according to embodiment 1.

The determiner 36 contains a microprocessor unit (MPU) and has the same configuration as the determiner 15 according to embodiment 1. In particular, the determiner determines 36 whether values of bits contained in the digital signal by converting the digital test signal by the D / A converter 34 and the A / D converter 35 is obtained and from the A / D converter 35 output, switch. More specifically, in order to determine whether an error occurs in which a value of a bit is set, the determiner determines 36 for each bit of a plurality of bits of the digital signal to be tested, whether a value of the bit differs before or after the value of the digital test signal. Similar to Embodiment 1, the determiner updates 36 a value of the first latch array using a result of an AND operation between one of the A / D converter 35 output value and the value of the first latch array and updates a value of the second latch array using a result of an OR operation between that of the A / D converter 35 output value and the value of the second latch array, which enables the detection of the presence or absence of an error.

The output device 37 has the same configuration as the output device 16 according to embodiment 1. If the determiner 36 determines that an error occurs in which a value of a bit is set, outputs the output device 16 Information from an error of the D / A converter 34 Show. This information can be data indicating the details of the fault and can be output as a light up of the LED or a warning tone of the buzzer.

The control 38 contains an MPU, ROM and RAM. The control 38 centrally controls each component of the signal processing device 30th .

As described above, the signal processing device provides 30th a digital test signal to the D / A converter 34 and determines whether the D / A converter 34 correctly recognizes the digital test signal. In particular, the detection of an error of the D / A converter 34 by monitoring one of the A / D converter 35 output value and by determining whether values of bits in the signal input to the D / A converter 34 entered and processed by this, are included, to be switched.

Here the detection of an error of the D / A converter 34 can be achieved if the A / D converter 35 works normally. However, if the A / D converter 35 fails, it is difficult to fail the A / D converter 35 from the failure of the D / A converter 34 to distinguish. This allows monitoring of one of the D / A converter 34 output and into the A / D converter 35 input analog signal are performed to determine whether the D / A converter 34 or the A / D converter 35 fails.

Although Embodiments 2-7 describe modified examples of A / D converter failure detection according to Embodiment 1, D / A converter failure detection according to the present embodiment may be modified as described in Embodiments 2-7 will. For example, in the case of a modification as in the embodiment 3rd an offset value can be corrected such that the difference between that in the memory 11 stored test bit pattern and one from the A / D converter 35 output value becomes small.

While embodiments according to the present disclosure have been described above, the present disclosure is not limited to the embodiments described above.

For example, such a configuration is not restrictive, although each of the signal processing devices 10th and 30th simply converts an input signal and outputs the converted signal in the embodiments described above. As in 17th shown, the signal processing device 10th for example a signal processor 191 included, the signal processing at one of the input port 101 inputted signal and a result of the processing as a non-test signal to the selector 13 outputs, and a signal processor 192 which has a signal processing on one of the A / D converter 14 output signal performs and a result of processing to the output terminal 102 issues. Either the signal processor 191 or the signal processor 192 can in the signal processing device 10th be omitted. Similarly, the signal processing device 30th contain a signal processor.

As in 18th shown, the signal processing device 10th instead of the input connector 101 and the output connector 102 a signal source that generates a non-test signal and an output device 194 included, the information based on an output from the A / D converter 14 issues. Similarly, the signal processing device 30th a signal source and an output device containing information based on an output from the D / A converter 34 issues.

Although the embodiments described above describe cases in which the width of those in the pattern table 111 contained test bit pattern equal to the width of the bit one from the A / D converter 14 output digital signal, they also describe cases where the width of the in the pattern table 311 contained test bit pattern equal to the width of the bit one in the D / A converter 34 input digital signal. Another configuration can be used. The width of the in the stores 11 and 31 stored test bit pattern can be equal to the width of the bits to be tested of a digital signal that is input or output. For example, if the lower 8 bits are to be tested, the width of the test bit pattern can be 8 bits.

In addition, dedicated hardware or an ordinary computer system can also perform the functions of the signal processing devices 10th and 30th fulfill.

For example, by distributing one of the controls 17th and 38 program to be executed can be obtained by storing the program on a computer readable recording medium and installing the program on a computer, a device for performing the processing described above.

In addition, the program can be stored on a disk device of a server device in a communication network such as the Internet, for example superimposed on a carrier wave and downloaded to a computer.

Furthermore, the processing described above can also be achieved by starting and executing the program while the program is being transmitted via the communication network.

Furthermore, the processing described above can also be accomplished by causing all or part of the program to run on the server device and executing the program while the computer is sending and receiving processing information over the communication network.

For example, in the case where the functions described above are implemented by an operating system (OS) or are implemented through cooperation between the operating system and an application, the distribution of only a part other than the operating system may be permitted, by a part on a medium saved or downloaded to a computer.

The means for achieving the functions of the signal processing devices 10th and 30th is not limited to software, and dedicated hardware, including circuitry, can accomplish some or all of the functions.

The foregoing describes some example embodiments for illustrative purposes. Although the above discussion has presented specific embodiments, those skilled in the art will recognize that changes in form and detail can be made without departing from the broader spirit and scope of the invention. Accordingly, the description and drawings are illustrative rather than restrictive. This detailed description is, therefore, not to be taken in a limiting sense, and the scope of the invention is defined only by the appended claims, along with the full range of equivalents to which such claims are entitled.

Industrial applicability

The present disclosure is useful for detecting a converter failure.

Reference list

10.30

Signal processing device

11, 31

Storage

111, 311

Sample table

112

Digital data elements

12.32

Test signal feeder

122

Addition module

121, 321

Test signal generation module

13.33

Selection module

14,142.35

A / D converter

15.36

Determiner

16.37

Output device

17.38

control

18th

Adjuster

19th

timer

34

D / A converter

101

Input connector

102

Output connector

103

Input connector

104

Output connector

191, 192

Signal processor

193

Signal source

194

Output device

301

Input connector

302

Output connector

QUOTES INCLUDE IN THE DESCRIPTION

This list of documents listed by the applicant has been generated automatically and is only included for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Patent literature cited

• JP 2007285764 [0004]
• JP H856160 [0004]

Claims (11)

A signal processing device comprising: A / D converting means for converting an analog signal into a digital signal and outputting the digital signal; supply means for supplying an analog test signal corresponding to a test bit pattern to the A / D converting means; determining means for determining when a level of the analog test signal supplied to the A / D converting means switches whether a value of a bit of the digital signal output from the A / D converting means to be tested after switching the level of the analog test signal toggles; and an output means for outputting a result of the determination by the determination means. Signal processing device according to Claim 1 wherein the feeding means comprises: storage means for storing a plurality of predetermined digital data items; and an adding means for adding an offset value to the plurality of digital data items stored in the storage means to obtain a plurality of the test bit patterns, and wherein the supplying means supplies the A / D converting means a plurality of the analog test signals each corresponding to the one Test bit pattern obtained by the addition means correspond. Signal processing device according to Claim 2 , further comprising setting means for setting the offset value so that a difference between the test bit pattern output from the addition means and the digital signal output from the A / D conversion means becomes small. Signal processing device according to Claim 1 wherein the test bit pattern is a plurality of bit patterns, each of the plurality of bit patterns containing a bit with a value different from the values of other bits of the corresponding bit pattern, and wherein the supplying means to the A / D converting means are a plurality of analog test signals feeds, each corresponding to the corresponding test bit pattern, so that a position between successive bit patterns is shifted by one. Signal processing device according to one of the Claims 1 to 4th , wherein the feed means feeds the analog test signal periodically. Signal processing device according to Claim 5 , the determining means determines whether a value of the bit of a digital signal to be tested, which is obtained by converting a non-test signal and output from the A / D converting means, switches after changing a level of the non-test signal, the non- Test signal is different from the analog test signal, and wherein the feed means omits the next generation of the analog test signal when the determining means determines, based on the non-test signal, that the value of the bit under test switches. Signal processing device according to one of the Claims 1 to 4th , the determining means determines whether a value of the bit of a digital signal to be tested, which is obtained by converting a non-test signal and output from the A / D converting means, switches after changing a level of the non-test signal, the non- Test signal is different from the analog test signal, and wherein the supply means omits the supply of the analog test signal corresponding to a test bit pattern from the plurality of test bit patterns when switching all bits to be tested by the one test bit pattern by a determination based on the non-test signal is confirmed. Signal processing device according to one of the Claims 1 to 7 , further comprising: another A / D converting means for converting an analog signal into a digital signal and outputting the digital signal, the supplying means supplying the analog test signal of the A / D converting means and the other A / D converting means by a supply target of the analog test signal is switched between the A / D converting means and the other A / D converting means. A signal processing apparatus comprising: D / A converting means for converting a digital signal into an analog signal and outputting the analog signal; A / D converting means for converting the analog signal output from the D / A converting means into a digital signal; supply means for supplying a digital test signal to the D / A converting means while changing a value of the digital test signal; determining means for determining whether a value of each bit of a plurality of bits of a digital signal to be tested switches after the supply means switches a value of the digital test signal, the digital signal by converting the digital test signal by the D / A converting means and the A / D converting means obtained and outputted by the A / D converting means; and an output means for outputting as a test result of a result of the determination by the determination means. An operational test method for testing the operation of A / D converting means for converting an analog signal into a digital signal and outputting the digital signal, the method comprising the steps of: Supplying an analog test signal to the A / D converting means while changing a level of the analog test signal; and Determining whether a value of each bit of a plurality of bits of a digital signal to be tested switches after changing the level of the analog test signal, the digital signal obtained by converting the analog test signal and output from the A / D converting means. Operating test method for testing the operation of D / A converting means for converting a digital signal into an analog signal and for outputting the analog signal, the method comprising the following steps: Supplying a digital test signal to the D / A converting means while changing a value of the digital test signal; and Determining whether a value of each bit of a plurality of bits of a digital signal to be tested switches after changing the value of the digital test signal, the digital signal being output from the A / D converting means after the A / D converting means is converted of the digital test signal obtained and output from the D / A converting means converted analog signal into the digital signal.

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