JP2007201494A - Nonvolatile semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To simultaneously achieve a transistor in a low-voltage circuit region having a high function, and a transistor in a high-voltage circuit region resistant to high voltage and highly integrated. <P>SOLUTION: This nonvolatile semiconductor storage device is provided with a cell array region 120 having a word line formed of a metal salicide film, the high-voltage circuit region 90 including a transistor provided with a main electrode and a control electrode disposed at the periphery and electrically contacted or insulated in a part of the metal salicide film, and the low-voltage circuit region 80 disposed at peripheries of the cell array region and the high voltage circuit region and including the transistor provided with the main electrode and the control electrode formed of the metal salicide film, wherein the memory cell transistor is provided with a stack gate type structure, and each transistor in the high voltage circuit region and the low voltage circuit region each has a gate structure or a stack gate type structure made of a single layer and has a wiring region in contact with the metal salicide film and an electrically insulated resistance element region. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device characterized in that a metal salicide film is structurally applied as an electrode film.

  Conventionally, as a nonvolatile semiconductor memory device, for example, a programmable read-only memory (EEPROM) that electrically writes and erases data is known (Non-Patent Document 1). In this EEPROM, in particular, in the case of the NAND type, a memory cell array is configured by disposing memory cells at the intersections between the word lines in the row direction and the bit lines in the column direction that intersect each other. As the memory cell, for example, a MOS transistor having a stacked gate structure in which a floating gate and a control gate are stacked is usually used.

As shown in Non-Patent Document 1, a NAND flash memory has a structure in which a plurality of memory cell transistors are connected in series to form a NAND string, and selection transistors are arranged on both sides of the NAND string. Have In addition, an element isolation region is arranged in parallel to the element active region of the memory cell to constitute a memory cell array. In general, the gate length of the selection transistor is longer than the gate length of the memory cell transistor, and the deterioration of the cutoff characteristics of the transistor due to the short channel effect is ensured. The selection transistor is usually composed of an enhancement type MOS transistor.

In a nonvolatile semiconductor memory device using a memory cell composed of two transistors, a memory transistor and a select transistor, a configuration in which the gate oxide film thicknesses of the memory transistor portion and the select transistor portion are different from each other has already been disclosed ( Patent Document 1).

Further, a configuration in which the gate oxide film of the selection MOS transistor formed by the gate electrode and the gate oxide film of the MOS transistor of the peripheral circuit are different from each other has already been disclosed (Patent Document 2).

In the nonvolatile semiconductor memory device having a floating gate in the charge storage layer, the peripheral transistor is formed by using a salicide process, and the memory cell portion is not salicided in the diffusion layer, and only the control gate is salicided. A structure of a flash memory having a structure and a manufacturing method have also been proposed (Patent Document 3).
JP 2000-269361 A Japanese Patent Laid-Open No. 04-165670 JP 2003-60092 A Riichiro Shirata, "A Review of 256Mbit NAND Flash Memories and NAND Flash Future Trend", Non-Volatile Semiconductor Memory Workshop (NVSMW), 2000, P.22- 31

In a conventional nonvolatile semiconductor memory device such as a flash EEPROM, a high voltage circuit region is necessary to supply high voltage pulses such as a write voltage, an intermediate voltage, and an erase voltage to the memory cell array region. On the other hand, there is also a low voltage circuit area that requires normal low voltage and high speed performance.

However, in the low voltage circuit region, it is more advantageous to use a transistor having a higher speed performance by increasing the driving capability of the transistor. In particular, in a low-voltage circuit area of a flash EEPROM capable of operating at a low power supply voltage, it becomes a problem to ensure the driving capability of the transistor. On the other hand, as the capacity of the memory cell array increases, it is an important issue to improve the writing speed and the reading speed by lowering the resistance of the word line in the memory cell region.

In the low voltage circuit area, it is necessary to increase the driving capability and obtain a transistor having higher speed performance. In a large-capacity memory cell array, forming a metal salicide film on the gate or diffusion layer is one method for reducing the resistance of the word line in the memory cell region and improving the writing speed and reading speed. .

However, in a nonvolatile semiconductor memory device such as a flash EEPROM, as with CMOS logic, when a metal salicide film is formed on the gate and diffusion layers in the entire circuit region, a high voltage of 15 V or more such as a write voltage V _pgm and an erase voltage V _erase In a transistor in a high voltage circuit region arranged to generate a voltage, it becomes a problem to avoid an increase in junction leakage and deterioration of junction breakdown voltage and surface breakdown voltage.

  In particular, the NAND type requires a higher voltage than AND and NOR, so that the problems of junction leakage and junction breakdown voltage become significant.

  An object of the present invention is to provide a nonvolatile semiconductor memory device that simultaneously realizes higher functionality of transistors in a low voltage circuit region and higher breakdown voltage and higher integration of transistors in a high voltage circuit region.

According to one aspect of the present invention, (b) a cell array region including a memory cell transistor including a first control gate electrode and a floating gate electrode adjacent to the first control gate electrode; A first source region and a drain region comprising a diffusion layer having an impurity density and a low impurity density diffusion layer disposed at both ends of the diffusion layer having a high impurity density, and disposed between the first source region and the drain region. A high-voltage circuit region including a high-voltage transistor including a first gate region and an insulating film covering a side wall and an upper surface of the first gate region; (c) a second source region and a drain region; A low-voltage circuit region including a low-voltage transistor including a second gate region disposed between the second source region and the drain region on a semiconductor chip; The insulating film covering the side wall and the upper surface of the first gate region is also disposed on the first source region and the drain region, and the first control gate electrode, the second source region and the drain region, and The second gate region is silicided, and the first gate region from which a part of the insulating film covering the side wall and the upper surface of the first gate region is removed is silicided, or the first gate region There is provided a nonvolatile semiconductor memory device in which the high impurity density diffusion layer in the first source region and drain region from which a part of the insulating film covering one source region and drain region is removed is silicided. .

  According to another aspect of the present invention, (a) a cell array region comprising memory cell transistors comprising a first control gate electrode and a floating gate electrode adjacent to the first control gate electrode; A first source region and a drain region each including a high impurity density diffusion layer and a low impurity density diffusion layer disposed on both ends of the high impurity density diffusion layer, and the first source region and the drain region are disposed between the first source region and the drain region. A high-voltage circuit region including a high-voltage transistor including a first gate region to be formed and an insulating film covering a side wall portion and an upper surface of the first gate region; and (c) a second source region and a drain region. A low-voltage circuit region including a low-voltage transistor including a second gate region disposed between the second source region and the drain region on the semiconductor chip; The insulating film covering the side wall and the upper surface of the first gate region is also disposed on the first source region and the drain region, and the first control gate electrode, the second source region and the drain region, And the second gate region is silicided, and the first gate region from which a part of the insulating film covering the side wall and the upper surface of the first gate region is removed is silicided, and Provided is a nonvolatile semiconductor memory device in which the high impurity density diffusion layer in the first source region and drain region from which a part of the insulating film covering the first source region and drain region is removed is silicided. The

  According to another aspect of the present invention, (a) a floating gate electrode, an insulating layer disposed on the floating gate electrode, and a first control stacked on the floating gate electrode via the insulating layer A cell array region comprising a memory cell transistor comprising a gate electrode; and (b) a first source comprising a high impurity density diffusion layer and a low impurity density diffusion layer disposed at each end of the high impurity density diffusion layer. A high-voltage transistor including a region and a drain region, a first gate region disposed between the first source region and the drain region, and an insulating film covering a side wall and an upper surface of the first gate region A low-voltage transistor comprising: a high-voltage circuit region; (c) a second source region and a drain region; and a second gate region disposed between the second source region and the drain region. A low-voltage circuit region including a capacitor on a semiconductor chip, and each of the first gate region and the second gate region is a single layer, and (2) a sidewall portion and an upper surface of the first gate region The insulating film covering the first source region and the drain region is also disposed, and the first control gate electrode, the second source region and the drain region, and the second gate region are silicided. And the first gate region from which a part of the insulating film covering the side wall and the upper surface of the first gate region is removed is silicided or the first source region and the drain region are covered. There is provided a nonvolatile semiconductor memory device in which the high impurity density diffusion layers in the first source region and the drain region from which a part of the insulating film is removed are silicided.

  According to another aspect of the present invention, (a) a floating gate electrode, an insulating layer disposed on the floating gate electrode, and a first control stacked on the floating gate electrode via the insulating layer A cell array region comprising a memory cell transistor comprising a gate electrode; and (b) a first source comprising a high impurity density diffusion layer and a low impurity density diffusion layer disposed at each end of the high impurity density diffusion layer. A high-voltage transistor including a region and a drain region, a first gate region disposed between the first source region and the drain region, and an insulating film covering a side wall and an upper surface of the first gate region A low-voltage transistor comprising: a high-voltage circuit region; (c) a second source region and a drain region; and a second gate region disposed between the second source region and the drain region. A low-voltage circuit region including a capacitor on a semiconductor chip, and each of the first gate region and the second gate region is a single layer, and (2) a sidewall portion and an upper surface of the first gate region The insulating film covering the first source region and the drain region is also disposed, and the first control gate electrode, the second source region and the drain region, and the second gate region are silicided. And the first gate region from which a part of the insulating film covering the side wall and the upper surface of the first gate region is removed is silicided and covers the first source region and the drain region. There is provided a nonvolatile semiconductor memory device in which the high impurity density diffusion layers in the first source region and the drain region from which a part of the insulating film is removed are silicided.

  According to another aspect of the present invention, (a) a floating gate electrode, an insulating layer disposed on the floating gate electrode, and a first control stacked on the floating gate electrode via the insulating layer A cell array region comprising a memory cell transistor comprising a gate electrode; and (b) a first source comprising a high impurity density diffusion layer and a low impurity density diffusion layer disposed at each end of the high impurity density diffusion layer. A first gate region disposed between the first source region and the drain region; a second control gate electrode disposed on the first gate region; and the first gate region disposed on the first gate region; A high-voltage circuit region including a high-voltage transistor including a gate region, a sidewall of the second control gate electrode, and an insulating film covering an upper surface of the second control gate electrode; and (c) a second source A low voltage transistor comprising: a region and a drain region; a second gate region disposed between the second source region and the drain region; and a third control gate electrode disposed on the second gate region. And (2) the first control gate electrode, the second source region and the drain region, and the third control gate electrode are silicided, and the low-voltage circuit region is included on the semiconductor chip. The second control gate electrode from which a part of the insulating film covering the upper surface of the second control gate electrode has been removed is silicided, or a part of the insulating film covering the first source region and the drain region is formed. There is provided a nonvolatile semiconductor memory device in which the high impurity density diffusion layers of the removed first source region and drain region are silicided.

  According to another aspect of the present invention, (a) a floating gate electrode, an insulating layer disposed on the floating gate electrode, and a first control stacked on the floating gate electrode via the insulating layer A cell array region comprising a memory cell transistor comprising a gate electrode; and (b) a first source comprising a high impurity density diffusion layer and a low impurity density diffusion layer disposed at each end of the high impurity density diffusion layer. A first gate region disposed between the first source region and the drain region; a second control gate electrode disposed on the first gate region; and the first gate region disposed on the first gate region; A high-voltage circuit region including a high-voltage transistor including a gate region, a sidewall of the second control gate electrode, and an insulating film covering an upper surface of the second control gate electrode; and (c) a second source A low voltage transistor comprising: a region and a drain region; a second gate region disposed between the second source region and the drain region; and a third control gate electrode disposed on the second gate region. And (2) the first control gate electrode, the second source region and the drain region, and the third control gate electrode are silicided, and the low-voltage circuit region is included on the semiconductor chip. The second control gate electrode from which a part of the insulating film covering the upper surface of the second control gate electrode is removed is silicided, and a part of the insulating film covering the first source region and the drain region is formed. There is provided a nonvolatile semiconductor memory device in which the high impurity density diffusion layers of the removed first source region and drain region are silicided.

According to the present invention, the functions of the transistors in the low voltage circuit region disposed in the peripheral portion of the memory cell array region are enhanced, and the transistors in the high voltage circuit region disposed in the peripheral portion of the memory cell array region are also increased in breakdown voltage. It is possible to provide a nonvolatile semiconductor memory device capable of realizing integration at the same time.

  Next, first to fourth embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

  Further, the following first to fourth embodiments exemplify apparatuses and methods for embodying the technical idea of the present invention, and the technical idea of the present invention includes components. The material, shape, structure, arrangement, etc. are not specified below. The technical idea of the present invention can be variously modified within the scope of the claims.

(First embodiment)
-Whole plane pattern block configuration-
A schematic block configuration of the nonvolatile semiconductor memory device according to the first embodiment of the invention includes, for example, a cell array region 120 arranged on a semiconductor chip 150 and a high voltage circuit region 90 as shown in FIG. And a low-voltage circuit region 80 and another circuit region 100 composed of a mixture of a low-voltage circuit, a high-voltage circuit, and a resistance element region. The high voltage circuit region 90 is a circuit for applying a voltage pulse relatively higher than the power supply voltage such as the write voltage V _pgm and the erase voltage V _erase to the cell array region 120. The low voltage circuit region 80 is a logic circuit such as a CMOS, and is a circuit region that requires relatively high speed and low power consumption performance. In the other circuit region 100, a low voltage circuit other than the circuits set in the low voltage circuit region 80 and the high voltage circuit region 90, a high voltage circuit, a resistance element region for generating a reference voltage, and the like are arranged. .

  In the nonvolatile semiconductor memory device according to the first embodiment of the present invention, the cell array region 120, the high voltage circuit region 90, and the low voltage circuit region 80 are particularly related. Further, a low voltage circuit, a high voltage circuit, a resistance element region for generating a reference voltage and the like in the cell array region 120 and other circuit regions 100 are also related. Furthermore, the cell array region 120, the high voltage circuit region 90, the low voltage circuit region 80, and the wiring region in the other circuit regions 100 are also related.

―Element structure―
As shown in FIGS. 1 and 6, the nonvolatile semiconductor memory device according to the first embodiment of the present invention is in electrical contact with the first metal salicide film 11 and the first metal salicide film 11. A cell array region 120 formed of a memory cell transistor (FIG. 6D) including the first control gate electrode 7 and the floating gate electrode 4 adjacent to the first control gate electrode 7, and the second metal salicide film 11 And a first source / drain region 24, 25, 26, 27, and a first gate region 74, 73 disposed between the first source / drain region 24, 25, 26, 27. High-voltage circuit regions 90 and 14 including transistors (FIG. 6B), a third metal salicide film 11, a second source / drain region 20 in electrical contact with the third metal salicide film 11, 21, 2, 23 and a second gate region 72, 71 disposed between the second source / drain regions 20, 21, 22, 23 and in electrical contact with the third metal salicide film 11. Low voltage circuit regions 80 and 13 including transistors (FIG. 6A) are provided on the semiconductor chip 150.

  2A to 6A, FIG. 2A illustrates a schematic element cross-sectional structure diagram in the low voltage circuit region 80, FIG. 2B illustrates a schematic element cross-sectional structure diagram in the high voltage circuit region 90, and FIG. 2A and 2B are schematic planar pattern configuration diagrams corresponding to FIG. 2B, and FIG. 2D is a schematic element cross-sectional structure diagram in the corresponding cell array region 120. FIG.

  Similarly, in FIGS. 7 to 9, FIGS. 7A, 8 </ b> A, and 9 </ b> A are schematic element cross-sectional structures of transistors in the low-voltage circuit region 80, and FIG. FIGS. 8B and 9B show schematic element cross-sectional structure diagrams of transistors in the high-voltage circuit region 90. FIGS. 7C, 8C, and 9C are respectively shown in FIGS. A corresponding schematic plane pattern configuration diagram is shown.

  In the nonvolatile semiconductor memory device according to the first embodiment of the present invention, the memory cell transistor has a stack gate structure, but both the transistor in the low voltage circuit region 80 and the transistor in the high voltage circuit region 90 are single layers. The gate structure is provided.

―Memory cell structure―
As shown in FIGS. 2D to 6D, the memory cell transistor of the nonvolatile semiconductor memory device according to the first embodiment of the present invention includes a first electrode film 4 serving as a floating gate electrode, The basic structure is a stack gate structure composed of a seventh insulating film 12 acting as an interlayer insulating film and a second electrode film 7 serving as a first control gate electrode, and a second electrode film The first metal salicide film 11 is in electrical contact with the substrate 7.

  As shown in FIGS. 2D to 6D, the detailed structure of the memory cell transistor of the nonvolatile semiconductor memory device according to the first embodiment of the present invention includes, for example, a semiconductor substrate 1 and a semiconductor substrate. N well region 19 and p well region 17 formed in 1, first insulating film 2 serving as a tunnel insulating film, first electrode film 4 disposed on first insulating film 2, 7, the second electrode film 7, the fourth insulating film 8 disposed on the side wall portion of the stacked gate structure, and the metal salicide that is in electrical contact with the upper portion of the second electrode film 7. A film 11. Since the second electrode film 7 corresponds to the word line, the metal salicide film 11 constitutes the word line. In FIG. 2D to FIG. 6D, descriptions of the source / drain regions, element isolation regions, and the like of the memory cell transistor are omitted.

-Transistor structure in low voltage circuit area-
As shown in FIGS. 2A to 9A, the low-voltage circuit region 80 is formed in, for example, the p-well region 16 and the n-well region 18 formed in the semiconductor substrate 1 and the p-well region 16. An nMOS transistor formed and a pMOS transistor formed in the n-well region 18 are provided. Also, the planar pattern diagrams shown in FIGS. 2 (c) to 9 (c) show the p-well region 16 and n corresponding to the low voltage circuit region 13 shown in FIGS. 2 (a) to 9 (a). A well region 18 is disposed. An nMOS formation region 30 is disposed in the p well region 16 corresponding to the low voltage circuit region 13, and a pMOS formation region 40 is disposed in the n well region 18.

  The transistor structure in the low-voltage circuit regions 80 and 13 of the nonvolatile semiconductor memory device according to the first embodiment of the present invention is the second nMOS transistor as shown in FIGS. 6 (a) to 9 (a). Source / drain regions 20, 21; a first gate region 72 disposed between the second source / drain regions 20, 21; second source / drain regions 22, 23 of the pMOS transistor; The second gate region 71 disposed between the source / drain regions 22 and 23 of the first and second source / drain regions 20, 21, 22, and 23 and the second gate regions 72 and 71 are electrically A third metal salicide film 11 is provided.

The detailed structure of the nMOS transistor in the low-voltage circuit region 13 of the nonvolatile semiconductor memory device according to the first embodiment of the present invention is, for example, as shown in FIG. 6A to FIG. 1, an element isolation region 3, a p-well region 16 formed in the semiconductor substrate 1, a third insulating film 6 serving as a gate insulating film, and a second insulating film 6 disposed on the third insulating film 6. N ⁺ polysilicon gate electrode 72 serving as a gate region, n ⁺ source / drain regions 20 and 21 serving as second source / drain regions, and electric field relaxation arranged adjacent to n ⁺ source / drain regions 20 and 21 An n ⁻ layer 28 serving as a layer, a fourth insulating film 8 disposed on a sidewall of the n ⁺ polysilicon gate electrode 72, the n ⁺ source / drain regions 20 and 21, and the n ⁺ polysilicon gate Electrical contact on electrode 72 And a third metal salicide film 11 disposed Te.

Similarly, the detailed structure of the pMOS transistor in the low voltage circuit region 13 of the nonvolatile semiconductor memory device according to the first embodiment of the present invention is, for example, as shown in FIGS. 6A to 9A. The semiconductor substrate 1, the element isolation region 3, the n-well region 18 formed in the semiconductor substrate 1, the third insulating film 6 serving as a gate insulating film, and the third insulating film 6 are disposed. a p ⁺ polysilicon gate electrode 71 serving as a second gate region, a p ⁺ source and drain regions 22 and 23 serving as a second source-drain region, adjacent to the p ⁺ source and drain regions 22 and 23 located The p ⁻ layer 29 serving as an electric field relaxation layer, the fourth insulating film 8 disposed on the sidewall of the p ⁺ polysilicon gate electrode 71, the p ⁺ source / drain regions 22, 23 and p ⁺ Electricity on the polysilicon gate electrode 71 Contact with the and a third metal salicide film 11 disposed.

-Transistor structure in high voltage circuit area-
As shown in FIGS. 2B to 9B, the high-voltage circuit region 90 includes, for example, a p-well region 16 and an n-well region 18 formed in the semiconductor substrate 1 and the p-well region 16. An nMOS transistor formed and a pMOS transistor formed in the n-well region 18 are provided. The planar pattern diagrams shown in FIGS. 2 (c) to 9 (c) include p-well regions 16 and n corresponding to the high voltage circuit region 14 shown in FIGS. 2 (b) to 9 (b). A well region 18 is disposed. An nMOS formation region 50 is disposed in the p well region 16 corresponding to the high voltage circuit region 14, and a pMOS formation region 60 is disposed in the n well region 18.

  The transistor structure in the high voltage circuit regions 90 and 14 of the nonvolatile semiconductor memory device according to the first embodiment of the present invention is the first nMOS transistor as shown in FIGS. 6B to 9B. Source / drain regions 24, 25, a first gate region 74 disposed between the first source / drain regions 24, 25, first source / drain regions 26, 27 of the pMOS transistor, The first gate region 73 disposed between the source / drain regions 26 and 27, and the first source / drain regions 24, 25, 26 and 27 and the first gate regions 74 and 73 are electrically connected to each other. A second metal salicide film 11 that is insulated or partially in electrical contact is provided.

  The transistor structure in the high-voltage circuit regions 90 and 14 of the nonvolatile semiconductor memory device according to the first embodiment of the present invention is the first source of the nMOS transistor and pMOS transistor as shown in FIG. The second metal salicide film 11 is not electrically contacted with any of the drain regions 24, 25, 26, 27 and the first gate regions 74, 73, and is electrically insulated from the metal salicide film 11. It has a structure.

  Alternatively, as shown in FIG. 7B, the second metal salicide film 11 is in electrical contact with both the first gate regions 74 and 73 of the nMOS transistor and the pMOS transistor.

  Alternatively, as shown in FIG. 8B, the second metal salicide film 11 is brought into electrical contact with any of the first source / drain regions 24, 25, 26, and 27 of the nMOS transistor and the pMOS transistor. Has a structure.

  Alternatively, as shown in FIG. 9B, the metal salicide film 11 is formed on any of the first source / drain regions 24, 25, 26, and 27 and the first gate regions 74 and 73 of the nMOS transistor and the pMOS transistor. Are in electrical contact with each other.

The detailed structure of the nMOS transistor in the high voltage circuit region 14 of the nonvolatile semiconductor memory device according to the first embodiment of the present invention is, for example, as shown in FIG. 3, a p-well region 16 formed in the semiconductor substrate 1, a second insulating film 5 serving as a gate insulating film, and an n ^{+ serving} as a first gate region disposed on the second insulating film 5. responsible polysilicon gate electrode 74, the n ⁺ source and drain regions 24 and 25 serving as the first source-drain region, it is disposed adjacent to the n ⁺ source and drain regions 24 and 25 work as electric field relaxation layer It is deposited on the n ⁻ layer 28, the fourth insulating film 8 disposed on the sidewall of the n ⁺ polysilicon gate electrode 74, the n ⁺ source / drain regions 24 and 25 and the n ⁺ polysilicon gate electrode 74. 5th insulating film 9 Beauty and a dielectric film 10 of the sixth. Of course, the fifth insulating film 9 and the sixth insulating film 10 may be formed as a single insulating film. Alternatively, as shown in FIG. 7B, the second metal salicide film 11 may be in electrical contact with the n ⁺ polysilicon gate electrode 74 of the nMOS transistor. Alternatively, as shown in FIG. 8B, the second metal salicide film 11 may be in electrical contact with the n ⁺ source / drain regions 24 and 25 of the nMOS transistor. Alternatively, as shown in FIG. 9B, the second metal salicide film 11 is brought into electrical contact with both the n ⁺ source / drain regions 24 and 25 and the n ⁺ polysilicon gate electrode 74 of the nMOS transistor. It is good also as a structure.

As shown in FIG. 6B, the detailed structure of the pMOS transistor in the high voltage circuit region 14 of the nonvolatile semiconductor memory device according to the first embodiment of the present invention includes, for example, a semiconductor substrate 1 and an element isolation region. 3, an n well region 18 formed in the semiconductor substrate 1, a second insulating film 5 serving as a gate insulating film, and p ^{+ serving} as a first gate region disposed on the second insulating film 5. responsible polysilicon gate electrode 73, a p ⁺ source and drain regions 26 and 27 serving as the first source-drain region is disposed adjacent to the p ⁺ source and drain regions 26 and 27 work as electric field relaxation layer It is deposited on the p ⁻ layer 29, the fourth insulating film 8 disposed on the sidewall of the p ⁺ polysilicon gate electrode 73, the p ⁺ source / drain regions 26 and 27 and the p ⁺ polysilicon gate electrode 73. 5th insulating film 9 Beauty and a dielectric film 10 of the sixth. Of course, the fifth insulating film 9 and the sixth insulating film 10 may be formed as a single insulating film. Alternatively, as shown in FIG. 7B, the second metal salicide film 11 may be in electrical contact with the p ⁺ polysilicon gate electrode 73 of the pMOS transistor. Alternatively, as shown in FIG. 8B, the second metal salicide film 11 may be in electrical contact with the p ⁺ source / drain regions 26 and 27 of the pMOS transistor. Alternatively, as shown in FIG. 9B, the second metal salicide film 11 is brought into electrical contact with both the p ⁺ source / drain regions 26 and 27 and the p ⁺ polysilicon gate electrode 73 of the pMOS transistor. It is good also as a structure.

-Production method-
A method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment of the present invention will be described with reference to FIGS.

(A) After forming the element isolation region 3 of the transistor in the low voltage circuit region 13 and the transistor in the high voltage circuit region 14, the structure immediately after depositing the first electrode film 4 serving as the floating gate electrode material of the memory cell transistor It is shown in FIGS. 2 (a) to 2 (d).

(B) Next, in the high voltage circuit region 14, using the lithography technique and the etching technique, the seventh insulating film 12 that becomes the interlayer insulating film of the memory cell transistor, and the first that becomes the floating gate electrode material of the memory cell transistor After the electrode film 4 and the first insulating film 2 which is a tunnel oxide film of the memory cell transistor are peeled off, a second insulating film 5 which becomes a gate oxide film of the transistor in the high voltage circuit region 14 is formed, and a low voltage circuit is formed. In the region 13, after the seventh insulating film 12, the first electrode film 4, and the first insulating film 2 are peeled off by using lithography technology and etching technology, the gate oxide film of the transistor in the low voltage circuit region 13 A third insulating film 6 is formed (FIGS. 3A to 3D).

(C) Next, a second electrode film 7 is deposited which becomes the control gate of the memory cell transistor in the cell array region 120, the gate electrode of the transistor in the peripheral low voltage circuit region 13, and the gate electrode of the transistor in the high voltage circuit region 14. Thereafter, the second electrode film 7 is formed by using a lithography technique and an etching technique (FIGS. 4A to 4D).

(D) Next, after depositing the fourth insulating film 8, the gate sidewall structure of the transistor in the peripheral low-voltage circuit region 13 and the gate sidewall structure of the transistor in the high-voltage circuit region 14 are formed using a selective etching technique. After that, a fifth insulating film 9 is deposited on the entire surface to form the structures of FIGS. 5 (a) to 5 (d).

  Selection of the 4th insulating film 8 and the 5th insulating film 9 is an insulating film from which the etching selectivity of the 1st electrode film 4 and the 2nd electrode film 7 is obtained, and the 4th insulating film 8 is This is a salicide suppressing film on the side surface of the gate when the metal salicide film 11 described later is formed. Further, the fifth insulating film 9 is desirably an insulating film that can obtain a selection ratio with respect to the fourth insulating film 8. At this time, the same impurity as that of the diffusion layer is implanted into the second electrode film 7 so that the pMOS transistor becomes p + polysilicon gate electrodes 71 and 73 and the nMOS transistor becomes n + polysilicon gate electrodes 72 and 74. Become.

(E) Next, a sixth insulating film 10 to be a metal salicide suppressing film is deposited, and the fifth insulating film 9 and the sixth insulating film 10 in the low voltage circuit region 13 are formed by using a lithography technique and an etching technique. Remove. Thereafter, through a metal salicide process, the second electrode films 71 and 72 in the low voltage circuit region 13 and the diffusion layers such as the n ⁺ source / drain regions 20 and 21 and the p ⁺ source and drain regions 22 and 23 are applied. A metal salicide film 11 is formed (FIGS. 6A to 6D).

  As a material for forming the metal salicide film, for example, cobalt (Co), nickel (Ni), titanium (Ti), tantalum (Ta), platinum (Pt), molybdenum (Mo), tungsten (W), palladium (Pd A silicide material such as) can be applied.

  Note that the metal salicide film 11 is not formed in the high-voltage circuit region 14 covered with the fifth insulating film 9 and the sixth insulating film 10 (FIG. 6B). The selection of the sixth insulating film 10 is desirably an insulating film that can obtain a selection ratio with respect to the fifth insulating film 9.

Depending on the lithography patterning described in the structure of FIG. 6, only the second electrode films 73 and 74 in the high voltage circuit region 14 (FIG. 7), the n ⁺ source / drain regions 20, 21, 24, 25, p Only a part of the ⁺ source / drain regions 22, 23, 26, 27 (FIG. 8), or p + polysilicon gate electrodes 71, 73, n + polysilicon gate electrodes 72, 74 and n ⁺ source / drain regions 20, 21, 24, 25, p ⁺ source / drain regions 22, 23, 26, 27 can be partially formed (FIG. 9) to form metal salicide film 11.

  The structure of the high voltage circuit region 14 shown in FIGS. 6B, 7B, 8B, and 9B is selected depending on the electric breakdown voltage of the transistors in the high voltage circuit region 14. Thereafter, a general contact formation process and a wiring formation process are performed.

  Further, in the cell region of the cell array region 120 shown in FIG. 5D, the fifth insulating film in the cell region in FIG. 6D is obtained by filling the space between the second electrode films 7 with the fourth insulating film 8. 9 and the sixth insulating film 10 can be peeled off, and the metal salicide film 11 can be selectively formed only on the second electrode film 7 (word line).

  In addition to the structure in which the metal salicide film 11 is formed on the transistor in the low voltage circuit region 13 as shown in FIGS. 6A, 7A, 8A, and 9A, lithography is performed. Depending on the patterning, a metal salicide film 11 is formed only on the second electrode film (word line) 7 in the cell region, and a structure specialized for reducing the resistance of the second electrode film (word line) 7 can be realized.

  With the nonvolatile semiconductor memory device and the manufacturing process thereof according to the first embodiment of the present invention described above, it is possible to increase the functionality of the transistors in the low voltage circuit region 13, increase the breakdown voltage of the transistors in the high voltage circuit region 14, and Integration can be realized at the same time.

(Second Embodiment)
-Whole plane pattern block configuration-
A schematic block configuration of the nonvolatile semiconductor memory device according to the second embodiment of the present invention includes, for example, a cell array region 120 arranged on a semiconductor chip 150 and a high voltage circuit region 90 as shown in FIG. And a low-voltage circuit region 80 and another circuit region 100 composed of a mixture of a low-voltage circuit, a high-voltage circuit, and a resistance element region. Since the detailed arrangement configuration is the same as that of the first embodiment, description thereof is omitted.

―Element structure―
The cell array region 120 and the peripheral high voltage circuit region 90 are formed before the element isolation region 3 such as STI is formed, and the peripheral low voltage circuit region 80 is formed in a later manufacturing process. The nonvolatile semiconductor memory device according to the embodiment is manufactured as shown in FIGS.

  10 to 14, (a) represents a schematic element cross-sectional structure diagram in the low-voltage circuit region 80, (b) represents a schematic element cross-sectional structure diagram in the high-voltage circuit region 90, and (c) corresponds to FIG. 2 is a schematic element cross-sectional structure diagram in a cell array region 120 to be processed.

  In the nonvolatile semiconductor memory device according to the second embodiment of the present invention, both the memory cell transistor and the transistor in the high voltage circuit region 90 have a stack gate structure, but the transistor in the low voltage circuit region 80 is a single layer. The gate structure is provided.

―Memory cell structure―
As shown in FIGS. 10C to 14C, the memory cell transistor of the nonvolatile semiconductor memory device according to the second embodiment of the present invention includes a first electrode film 4 serving as a floating electrode, The basic structure is a stack gate type structure composed of a seventh insulating film 12 serving as an interlayer insulating film and a second electrode film 7 serving as a first control gate electrode, and further on the second electrode film 7. The first metal salicide film 11 is in electrical contact with the structure. Since the structure of each part is the same as that of the memory cell transistor in the first embodiment, description thereof is omitted.

-Transistor structure in low voltage circuit area-
The transistor structure in the low voltage circuit region 80 of the nonvolatile semiconductor memory device according to the second embodiment of the present invention is the same as that of the nMOS transistor and the pMOS transistor as shown in FIGS. 10 (a) to 14 (a). Each of the two source / drain regions 20, 21, 22, 23 and the second gate regions 72, 71 has a structure in which the third metal salicide film 11 is in electrical contact. Since the structure of each part is the same as the transistor structure in the low voltage circuit region in the first embodiment, the description thereof is omitted.

-Transistor structure in high voltage circuit area-
As shown in FIG. 10B to FIG. 14B, the high voltage circuit region 90 includes, for example, a p well region 16 and an n well region 18 formed in the semiconductor substrate 1, and a p well region 16. An nMOS transistor formed and a pMOS transistor formed in the n-well region 18 are provided.

  The transistor structure in the high voltage circuit region 90 of the nonvolatile semiconductor memory device according to the second embodiment of the present invention has an nMOS transistor and a pMOS transistor gate structure as shown in FIG. That is, a stack gate type structure similar to the memory cell transistor structure is provided as a gate structure. The stacked gate type structure includes a first electrode film 4 serving as a first gate region and second electrode films 74 and 73 serving as second control gate electrodes in contact with the first electrode film 4. The laminated structure which becomes. In order to realize the gate electrode of each of the nMOS transistor and the pMOS transistor as a stacked structure, the first electrode film 4 is in electrical contact with the opening portion with respect to the seventh insulating film 12 deposited on the first electrode film 4. The structure of the second electrode films 74 and 73 is provided. Needless to say, the seventh insulating film 12 may be completely peeled off in the gate region to have a complete laminated structure.

  In the configuration shown in FIG. 14B, the second metal salicide film 11 is not in electrical contact with any of the second electrode films 74 and 73 as in the structure of FIG. The second metal salicide film 11 is insulated from the second metal salicide film 11. Alternatively, as shown in FIG. 7B, the second metal salicide film 11 may be in electrical contact with both the second electrode films 74 and 73 of the nMOS transistor and the pMOS transistor. Of course. Alternatively, as shown in FIG. 8B, a second metal salicide film is formed on a part of the first source / drain regions 24 and 25 of the nMOS transistor and the first source / drain regions 26 and 27 of the pMOS transistor. Of course, a structure in which 11 is electrically contacted may be used. Alternatively, as shown in FIG. 9B, the first source / drain regions 24 and 25 of the nMOS transistor, the first source / drain regions 26 and 27 of the pMOS transistor, and the second electrode films 74 and 73 Needless to say, the second metal salicide film 11 may be in electrical contact with any of the above.

As shown in FIG. 14B, the detailed structure of the nMOS transistor in the high voltage circuit region 90 of the nonvolatile semiconductor memory device according to the second embodiment of the present invention includes, for example, the semiconductor substrate 1 and the element isolation region. 3, a p-well region 16 formed in the semiconductor substrate 1, a second insulating film 5 serving as a gate insulating film, a first electrode film 4 disposed on the second insulating film 5, A seventh insulating film 12 deposited on one electrode film 4, an n ⁺ polysilicon gate electrode 74 that is in electrical contact through an opening formed in the seventh insulating film 12, and an n ⁺ source The drain regions 24 and 25, the n ⁻ layer 28 disposed adjacent to the n ⁺ source / drain regions 24 and 25 and serving as an electric field relaxation layer, the first electrode film 4, and the n ⁺ polysilicon gate electrode 74 It is arranged on the side wall part etc. of the stack gate type structure consisting of The fourth insulating film 8 includes a fifth insulating film 9 and a sixth insulating film 10 deposited on the n ⁺ source / drain regions 24 and 25 and the n ⁺ polysilicon gate electrode 74. Of course, the fifth insulating film 9 and the sixth insulating film 10 may be formed as a single insulating film. Alternatively, as shown in FIG. 7B, the metal salicide film 11 may be in electrical contact with the n ⁺ polysilicon gate electrode 74 of the nMOS transistor. Alternatively, as shown in FIG. 8B, the metal salicide film 11 may be in electrical contact with a part of the n ⁺ source / drain regions 24 and 25 of the nMOS transistor. Alternatively, as shown in FIG. 9B, the metal salicide film 11 is brought into electrical contact with both of the n ⁺ source / drain regions 24 and 25 of the nMOS transistor and the n ⁺ polysilicon gate electrode 74. It is good also as a structure.

The detailed structure of the pMOS transistor in the high voltage circuit region 90 of the nonvolatile semiconductor memory device according to the second embodiment of the present invention is, for example, as shown in FIG. 3, an n-well region 18 formed in the semiconductor substrate 1, a second insulating film 5 serving as a gate insulating film, a first electrode film 4 disposed on the second insulating film 5, A seventh insulating film 12 deposited on one electrode film 4, a p ⁺ polysilicon gate electrode 73 in electrical contact through an opening opened in the seventh insulating film 12, and a p ⁺ source The drain regions 26 and 27, the p ⁻ layer 29 disposed adjacent to the p ⁺ source / drain regions 26 and 27 and serving as an electric field relaxation layer, the first electrode film 4, and the p ⁺ polysilicon gate electrode 73 It is arranged on the side wall part etc. of the stack gate type structure consisting of The fourth insulating film 8 includes the fifth insulating film 9 and the sixth insulating film 10 deposited on the p ⁺ source / drain regions 26 and 27 and the p ⁺ polysilicon gate electrode 73. Of course, the fifth insulating film 9 and the sixth insulating film 10 may be formed as a single insulating film. Alternatively, as shown in FIG. 7B, the metal salicide film 11 may be in electrical contact with the p ⁺ polysilicon gate electrode 73 of the pMOS transistor. Alternatively, as shown in FIG. 8B, the metal salicide film 11 may be in electrical contact with a part of the p ⁺ source / drain regions 26 and 27 of the pMOS transistor. Alternatively, as shown in FIG. 9B, the metal salicide film 11 is in electrical contact with both the p ⁺ source / drain regions 26 and 27 and the p ⁺ polysilicon gate electrode 73 of the pMOS transistor. Also good.

-Production method-
A method for manufacturing a nonvolatile semiconductor memory device according to the second embodiment of the present invention will be described with reference to FIGS.

(A) The second insulating film 5 to be the gate insulating film of the transistor in the high voltage circuit region 90 is formed, and the first insulating film 2 that is the tunnel oxide film of the memory cell transistor in the cell array region 120 is formed in the cell array region 120. A structure formed in the memory cell transistor and at the same time in the transistor in the low voltage circuit region 80 is shown in FIGS.

(B) Next, after depositing the first electrode film 4 serving as the floating gate of the memory cell transistor, the element isolation region 3 was formed, and the seventh insulating film 12 serving as the interlayer insulating film of the memory cell transistor was deposited. Thereafter, as in FIGS. 2 and 3, in the low voltage circuit region 80, the seventh insulating film 12, the first electrode film 4, and the first insulating film 2 were peeled off using the lithography technique and the etching technique. After that, a third insulating film 6 that forms a gate oxide film of the transistor in the low voltage circuit region 80 is formed (FIGS. 11A to 11C).

(C) Next, in the high voltage circuit region 90, the control gates of the memory cell transistors formed in the process shown in FIG. 13 and the gates of the transistors in the peripheral high voltage circuit region 90 and the low voltage circuit region 80. In order to electrically connect the second electrode film 7 serving as an electrode and the first electrode film 4, a part of the gate region of the transistor in the high voltage circuit region 90 or the seventh insulating film 12 on the entire surface is peeled off. (FIGS. 12A to 12C).

(D) Next, after depositing the second electrode film 7, the second electrode film 7 is formed in the same manner as in FIG. 4 (FIGS. 13A to 13C).

(E) After that, the metal salicide film 11 is selectively formed as in FIGS. 5 to 9 (FIG. 14 has the same structure as FIG. 6).

At this time, the second electrode films 71 and 72 of the transistor in the low-voltage circuit region 80 are implanted with impurities similar to those in the diffusion layer. The p-type transistor is the p + polysilicon gate electrode 71 and the n-type transistor is n. ^The p + polysilicon gate electrode 73 and the n ⁺ polysilicon gate electrode 74 that become the ⁺ polysilicon gate electrode 72 and the gate electrode of the transistor in the high voltage circuit region 90 are electrically connected to the floating gate electrode material (N-type) 4. Since the p-type transistor is connected, p-type and n-type impurities are mixed, but the floating gate electrode material 4 and the p + polysilicon gate electrode 73 are sufficiently diffused by the subsequent thermal process. P-type gate due to the volume ratio.

  The n-type transistor is an n-type gate, similar to the transistor in the low voltage circuit region 80. Further, as described in FIG. 6D of the first embodiment of the present invention, the metal salicide film 11 can be formed only on the second electrode film 7 (word line) in the cell region. .

  Through the above-described manufacturing process of the nonvolatile semiconductor memory device according to the second embodiment of the present invention, the function of the transistor in the low voltage circuit region 80 is enhanced, the breakdown voltage of the transistor in the high voltage circuit region 90 is increased, and the integration is high. Can be realized simultaneously.

(Third embodiment)
-Whole plane pattern block configuration-
A schematic block configuration of a nonvolatile semiconductor memory device according to the third embodiment of the present invention includes, for example, a cell array region 120 arranged on a semiconductor chip 150 and a high voltage circuit region 90 as shown in FIG. And a low-voltage circuit region 80 and another circuit region 100 composed of a mixture of a low-voltage circuit, a high-voltage circuit, and a resistance element region. Since the detailed arrangement configuration is the same as that of the first embodiment, description thereof is omitted.

―Element structure―
The non-volatile semiconductor memory device according to the third embodiment of the present invention, in which the cell array region 120 and the peripheral high-voltage circuit region 90 and low-voltage circuit region 80 are formed before the element isolation region 3 such as STI is formed Is manufactured as shown in FIGS. 15 to 17, (a) represents a schematic element cross-sectional structure diagram in the low-voltage circuit region 80, (b) represents a schematic element cross-sectional structure diagram in the high-voltage circuit region 90, and (c) corresponds to FIG. 2 is a schematic element cross-sectional structure diagram in a cell array region 120 to be processed.

  In the nonvolatile semiconductor memory device according to the third embodiment of the present invention, the memory cell transistor, the transistor in the high voltage circuit region 90, and the transistor in the low voltage circuit region 80 all have a stack gate structure.

―Memory cell structure―
As shown in FIGS. 15A to 17C, the memory cell transistor of the nonvolatile semiconductor memory device according to the third embodiment of the present invention includes a first electrode film 4 serving as a floating electrode, The basic structure is a stack gate type structure composed of a seventh insulating film 12 serving as an interlayer insulating film and a second electrode film 7 serving as a first control gate electrode, and further on the second electrode film 7. And a structure in which the first metal salicide film 11 is in electrical contact. Since the structure of each part is the same as that of the memory cell transistor in the first and second embodiments, description thereof is omitted.

-Transistor structure in low voltage circuit area-
As shown in FIGS. 15A to 17A, the low-voltage circuit region 80 is formed in, for example, the p-well region 16 and the n-well region 18 formed in the semiconductor substrate 1 and the p-well region 16. An nMOS transistor formed and a pMOS transistor formed in the n-well region 18 are provided.

  The transistor in the low voltage circuit region 80 of the nonvolatile semiconductor memory device according to the third embodiment of the present invention has a gate structure of an nMOS transistor and a pMOS transistor as shown in FIG. That is, a stack gate type structure similar to the memory cell transistor structure is provided as a gate structure. The stacked gate type structure includes a first electrode film 4 serving as a second gate region and second electrode films 72 and 71 serving as third control gate electrodes in contact with the first electrode film 4. The laminated structure which becomes. In order to realize the gate structures of the nMOS transistor and the pMOS transistor as a laminated structure, respectively, the first electrode film 4 is in electrical contact with the opening portion with respect to the seventh insulating film 12 deposited on the first electrode film 4. The structure of the second electrode films 72 and 71 is provided. Needless to say, the seventh insulating film 12 may be completely peeled off in the gate region to have a complete laminated structure.

  The configuration shown in FIG. 17A is similar to the structure shown in FIG. 6A or FIG. 14A, and the second source / drain regions 20, 21, 22, 23 of the nMOS transistor and pMOS transistor, and The third metal salicide film 11 is in electrical contact with both the second gate electrodes 72 and 71.

The detailed structure of the nMOS transistor in the low voltage circuit region 80 of the nonvolatile semiconductor memory device according to the third embodiment of the present invention is, for example, as shown in FIG. 3, a p-well region 16 formed in the semiconductor substrate 1, a third insulating film 6 serving as a gate insulating film, a first electrode film 4 disposed on the third insulating film 6, A seventh insulating film 12 deposited on one electrode film 4, an n ⁺ polysilicon gate electrode 72 in electrical contact through an opening opened in the seventh insulating film 12, an n ⁺ source The drain regions 20 and 21, the n ⁻ layer 28 disposed adjacent to the n ⁺ source / drain regions 20 and 21 and serving as an electric field relaxation layer, the first electrode film 4, and the n ⁺ polysilicon gate electrode 72 It is arranged on the side wall part etc. of the stack gate type structure consisting of A fourth insulating film 8 and a metal salicide film 11 disposed in electrical contact with the n ⁺ source / drain regions 20 and 21 and the n ⁺ polysilicon gate electrode 72 are provided.

The detailed structure of the pMOS transistor in the low voltage circuit region 80 of the nonvolatile semiconductor memory device according to the third embodiment of the present invention is, for example, as shown in FIG. 3, an n-well region 18 formed in the semiconductor substrate 1, a third insulating film 6 serving as a gate insulating film, a first electrode film 4 disposed on the third insulating film 6, A seventh insulating film 12 deposited on one electrode film 4, a p ⁺ polysilicon gate electrode 71 in electrical contact via an opening opened in the seventh insulating film 12, and a p ⁺ source The drain regions 22 and 23, the p ⁻ layer 29 disposed adjacent to the p ⁺ source / drain regions 22 and 23 and serving as an electric field relaxation layer, the first electrode film 4 and the p ⁺ polysilicon gate electrode 71 It is arranged on the side wall part etc. of the stack gate type structure consisting of A fourth insulating film 8 and a metal salicide film 11 disposed in electrical contact on the p ⁺ source / drain regions 22 and 23 and the p ⁺ polysilicon gate electrode 71 are provided.

-Transistor structure in high voltage circuit area-
As shown in FIGS. 15B to 17B, the high-voltage circuit region 90 is formed in, for example, the p-well region 16 and the n-well region 18 formed in the semiconductor substrate 1 and the p-well region 16. An nMOS transistor formed and a pMOS transistor formed in the n-well region 18 are provided.

  The transistor structure in the high voltage circuit region 90 of the nonvolatile semiconductor memory device according to the third embodiment of the present invention has an nMOS transistor and pMOS transistor gate structure as shown in FIG. That is, a stack gate type structure similar to the memory cell transistor structure is provided as a gate structure. The stacked gate type structure includes a first electrode film 4 serving as a first gate region and second electrode films 74 and 73 serving as second control gate electrodes in contact with the first electrode film 4. The laminated structure which becomes. In order to realize the gate structures of the nMOS transistor and the pMOS transistor as a laminated structure, respectively, the first electrode film 4 is in electrical contact with the opening portion with respect to the seventh insulating film 12 deposited on the first electrode film 4. The structure of the second electrode films 74 and 73 is provided. Needless to say, the seventh insulating film 12 may be completely peeled off in the gate region to have a complete laminated structure. Since the structure of each part is the same as the transistor structure of the high voltage circuit region in the second embodiment, the description is omitted.

-Production method-
A method for manufacturing a nonvolatile semiconductor memory device according to the third embodiment of the present invention will be described with reference to FIGS.

(A) Similar to FIGS. 10 and 11, the second insulating film 5 to be the gate oxide film of the transistor in the high voltage circuit region 90 is formed, and the first insulating film 2 to be the tunnel oxide film of the memory cell transistor. Is formed in the cell array region 120 and the low-voltage circuit region 80, and then the first electrode film 4 serving as the floating gate of the memory cell transistor is deposited to form the element isolation region 3, which becomes the interlayer insulating film of the memory cell transistor The structure in which the seventh insulating film 12 is deposited is shown in FIGS. 15 (a) to 15 (c).

(B) Next, as in FIG. 12, in addition to the transistor in the high voltage circuit region 90, a part of the gate region of the transistor in the low voltage circuit region 80 or the seventh insulating film 12 on the entire surface is peeled off. Similarly to FIG. 13, the second electrode film 7 is formed (FIGS. 16A to 16C).

Thereafter, the metal salicide film 11 is selectively formed as in FIGS. 5 to 9 or 14 (FIG. 17 is a structure similar to FIGS. 6 and 14).

At this time, the second electrode film 7 of the transistor in the low voltage circuit region 80 and the high voltage circuit region 90 is implanted with the same impurity as the diffusion layer, and the p-type transistor has p + polysilicon gate electrodes 71 and 73. The n-type transistor becomes n ⁺ polysilicon gate electrodes 72 and 74. The p + polysilicon gate electrodes 71 and 73 and the n ⁺ polysilicon gate electrodes 72 and 74 are both electrically connected to the floating gate electrode material (n-type) 4.

In particular, the p ⁺ polysilicon gate electrode 71 of the transistor in the low voltage circuit region 80 and the p ⁺ polysilicon gate electrode 73 of the transistor in the high voltage circuit region 90 are electrically connected to the floating gate electrode material (n-type) 4. Therefore, the p-type and n-type impurities are mixed, but by sufficiently diffusing both impurities in the subsequent thermal process, the volume ratio between the floating gate electrode material 4 and the p + polysilicon gate electrodes 71 and 73 is It becomes a p-type gate.

As for the n-type transistors, both the transistors in the low voltage circuit region 80 and the transistors in the high voltage circuit region 90 are n-type gates, so that n ⁺ polysilicon gate electrodes 72 and 74 are obtained.

  Further, as described in FIG. 6D of the first embodiment of the present invention and FIG. 14C of the second embodiment, only the second electrode film 7 (word line) in the cell region. It is also possible to form the metal salicide film 11.

  Through the above-described manufacturing process of the nonvolatile semiconductor memory device according to the third embodiment of the present invention, the function of the transistor in the low voltage circuit region 80 is enhanced, the breakdown voltage of the transistor in the high voltage circuit region 90 is increased, and the integration is high. Can be realized simultaneously.

(Fourth embodiment)
FIG. 18 (a), FIG. 19 (a) and FIG. 20 (a) show a schematic element cross-sectional structure of a resistance element region included in another circuit region 100 shown in FIG. 1 as a fourth embodiment of the present invention. ). A schematic element cross-sectional structure of the wiring region of the cell array region 120, the low-voltage circuit region 80, the high-voltage circuit region 90, and the other circuit regions 100 shown in FIG. 1 is shown in FIG. 18 as the fourth embodiment of the present invention. It is shown in (b), FIG. 19 (b) and FIG. 20 (b). Both the resistance element region and the wiring region according to the fourth embodiment of the present invention are formed on the element isolation region 3. Further, it can be manufactured in common in the manufacturing process of the nonvolatile semiconductor memory device according to the first to third embodiments of the present invention.

  The resistance element region shown in FIG. 18 (a) and the wiring region shown in FIG. 18 (b) are both manufactured in common, and the process of FIG. 4 in the first embodiment or in the second embodiment. This corresponds to the step of FIG. 13 or the step of FIG. 16 in the third embodiment.

  Similarly, both the resistance element region shown in FIG. 19A and the wiring region shown in FIG. 19B are manufactured in common and correspond to the step of FIG. 5 in the first embodiment.

  Similarly, both the resistance element region shown in FIG. 20A and the wiring region shown in FIG. 20B are manufactured in common, and the steps of FIGS. 6 to 9 in the first embodiment or This corresponds to the step of FIG. 14 in the second embodiment or the step of FIG. 17 in the third embodiment.

  As shown in FIG. 18A, the resistance element region is formed by the second electrode film 76 patterned on the element isolation region 3 formed in the semiconductor substrate 1 through the seventh insulating film 12. Is done. On the other hand, as shown in FIG. 18B, the wiring region is formed by a second electrode film 75 patterned through the seventh insulating film 12 on the element isolation region 3 formed in the semiconductor substrate 1. It is formed.

―Formation method―
A method for forming a resistance element region and a wiring region using the second electrode film (control gate electrode material) 7 of the nonvolatile semiconductor memory device according to the fourth embodiment of the present invention will be described with reference to FIGS. To do.

(A) In the resistance element region, after the element isolation region 3 is formed, the seventh insulating film 12 and the second electrode film 7 are formed, and then in the same process as in FIGS. The second electrode film 76 in the region is processed as a resistance element so as to obtain a desired line width (FIG. 18A).

  Similarly, after the element isolation region 3 is formed in the wiring region, the seventh insulating film 12 and the second electrode film 7 are formed, and then in the same process as FIGS. 4, 13, and 16, A certain second electrode film 75 is used as a wiring region and processed into a line width that provides a desired wiring layer (FIG. 18B).

  For the purpose of controlling the resistance value as the resistance element, line width processing may be performed after ion implantation is performed on the second electrode film 76.

(B) Next, similarly to the high-voltage circuit regions 14 and 90 in the nonvolatile semiconductor memory devices according to the first to third embodiments, the fourth insulating film 8, the fifth insulating film 9, and the sixth By using the insulating film 10 to suppress the metal salicide film 11, it is possible to form a high-resistance resistive element region using the second electrode film 76, and to integrate the resistive element region. (FIG. 19).

  At the same time, in the wiring region, similarly to the high voltage circuit regions 14 and 90 in the nonvolatile semiconductor memory devices according to the first to third embodiments, the fourth insulating film 8 and the fifth insulating film 9 are used. As shown in FIG. 19B, a low-resistance wiring region using the second electrode film 75 can be formed, and the wiring region can be integrated (FIG. 19).

For the second electrode film 75, similarly to the high voltage circuit region 90 in the nonvolatile semiconductor memory device according to the first to third embodiments, the p ⁺ polysilicon gate electrode 73 or the n ⁺ polysilicon gate The electrode 74 can be used as it is, and therefore can be formed simultaneously. Alternatively, as a separate process, the impurity density to be added may be further increased.

(C) Next, after the sixth insulating film 10 is deposited on the entire surface, the fifth insulating film 9 and the sixth insulating film 10 on the second electrode film 75 are peeled off, and then through a metal salicide process, The metal salicide film 11 is formed in electrical contact with the second electrode film 75 (FIG. 20). Here, the formation of the metal salicide is performed in the low voltage circuit region 80, the high voltage circuit region 90 or the cell array region 120 in the nonvolatile semiconductor memory device according to the first to third embodiments. It can be formed simultaneously with the process.

  Through the above-described manufacturing process of the nonvolatile semiconductor memory device according to the fourth embodiment of the present invention, high-performance transistors in the low-voltage circuit region 80, high breakdown voltage of the transistors in the high-voltage circuit region 90, and high integration In addition, it is possible to realize high integration and high functionality in the wiring region and the resistance element region at the same time.

(Other embodiments)
As described above, the present invention has been described according to the first to fourth embodiments. However, it should not be understood that the description and drawings constituting a part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  As the basic element structure of the memory cell transistor of the nonvolatile semiconductor memory device according to the first to fourth embodiments, the stack gate type structure has been disclosed. However, the structure is not limited to this structure, and the sidewall control gate type structure is disclosed. Of course, it may be a MONOS structure or the like. In addition, as a specific circuit configuration as the nonvolatile semiconductor memory device according to the first to fourth embodiments, a NAND type, an AND type, a NOR type, or the like can be applied. Of course, various modifications and changes can be made in the manufacturing process.

  As described above, the present invention naturally includes various embodiments not described herein. Therefore, the technical scope of the present invention is defined only by the invention specifying matters according to the scope of claims reasonable from the above description.

The typical whole plane pattern block block diagram of the non-volatile semiconductor memory device which concerns on the 1st thru | or 4th embodiment of this invention. 1A and 1B are diagrams for explaining a process of a method for manufacturing a nonvolatile semiconductor memory device according to a first embodiment of the invention, in which FIG. 1A is a schematic element cross-sectional structure diagram of a low-voltage circuit region, and FIG. The typical element cross-section figure of a circuit area, (c) Corresponding typical plane pattern block diagram, (d) The typical element cross-section figure in a corresponding cell array area. 1A and 1B are diagrams for explaining a process of a method for manufacturing a nonvolatile semiconductor memory device according to a first embodiment of the invention, in which FIG. 1A is a schematic element cross-sectional structure diagram of a low-voltage circuit region, and FIG. The typical element cross-section figure of a circuit area, (c) Corresponding typical plane pattern block diagram, (d) The typical element cross-section figure in a corresponding cell array area. 1A and 1B are diagrams for explaining a process of a method for manufacturing a nonvolatile semiconductor memory device according to a first embodiment of the invention, in which FIG. 1A is a schematic element cross-sectional structure diagram of a low-voltage circuit region, and FIG. The typical element cross-section figure of a circuit area, (c) Corresponding typical plane pattern block diagram, (d) The typical element cross-section figure in a corresponding cell array area. 1A and 1B are diagrams for explaining a process of a method for manufacturing a nonvolatile semiconductor memory device according to a first embodiment of the invention, in which FIG. 1A is a schematic element cross-sectional structure diagram of a low-voltage circuit region, and FIG. The typical element cross-section figure of a circuit area, (c) Corresponding typical plane pattern block diagram, (d) The typical element cross-section figure in a corresponding cell array area. 1A and 1B are diagrams for explaining a process of a method for manufacturing a nonvolatile semiconductor memory device according to a first embodiment of the invention, in which FIG. 1A is a schematic element cross-sectional structure diagram of a low-voltage circuit region, and FIG. The typical element cross-section figure of a circuit area, (c) Corresponding typical plane pattern block diagram, (d) The typical element cross-section figure in a corresponding cell array area. 1A and 1B are diagrams for explaining a process of a method for manufacturing a nonvolatile semiconductor memory device according to a first embodiment of the invention, in which FIG. 1A is a schematic element cross-sectional structure diagram of a low-voltage circuit region, and FIG. The typical element cross-section figure of a circuit area, (c) Corresponding typical plane pattern block diagram, (d) The typical element cross-section figure in a corresponding cell array area. 1A and 1B are diagrams for explaining a process of a method for manufacturing a nonvolatile semiconductor memory device according to a first embodiment of the invention, in which FIG. 1A is a schematic element cross-sectional structure diagram of a low-voltage circuit region, and FIG. The typical element cross-section figure of a circuit area, (c) Corresponding typical plane pattern block diagram, (d) The typical element cross-section figure in a corresponding cell array area. 1A and 1B are diagrams for explaining a process of a method for manufacturing a nonvolatile semiconductor memory device according to a first embodiment of the invention, in which FIG. 1A is a schematic element cross-sectional structure diagram of a low-voltage circuit region, and FIG. The typical element cross-section figure of a circuit area, (c) Corresponding typical plane pattern block diagram, (d) The typical element cross-section figure in a corresponding cell array area. It is a figure explaining 1 process of the manufacturing method of the non-volatile semiconductor memory device which concerns on the 2nd Embodiment of this invention, Comprising: (a) Typical element cross-section figure of a low voltage circuit area, (b) High voltage The typical element cross-section figure of a circuit area | region, (c) The typical element cross-section figure in a corresponding cell array area | region. It is a figure explaining 1 process of the manufacturing method of the non-volatile semiconductor memory device which concerns on the 2nd Embodiment of this invention, Comprising: (a) Typical element cross-section figure of a low voltage circuit area, (b) High voltage The typical element cross-section figure of a circuit area | region, (c) The typical element cross-section figure in a corresponding cell array area | region. It is a figure explaining 1 process of the manufacturing method of the non-volatile semiconductor memory device which concerns on the 2nd Embodiment of this invention, Comprising: (a) Typical element cross-section figure of a low voltage circuit area, (b) High voltage The typical element cross-section figure of a circuit area | region, (c) The typical element cross-section figure in a corresponding cell array area | region. It is a figure explaining 1 process of the manufacturing method of the non-volatile semiconductor memory device which concerns on the 2nd Embodiment of this invention, Comprising: (a) Typical element cross-section figure of a low voltage circuit area, (b) High voltage The typical element cross-section figure of a circuit area | region, (c) The typical element cross-section figure in a corresponding cell array area | region. It is a figure explaining 1 process of the manufacturing method of the non-volatile semiconductor memory device which concerns on the 2nd Embodiment of this invention, Comprising: (a) Typical element cross-section figure of a low voltage circuit area, (b) High voltage The typical element cross-section figure of a circuit area | region, (c) The typical element cross-section figure in a corresponding cell array area | region. It is a figure explaining 1 process of the manufacturing method of the non-volatile semiconductor memory device based on the 3rd Embodiment of this invention, Comprising: (a) Typical element cross-section figure of a low voltage circuit area, (b) High voltage The typical element cross-section figure of a circuit area | region, (c) The typical element cross-section figure in a corresponding cell array area | region. It is a figure explaining 1 process of the manufacturing method of the non-volatile semiconductor memory device based on the 3rd Embodiment of this invention, Comprising: (a) Typical element cross-section figure of a low voltage circuit area, (b) High voltage The typical element cross-section figure of a circuit area | region, (c) The typical element cross-section figure in a corresponding cell array area | region. It is a figure explaining 1 process of the manufacturing method of the non-volatile semiconductor memory device based on the 3rd Embodiment of this invention, Comprising: (a) Typical element cross-section figure of a low voltage circuit area, (b) High voltage The typical element cross-section figure of a circuit area | region, (c) The typical element cross-section figure in a corresponding cell array area | region. It is a figure explaining 1 process of the manufacturing method of the non-volatile semiconductor memory device concerning the 4th Embodiment of this invention, Comprising: (a) Typical element cross-section figure of resistance element area | region, (b) Wiring area | region FIG. It is a figure explaining 1 process of the manufacturing method of the non-volatile semiconductor memory device concerning the 4th Embodiment of this invention, Comprising: (a) Typical element cross-section figure of resistance element area | region, (b) Wiring area | region FIG. It is a figure explaining 1 process of the manufacturing method of the non-volatile semiconductor memory device concerning the 4th Embodiment of this invention, Comprising: (a) Typical element cross-section figure of resistance element area | region, (b) Wiring area | region FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate 2 ... 1st insulating film 3 ... Element isolation region 4 ... 1st electrode film (floating gate electrode material)
5 ... 2nd insulating film 6 ... 3rd insulating film 7 ... 2nd electrode film (control gate electrode material)
8 ... 4th insulating film 9 ... 5th insulating film 10 ... 6th insulating film 11 ... Metal salicide film 12 ... 7th insulating film 13, 80 ... Low voltage circuit area | region 14, 90 ... High voltage circuit area | region 16 , 17 ... p-well region 18,19 ... n-well region 20,21,24,25 ... n ⁺ source and drain regions 22,23,26,27 ... p ⁺ source and drain regions 28 ... n ^- area 29 ... p ^- Region 30, 50 ... nMOS formation region 40, 60 ... pMOS formation region 71, 73 ... second electrode film (p ⁺ polysilicon gate electrode)
72, 74 ... second electrode film (n ⁺ polysilicon gate electrode)
75 ... Second electrode film (wiring electrode film)
76: Second electrode film (resistive electrode film)
100 ... Other circuit area 120 ... Cell array area 150 ... Semiconductor chip

Claims (7)

A cell array region comprising a memory cell transistor comprising a first control gate electrode and a floating gate electrode adjacent to the first control gate electrode;
A first source region and a drain region each comprising a high impurity density diffusion layer and a low impurity density diffusion layer disposed at both ends of the high impurity density diffusion layer, and between the first source region and the drain region. A high voltage circuit region including a high voltage transistor comprising: a first gate region to be disposed; and an insulating film covering a side wall and an upper surface of the first gate region;
A low-voltage circuit region including a low-voltage transistor comprising: a second source region and a drain region; and a second gate region disposed between the second source region and the drain region.
The insulating film covering the side wall and the upper surface of the first gate region is also disposed on the first source region and the drain region,
The first control gate electrode, the second source region and the drain region, and the second gate region are silicided, and a part of the insulating film that covers a side wall and an upper surface of the first gate region The first gate region from which is removed is silicided,
Alternatively, the high impurity density diffusion layer in the first source region and the drain region from which a part of the insulating film covering the first source region and the drain region is removed is silicided. Semiconductor memory device. A cell array region comprising a memory cell transistor comprising a first control gate electrode and a floating gate electrode adjacent to the first control gate electrode;
A first source region and a drain region each comprising a high impurity density diffusion layer and a low impurity density diffusion layer disposed at both ends of the high impurity density diffusion layer, and between the first source region and the drain region. A high voltage circuit region including a high voltage transistor comprising: a first gate region to be disposed; and an insulating film covering a side wall and an upper surface of the first gate region;
A low-voltage circuit region including a low-voltage transistor comprising: a second source region and a drain region; and a second gate region disposed between the second source region and the drain region.
The insulating film covering the side wall and the upper surface of the first gate region is also disposed on the first source region and the drain region,
The first control gate electrode, the second source region and the drain region, and the second gate region are silicided, and a part of the insulating film that covers a side wall and an upper surface of the first gate region The first gate region from which is removed is silicided,
The high impurity density diffusion layer in the first source region and drain region from which a part of the insulating film covering the first source region and drain region is removed is silicided. Semiconductor memory device. A cell array region comprising a memory cell transistor, comprising: a floating gate electrode; an insulating layer disposed on the floating gate electrode; and a first control gate electrode stacked on the floating gate electrode via the insulating layer; ,
A first source region and a drain region each comprising a high impurity density diffusion layer and a low impurity density diffusion layer disposed at both ends of the high impurity density diffusion layer, and between the first source region and the drain region. A high voltage circuit region including a high voltage transistor comprising: a first gate region to be disposed; and an insulating film covering a side wall and an upper surface of the first gate region;
A low-voltage circuit region including a low-voltage transistor including a second source region and a drain region, and a second gate region disposed between the second source region and the drain region; Both the first gate region and the second gate region are composed of a single layer,
The insulating film covering the side wall and the upper surface of the first gate region is also disposed on the first source region and the drain region,
The first control gate electrode, the second source region and the drain region, and the second gate region are silicided, and a part of the insulating film that covers a side wall and an upper surface of the first gate region The first gate region from which is removed is silicided,
Alternatively, the high impurity density diffusion layer in the first source region and the drain region from which a part of the insulating film covering the first source region and the drain region is removed is silicided. Semiconductor memory device. A cell array region comprising a memory cell transistor, comprising: a floating gate electrode; an insulating layer disposed on the floating gate electrode; and a first control gate electrode stacked on the floating gate electrode via the insulating layer; ,
A first source region and a drain region each comprising a high impurity density diffusion layer and a low impurity density diffusion layer disposed at both ends of the high impurity density diffusion layer, and between the first source region and the drain region. A high voltage circuit region including a high voltage transistor comprising: a first gate region to be disposed; and an insulating film covering a side wall and an upper surface of the first gate region;
A low-voltage circuit region including a low-voltage transistor including a second source region and a drain region, and a second gate region disposed between the second source region and the drain region; Both the first gate region and the second gate region are composed of a single layer,
The insulating film covering the side wall and the upper surface of the first gate region is also disposed on the first source region and the drain region,
The first control gate electrode, the second source region and the drain region, and the second gate region are silicided, and a part of the insulating film that covers a side wall and an upper surface of the first gate region The first gate region from which is removed is silicided,
The high impurity density diffusion layer in the first source region and drain region from which a part of the insulating film covering the first source region and drain region is removed is silicided. Semiconductor memory device. A cell array region comprising a memory cell transistor, comprising: a floating gate electrode; an insulating layer disposed on the floating gate electrode; and a first control gate electrode stacked on the floating gate electrode via the insulating layer; ,
A first source region and a drain region each comprising a high impurity density diffusion layer and a low impurity density diffusion layer disposed at both ends of the high impurity density diffusion layer, and between the first source region and the drain region. A first gate region disposed; a second control gate electrode disposed on the first gate region; sidewalls of the first gate region and the second control gate electrode; and the second A high voltage circuit region including a high voltage transistor comprising an insulating film covering an upper surface of the control gate electrode;
A second source region and a drain region; a second gate region disposed between the second source region and the drain region; and a third control gate electrode disposed on the second gate region. A low-voltage circuit region including a low-voltage transistor on a semiconductor chip,
The first control gate electrode, the second source region and drain region, and the third control gate electrode are silicided, and a part of the insulating film covering the upper surface of the second control gate electrode is formed. The removed second control gate electrode is silicided,
Alternatively, the high impurity density diffusion layer in the first source region and the drain region from which a part of the insulating film covering the first source region and the drain region is removed is silicided. Semiconductor memory device. A cell array region comprising a memory cell transistor, comprising: a floating gate electrode; an insulating layer disposed on the floating gate electrode; and a first control gate electrode stacked on the floating gate electrode via the insulating layer; ,
A first source region and a drain region each comprising a high impurity density diffusion layer and a low impurity density diffusion layer disposed at both ends of the high impurity density diffusion layer, and between the first source region and the drain region. A first gate region disposed; a second control gate electrode disposed on the first gate region; sidewalls of the first gate region and the second control gate electrode; and the second A high voltage circuit region including a high voltage transistor comprising an insulating film covering an upper surface of the control gate electrode;
A second source region and a drain region; a second gate region disposed between the second source region and the drain region; and a third control gate electrode disposed on the second gate region. A low-voltage circuit region including a low-voltage transistor on a semiconductor chip,
The first control gate electrode, the second source region and drain region, and the third control gate electrode are silicided, and a part of the insulating film covering the upper surface of the second control gate electrode is formed. The removed second control gate electrode is silicided,
The high impurity density diffusion layer in the first source region and drain region from which a part of the insulating film covering the first source region and drain region is removed is silicided. Semiconductor memory device. The non-volatile semiconductor memory device according to claim 1,
The nonvolatile semiconductor memory device, wherein the high impurity density diffusion layer in the first source region and the drain region is a region connected to a contact of the first source region and the drain region.