JPH06181293A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To maintain breakdown strength of a high voltage transistor high while holding a driving capacity of a normal transistor by differentiating widths of sidewall insulating films of a MOS transistor. CONSTITUTION:A polycrystalline silicon film 206 is formed on a field insulating film 202, insulating films 203, 205 formed on a semiconductor substrate 201, conductive impurity is ion implanted to reduce its resistance, and a gate electrode is formed by etching. Then, a source offset 207 and a drain offset 208 of a high voltage transistor and offsets 209, 210 of source and drain of a normal transistor are formed by implanting impurity. An insulating film 211 is formed on an entire surface, photoresist 212 is formed on a high voltage transistor forming region, and the film 211 out of this region is etched to reduce its thickness. Then, the resist 212 is removed, and the film 211 remains on a sidewall of the electrode 206 by etching. Thus, an insulating film can be formed thickly on the sidewall of the high voltage gate electrode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method.

[0002]

[Prior art]

(Prior Art 1) A conventional semiconductor device having a MOS high voltage transistor and a MOS transistor is as shown in FIG.

The field insulating film 8 is formed on the semiconductor substrate 801.
02 is formed, and a first gate insulating film 803 is formed on the semiconductor substrate 801 forming the MOS type high voltage transistor, and the first gate insulating film 8 is formed.
03, a gate electrode 805 of the MOS high voltage transistor is formed, and a first sidewall insulating film 807 is formed on a side wall of the gate electrode 805 of the MOS high voltage transistor. A second gate insulating film 804 is formed on a semiconductor substrate 801 forming a MOS transistor, and a gate electrode 806 of the MOS normal transistor is formed on the second gate insulating film 804. A second sidewall insulating film 808 is formed on the side wall of the gate electrode 806 of the MOS type normal transistor, and the gate electrode of the MOS type high voltage transistor and the gate electrode of the MOS type transistor have the same thickness. The width of the first sidewall insulating film 807 and the width of the second sidewall insulating film 808 are It is the same. Then, the source offset 809, the drain offset 810, the source 813, and the drain 81 of the MOS type high voltage transistor.
4, and a source offset 811, a drain offset 812, a source 815, and a drain 816 of the MOS type transistor are formed.

Next, a conventional method of manufacturing a semiconductor device will be briefly described. A conventional method for manufacturing a semiconductor device is shown in FIG.
It was as shown in FIG. 9 (e).

First, as shown in FIG. 9A, a semiconductor substrate 90
A silicon nitride film is formed on the substrate 1 in a predetermined shape. Then, thermal oxidation is performed to form a field insulating film 902. The field insulating film 902 is formed to a thickness of 600 nm to 800 nm. The nitride film is removed, and a first insulating film 903 is formed on the semiconductor substrate 901 by a thermal oxidation method. For example, the first insulating film 903 is formed to a thickness of about 30 nm by oxidizing in a dry atmosphere at an oxygen concentration of 40% at 1000 degrees. Next, using a photo and etching method, the photoresist 904 is left only in the region where the MOS type high voltage transistor is formed, and the first insulating film 903 formed in the region where the normal transistor is formed is removed.

Next, as shown in FIG. 9B, the photoresist 904 is removed, and a second insulating film 905 is formed on the silicon substrate 901 in the region where a MOS type normal transistor is formed by thermal oxidation. . For example, the first insulating film 903 is formed to a thickness of about 35 nm by being oxidized in a dry atmosphere at an oxygen concentration of 40% at 1000 ° C., and the second insulating film 9 is formed.
05 is formed to a thickness of about 15 nm. The first insulating film 90
3 is used as a gate insulating film of the high voltage transistor, and the second insulating film 905 is used as a gate insulating film of the MOS type normal transistor.

Next, as shown in FIG. 9C, the field insulating film 902, the first insulating film 903, and the second insulating film 903.
The polycrystalline silicon film 9 is formed on the insulating film 905 by the CVD method.
06 is formed to a thickness of about 200 nm. Usually, monosilane gas is thermally decomposed at around 620 ° C.
Deposit. And the first polycrystalline silicon film 9
In order to reduce the resistance of 06, for example, an element of Group 5 (for example, a conductive impurity such as phosphorus element or arsenic) is used by an ion implantation method to form 1 × 10 ¹⁵ to 1 × 10 ¹⁶ atoms · c.
Inject about m ^-2 .

Next, as shown in FIG. 9D, unnecessary portions of the polycrystalline silicon film 906 are removed by photo and etching methods. Then, an ion implantation method is used to implant impurities such as phosphorus and arsenic to remove the source offset 907 and the drain offset 908 of the MOS high voltage transistor and the source offset 909 and the drain offset 910 of the MOS normal transistor. Form.

Next, as shown in FIG. 9E, the field insulating film 902, the first insulating film 903, the second insulating film 905, the gate electrode of the MOS high voltage transistor, and the MOS type. A third insulating film 911 is usually formed on the gate electrode of the transistor by a CVD method to form 250
about nm. For example, as the third insulating film 911, a silicon oxide film is used by a high temperature CVD method (about 700 ° C. to 900 ° C.). Then, the third insulating film 911 is left only on the side wall of the polycrystalline silicon film 906 by an etching method. The third insulating film 911 is the MO
It becomes a sidewall insulating film of the S-type high voltage transistor and the MOS-type normal transistor. The etching of the third insulating film 911 is performed, for example, by using a RIE type dry etching apparatus in which a gas is introduced into a reaction chamber, a high frequency is applied between electrodes placed in parallel to plasmaize the gas, and etching is performed. , The pressure inside the device is, for example, 200 mTo
rr, the magnitude of the applied RF power is, for example, 800 W, and the etching process gas is, for example, CHF ₃ 100 sccm.
When etching is performed under the conditions of, for example, C ₂ F ₆ 25 sccm and a chamber temperature of 15 ° C., the etching rate of the silicon oxide film is 450 nm / min. For example, after the end point determination, overetching is performed at 5%. As a result, the width of the sidewall insulating film of the MOS high voltage transistor and the MOS normal transistor becomes about 0.2 μm on each side.

Finally, an ion implantation method is used to implant impurities such as phosphorus and arsenic, and the source 912 and drain 913 of the MOS high voltage transistor and the MOS
The source 914 and the drain 915 of the type normal transistor are formed.

The above is the conventional semiconductor device and the manufacturing method thereof.

(Prior Art 2) A MOS type transistor structure having a floating gate and a control gate is formed, and the MO of the control gate is changed depending on how the charge is injected into the floating gate.
A conventional semiconductor device having a semiconductor memory element in which the control threshold voltage of the characteristics of the S transistor changes, and a MOS type high voltage transistor for driving the semiconductor memory element and a MOS type normal transistor is as shown in FIG. there were.

A field insulating film 1002 is formed on the semiconductor substrate 1001, and the first insulating film 1 is formed on the semiconductor substrate 1001 forming the semiconductor memory element.
003 is formed, a first conductor layer (floating gate) 1006 is formed on the first insulating film 1003, and a fourth insulating film 1007 is formed on the first conductor layer 1006. And the fourth insulating film 1007
A second conductor layer (control gate) 1008 is formed on the first conductor layer 1006 and the fourth conductor layer 1006.
A side wall insulating film 1011 is formed on the side walls of the insulating film 1007 and the second conductor layer 1008.
Semiconductor substrate 1 on which the MOS type normal transistor is formed
A second insulating film 1004 is formed on 001,
A gate electrode 1009 of the MOS type normal transistor is formed on the second insulating film 1004, and a sidewall insulating film 1012 is formed on the side wall of the gate electrode 1009 of the MOS type normal transistor. A third insulating film 1005 is formed on a semiconductor substrate 1001 on which the MOS high voltage transistor is formed, and a gate electrode 1010 of the MOS high voltage transistor is formed on the third insulating film 1005. The sidewall insulating film 1013 is formed on the sidewall of the gate electrode 1010 of the MOS high voltage transistor.
Are formed. Then, the source 1014 and the drain 1015 of the semiconductor memory element, the source offset 1016, the drain offset 1017, the source 1020, and the drain 102 of the MOS type normal transistor.
1, and a source offset 1018, a drain offset 1019, a source 1022 and a drain 1023 of the MOS type high voltage transistor are formed. Then, the gate electrode 100 of the MOS type normal transistor
9 and the gate electrode 1 of the MOS type high voltage transistor
010 has the same thickness, and the width of the sidewall insulating film 1012 of the MOS type normal transistor is equal to that of the MO type normal transistor.
Sidewall insulating film 10 of S-type high voltage transistor
The width of 13 was characterized by being the same.

Next, an example of a conventional method for manufacturing a semiconductor device will be described in detail with reference to FIGS. 11 (a) to 11 (h).

First, as shown in FIG. 11A, the semiconductor substrate 11
A silicon nitride film is formed on 01 in a predetermined shape. Then, thermal oxidation is performed to form a field insulating film 1102. The field insulating layer 1101 has a thickness of 600 nm to 800 nm.
Form a degree. The nitride film is removed, and a first insulating film 1103 is formed on the semiconductor substrate 1101 by a thermal oxidation method. For example, it is oxidized in a dry atmosphere having an oxygen concentration of 40% at 1000 degrees. The first insulating film 1103 is an EPROM
30 nm to 50 nm is appropriate in the case of, and about 10 nm is appropriate in the case of EEPROM. This first insulating film 1
103 is used as a gate insulating film of the semiconductor memory element.

Next, as shown in FIG. 11B, a CV is formed on the field insulating film 1102 and the first insulating film 1103.
The first polycrystalline silicon film 1104 is formed to 200 nm by the D method.
Form a degree. Usually, monosilane gas is thermally decomposed at around 620 ° C. to deposit the first polycrystalline silicon 1104. Then, in order to reduce the resistance of the first polycrystalline silicon film 1104, for example, a group 5 element (for example, a conductive impurity such as phosphorus element or arsenic) is used by an ion implantation method from 1 × 10 ¹⁵ to 1 ×. Implant about 10 ¹⁶ atoms · cm ⁻² .

Next, as shown in FIG. 11C, the first polycrystalline silicon film 1104 is formed by a photo and etching method in a region other than the region for forming the semiconductor memory element.
And the first insulating film 1103 is removed.

Next, as shown in FIG. 11D, the second insulating film 1 is formed on the first polycrystalline silicon film 1104 by the thermal oxidation method.
105 is formed, and a third insulating film 1106 is formed on the semiconductor substrate 1101. For example, oxidation is performed at 1000 ° C. in a dry atmosphere having an oxygen concentration of about 40% to form the third insulating film 1106 of about 30 nm.

Next, as shown in FIG. 11 (e), the second insulating film 1105 and the region other than the region for forming the high voltage transistor of the driving element of the semiconductor memory element are formed by the photo and etching method. The third insulating film 1106 is removed.

Next, as shown in FIG. 11F, a fourth insulating film 1107 is formed on the first polycrystalline silicon film 1104 and a fifth insulating film 1108 is formed on the semiconductor substrate 1101 by a thermal oxidation method. Form. For example, oxidation is performed in a dry atmosphere having an oxygen concentration of about 40% at 1000 ° C., the fourth insulating film 1107 has a thickness of about 25 nm, and the fifth insulating film 1108 has a thickness of about 5 nm.
With a thickness of about 15 nm. By this thermal oxidation, the third insulating film 1106 has a film thickness of about 35 nm.

Next, as shown in FIG. 11G, the field insulating film 1102, the second insulating film 1105, the fourth insulating film 1107, and the fifth insulating film 1108.
A second polycrystalline silicon film 1109 is formed on the upper surface by a CVD method.
The thickness is about 40 nm. Then, in order to reduce the resistance of the first polycrystalline silicon film 1104, for example, a group 5 element (for example, a conductive impurity such as phosphorus element or arsenic) is used by an ion implantation method from 1 × 10 ¹⁵ to 1 ×. 10 ¹⁶ a
Inject about toms cm ^-2 .

Next, as shown in FIG. 11H, the second polycrystalline silicon film 1109 and the fifth insulating film 11 on the third insulating film 1106 are formed by photo and etching methods.
An unnecessary portion of the second polycrystalline silicon film 1109 on 08 is removed. This becomes the gate electrode of the MOS type high voltage transistor and the gate electrode of the MOS type normal transistor. Further, unnecessary portions of the first polycrystalline silicon film 1104, the fourth insulating film 1107, and the second polycrystalline silicon film 1109 formed in the region for forming the semiconductor memory element are removed by photo and etching methods. Remove. This becomes the gate electrode of the semiconductor memory element.

Then, using an ion implantation method, impurities such as phosphorus and arsenic are implanted to source 1110 and drain 1111 of the semiconductor memory element, source offset 1112 and drain offset 1113 of the MOS type normal transistor, and the MOS. Offset 1114 and drain offset 1 of high-voltage transistor
115 is formed. Next, the field insulating film 110
2, the first insulating film 1103, the third insulating film 1106, the fifth insulating film 1108, the gate electrode of the semiconductor memory element, the gate electrode of the MOS high voltage transistor, and the MOS The sixth insulating film 1116 on the gate electrode of the high voltage transistor
It is formed to about 250 nm by the VD method. For example, the sixth insulating film 1116 may be formed by a high temperature CVD method (from 700 ° C. to 900 ° C.).
A silicon oxide film is used depending on the temperature. Then, by using an etching method, only the side wall of the gate electrode of the semiconductor memory element, the side wall of the gate electrode of the MOS high-voltage transistor, and the side wall of the gate electrode of the MOS high-voltage transistor have the sixth feature. The insulating film 1116 is left. This becomes the side wall insulating film of the gate electrode of the semiconductor memory element, the gate electrode of the MOS high voltage transistor, and the gate electrode of the MOS high voltage transistor. For the etching, for example, a gas is introduced into the reaction chamber, a high frequency is applied between electrodes placed in parallel to plasmaize the gas, and an RIE type dry etching apparatus for etching is used, and the pressure inside the apparatus is adjusted to, for example, 200 mTorr, the magnitude of the applied RF power is 8
00W, etching process gas is CHF ₃ 1
When etching is carried out under the conditions of 00 sccm and C ₂ F ₆ 25 sccm and a chamber temperature of 15 ° C., the etching rate of the silicon oxide film is 450 nm / min.
Then, for example, after the end point determination, overetching is performed at 5%. As a result, the width of the sidewall insulating film of the semiconductor memory element becomes about 0.3 μm on each side,
The width of the sidewall insulating film of the MOS type high voltage transistor and the width of the sidewall insulating film of the MOS type normal transistor are about 0.2 μm on each side.

Finally, using the ion implantation method, the M
Source 1117 and drain 1 of OS type normal transistor
118, and a source 1119 and a drain 1120 of the MOS type high voltage transistor are formed.

The above is the conventional semiconductor device and the manufacturing method thereof.

[0026]

However, in the above-mentioned conventional technique, since the width of the sidewall insulating film formed on the sidewalls of the gate electrodes of the MOS high voltage transistor and the MOS normal transistor is the same, If the width of the sidewall insulating film is narrowed and the offset length is shortened in an attempt to increase the drive capacity of the normal transistor, the junction breakdown voltage and operating breakdown voltage of the high-voltage transistor will decrease, and the junction breakdown voltage and operating breakdown voltage of the high-voltage transistor will decrease. However, if the offset length is lengthened by increasing the width of the sidewall insulating film in order to increase the power consumption, there is a problem that the driving capability of the normal transistor decreases.

Therefore, the present invention solves such a problem, and an object thereof is to maintain the junction breakdown voltage and the operating breakdown voltage of a high voltage transistor at a high level without lowering the driving capability of the normal transistor.

[0028]

[Means for Solving the Problems]

(Means for Solving the Problem 1) In order to achieve the above object, the semiconductor device of the present invention is a semiconductor device having a MOS transistor, in which the width of the sidewall insulating film of the MOS transistor is different. It has a type transistor.

(Means for Solving the Problem 2) In order to achieve the above object, the semiconductor device of the present invention is a semiconductor device having a MOS type transistor and a MOS type high voltage transistor. The width of the wall insulating film is shorter than the width of the insulating film sidewall of the MOS type high voltage transistor.

(Means 3 for Solving the Problems) In order to achieve the above object, in the semiconductor device of the present invention, a field insulating film is formed on a semiconductor substrate in a method of manufacturing a semiconductor device having a MOS transistor. Process, forming a gate insulating film of the MOS transistor on the semiconductor substrate, the field insulating film, and the MOS
Type transistor, a step of forming a conductor layer on a gate insulating film, a step of forming a gate electrode of the MOS type transistor by removing unnecessary portions of the conductor layer, the field insulating film and the MOS type transistor Forming an insulating film on the gate insulating film and the gate electrode of the MOS transistor, thinning a part of the insulating film, and etching the insulating film to form a sidewall insulating film of the MOS transistor. And a step of forming.

(Means 4 for Solving the Problems) In order to achieve the above-mentioned object, a semiconductor device of the present invention is a semiconductor device manufacturing method having a MOS transistor and a MOS high voltage transistor. Forming a field insulating film on the semiconductor substrate, the MOS on the semiconductor substrate
Forming a gate insulating film of a MOS transistor and a gate insulating film of the MOS high voltage transistor, the field insulating film, and a gate insulating film of the MOS transistor and a gate insulating film of the MOS high voltage transistor A step of forming a conductor layer on the substrate, a step of forming a gate electrode of the MOS type transistor and a gate electrode of the MOS type high voltage transistor by removing an unnecessary portion of the conductor layer, the field insulating film, And a gate electrode of the MOS transistor, and the M
Forming an insulating film on the gate electrode of the OS type high voltage transistor, thinning the insulating film formed on the region where the MOS type transistor is formed, etching the insulating film to form the MOS type It is characterized by comprising a step of forming a sidewall insulating film of a transistor and the MOS type high voltage transistor.

(Means for Solving the Problem 5) In order to achieve the above-mentioned object, in the semiconductor device of the present invention, the height of the gate electrode of the first MOS transistor is greater than the height of the gate electrode of the second MOS transistor. Low, the first MOS
The width of the sidewall insulating film of the transistor is the second
A semiconductor device characterized by being shorter than the width of a sidewall insulating film of a MOS transistor.

(Means 6 for Solving the Problems) In order to achieve the above-mentioned object, a semiconductor device of the present invention is a semiconductor device having a MOS transistor and a MOS high voltage transistor. The height of the gate electrode is lower than the height of the gate electrode of the MOS type high voltage transistor, and the width of the sidewall insulating film of the MOS type transistor is larger than the width of the sidewall insulating film of the MOS type high voltage transistor. Characterized by being short.

(Means 7 for Solving the Problems) In order to achieve the above object, in a semiconductor device of the present invention, a field insulating film is formed on a semiconductor substrate in a method of manufacturing a semiconductor device having a MOS transistor. Process, forming a gate insulating film of the MOS transistor on the semiconductor substrate, the field insulating film, and the MOS
Forming a conductor layer on the gate insulating film of the MOS transistor, thinning a part of the conductor layer, and forming a gate electrode of the MOS transistor by removing an unnecessary portion of the conductor layer, Forming an insulating film on the field insulating film, the gate insulating film of the MOS transistor, and the gate electrode of the MOS transistor, and forming the sidewall insulating film of the MOS transistor by etching the insulating film It is characterized by comprising the step of

(Means 8 for Solving the Problems) In order to achieve the above object, a semiconductor device of the present invention is a semiconductor device manufacturing method having a MOS type transistor and a MOS type high voltage transistor. Forming a field insulating film on the semiconductor substrate, the MOS on the semiconductor substrate
Forming a gate insulating film of a MOS transistor and a gate insulating film of the MOS high voltage transistor, the field insulating film, and a gate insulating film of the MOS transistor and a gate insulating film of the MOS high voltage transistor A gate electrode of the MOS transistor by forming a conductor layer on the substrate, thinning the conductor layer formed on the region where the MOS transistor is formed, and removing unnecessary portions of the conductor layer. And the above M
Forming a gate electrode of an OS type high voltage transistor, the field insulating film, and a gate electrode of the MOS type transistor, and forming an insulating film on the gate electrode of the MOS type high voltage transistor, the insulating It is characterized in that it comprises a step of forming a sidewall insulating film of the MOS type transistor and the MOS type high voltage transistor by etching the film.

(Means for Solving the Problems 9) In order to achieve the above object, the semiconductor device of the present invention comprises a step of forming a field insulating film on a semiconductor substrate, a first MOS type transistor on the semiconductor substrate. Forming a gate insulating film, forming the field insulating film and a first conductor layer on the gate insulating film of the first MOS transistor, and forming the first conductor in a region where a second MOS transistor is formed A layer and a step of removing a gate insulating film of the first MOS transistor, a step of forming a gate insulating film of the second MOS transistor on the semiconductor substrate and the first conductor layer, and a step of forming a gate insulating film on the first conductor layer Removing all or part of the formed gate insulating film of the second MOS transistor, the field insulating film and the first conductive film. Layer and a step of forming a second conductor layer on the gate insulating film of the second MOS transistor, the first conductor layer and the second conductor layer by removing an unnecessary portion of the first conductor layer and the second MOS transistor. A step of forming a gate electrode of a 2MOS transistor,
An insulating film is formed on the field insulating film, the gate insulating film of the first MOS transistor, the gate insulating film of the second MOS transistor, the gate electrode of the first MOS transistor, and the gate electrode of the second MOS transistor. And a step of forming a sidewall insulating film of the first MOS type transistor and a sidewall insulating film of the second MOS type transistor by etching the insulating film.

(Means 10 for Solving the Problems) In order to achieve the above-mentioned object, a semiconductor device of the present invention is a method of manufacturing a semiconductor device having a MOS type transistor and a MOS type high voltage transistor. Forming a field insulating film on the semiconductor substrate,
Forming a gate insulating film of an S-type high voltage transistor, forming the field insulating film and a first conductor layer on the gate insulating film of the MOS high-voltage transistor, forming the MOS transistor Removing the first conductor layer and the gate insulating film of the MOS high-voltage transistor formed in the region, forming the gate insulating film of the MOS transistor on the semiconductor substrate and the first conductor layer The step of removing all or part of the gate insulating film of the MOS transistor formed on the first conductor layer, the field insulating film, the first conductor layer, and the gate insulating film of the MOS transistor. Forming a second conductor layer on the substrate, removing the unnecessary portion of the first conductor layer and the second conductor layer, A step of forming a transistor and a gate electrode of the MOS high voltage transistor, a field insulating film, a gate insulating film of the transistor, a gate insulating film of the MOS high voltage transistor, a gate electrode of the MOS transistor, and The MO
A step of forming an insulating film on the gate electrode of the S-type high voltage transistor, by etching the insulating film,
It is characterized in that it comprises a step of forming a sidewall insulating film of the MOS type transistor and a sidewall insulating film of the MOS type high voltage transistor.

(Means 11 for Solving the Problems) In order to achieve the above object, the semiconductor device of the present invention has a MOS type transistor structure having a floating gate and a control gate, and charges of the floating gate are charged. A semiconductor memory element in which a control threshold voltage of the characteristic of the MOS transistor of the control gate changes depending on an injection state, and a MOS type transistor for driving the semiconductor memory element and a MOS type high voltage transistor In a semiconductor device, the MOS
The height of the gate electrode of the MOS type transistor is lower than the height of the gate electrode of the MOS type high voltage transistor, and the width of the sidewall insulating film of the MOS type transistor is side wall insulation of the MOS type high voltage transistor. It is characterized by being shorter than the width of the membrane.

(Means 12 for Solving the Problems) In order to achieve the above object, the semiconductor device of the present invention has a MOS type transistor structure having a floating gate and a control gate, and charges of the floating gate are A semiconductor memory element in which a control threshold voltage of the characteristic of the MOS transistor of the control gate changes depending on an injection state, and a MOS high voltage transistor and a MOS transistor for driving the semiconductor memory element In a semiconductor device, a step of forming a field insulating film on a semiconductor substrate, a tunnel insulating film of the semiconductor memory element is formed on the semiconductor substrate in a region where the semiconductor memory element is formed, and the MOS high voltage transistor is formed. The MOS type high voltage is formed on the semiconductor substrate in the region to be formed. Forming a gate insulating film of a transistor, the field insulating film, and forming a first conductive layer on the gate insulating film of the tunnel insulating film and the MOS-type high-voltage transistor of the semiconductor memory device,
Removing the first conductor layer formed in the region for forming the MOS transistor, forming a gate insulating film of the MOS transistor on the semiconductor substrate, and forming a first insulating film on the first conductor layer; Forming the MOS, the MOS
Removing all or part of the first insulating film formed in a region for forming a high-voltage transistor, the field insulating film and the first conductor layer, the gate insulating film of the MOS transistor, and the first Second on the insulating film
Forming a conductor layer, removing unnecessary portions of the first conductor layer, the first insulating film, and the second conductor layer to form a gate electrode of the semiconductor memory element, a gate electrode of the MOS transistor, and the gate electrode of the MOS transistor. Forming a gate electrode of a MOS high voltage transistor, the field insulating film, the tunnel insulating film of the semiconductor memory element, the gate insulating film of the MOS transistor, and the MO
Forming a second insulating film on the gate insulating film of the S-type high-voltage transistor, the gate electrode of the semiconductor memory element, the gate electrode of the MOS-type transistor, and the gate electrode of the MOS-type high-voltage transistor; 2 forming a sidewall insulating film of the semiconductor memory element, a sidewall insulating film of the MOS type transistor, and a sidewall insulating film of the MOS type high voltage transistor by etching the insulating film. Characterize.

[0040]

Embodiments of the present invention will now be described in detail with reference to the drawings.

(Embodiment 1) FIG. 1 is a sectional view showing the structure of a semiconductor device of the present invention.

Reference numeral 101 is a semiconductor substrate, 102 is a field insulating film, 103 is a gate insulating film of a MOS type high voltage transistor, 104 is a gate insulating film of a MOS type normal transistor, and 105 is a gate electrode of the MOS type high voltage transistor. 106 is a gate electrode of the MOS type normal transistor, 107 is a sidewall insulating film of the MOS type high voltage transistor, 108 is a gate electrode of the MOS type normal transistor, 109 is a source offset of the MOS type high voltage transistor. , 110 is the above M
Drain offset of OS type high voltage transistor, 1
11 is the source offset of the MOS type normal transistor, 112 is the drain offset of the MOS type normal transistor, 113 is the source of the MOS type high voltage transistor, 114 is the drain of the MOS type high voltage transistor, and 115 is the MOS. Of the MOS type normal transistor, the reference numeral 116 denotes the drain of the MOS type normal transistor, and the width of the sidewall insulating film 107 of the MOS type high voltage transistor is larger than the width of the sidewall insulating film 108 of the MOS type normal transistor. The lengths of the source offset 109 and the drain offset 110 of the MOS type high voltage transistor are wider than the source offset 111 and the drain offset 1 of the MOS type normal transistor.
It is longer than the length of 12.

Next, an example of the method of manufacturing the semiconductor device of the present invention will be described in detail with reference to FIGS. 2 (a) to 2 (d).

In all the drawings of the embodiments, those having the same function are designated by the same reference numeral, and the repeated description thereof will be omitted. Hereinafter, the description will be made in order according to FIGS. 2A to 2D.

First, as shown in FIG. 2A, the semiconductor substrate 20
A silicon nitride film is formed on the substrate 1 in a predetermined shape. Then, thermal oxidation is performed to form the field insulating film 202. The field insulating film 202 is formed to a thickness of 600 nm to 800 nm. The silicon nitride film is removed, and a first insulating film 203 is formed on the semiconductor substrate 201 by a thermal oxidation method. For example, the first insulating film 20 having a thickness of about 30 nm is formed by performing oxidation in a dry atmosphere having an oxygen concentration of 40% at 1000 degrees.
3 is formed. Then, by using a photo and etching method, the first photoresist 204 is left only in a region where the MOS type high voltage transistor is formed, and the first photoresist 204 is formed in a region where the MOS type normal transistor is formed.
The insulating film 203 is removed.

Next, as shown in FIG. 2B, the first photoresist 204 is removed and a second insulating film 205 is formed on the semiconductor substrate 201 by using a thermal oxidation method. For example,
Oxidation is performed in a dry atmosphere having an oxygen concentration of 40% at 1000 ° C. to form the second insulating film 205 having a thickness of about 18 nm. By this oxidation, the first insulating film 203 is formed to a thickness of about 35 nm. The first insulating film 203 is used as a gate insulating film of the MOS high voltage transistor, and the second insulating film 203 is used.
The insulating film 205 is used as a gate insulating film of the MOS type normal transistor. Then, the field insulating film 2
02, the first insulating film 203, and the second insulating film 205, a polycrystalline silicon film 206 is formed by a CVD method,
The thickness is about 400 nm. Then, in order to reduce the resistance of the polycrystalline silicon film 206, for example, an element of Group 5 (for example, a conductive impurity such as phosphorus element or arsenic) is used by an ion implantation method to form 1 × 10 ¹⁵ to 1 × 10 ^16. ato
Inject about ms · cm ⁻² . Then, the unnecessary portion of the polycrystalline silicon film 206 is removed by photo and etching methods to form the gate electrode of the MOS type high voltage transistor and the gate electrode of the MOS type normal transistor. Next, using an ion implantation method, impurities such as phosphorus and arsenic are implanted, and the source offset 207 and drain offset 208 of the high-voltage transistor and the source offset 2 of the normal transistor are used.
09 and the drain offset 210 are formed. For example,
Energy of phosphorus or boron of about 60 KeV
By implanting about 1 × 10 ¹³ atoms · cm ^{−2 at} a source offset 207 and a drain offset 208 of the MOS type high voltage transistor and the MO
A source offset 209 and a drain offset 210 of the S-type normal transistor are formed.

The field insulating film 202, the first insulating film 203, the second insulating film 205, the gate electrode of the MOS high voltage transistor,
And a third insulating film 211 on the gate electrode of the MOS type normal transistor by the CVD method, for example, 1000 nm.
Form a degree. For example, the third insulating layer 211 may have a high temperature C
A silicon oxide film is used by the VD method (about 700 ° C. to 900 ° C.).

Next, as shown in FIG. 2C, a second photoresist 212 is formed in the region where the MOS type high voltage transistor is to be formed by photo and etching.
The third insulating film 211 formed in the region where the MOS type normal transistor is formed has a thickness of, for example, about 300 nm. For the etching, for example, a gas is introduced into the reaction chamber, a high frequency is applied between electrodes placed in parallel to plasmaize the gas, and an RIE type dry etching apparatus is used to perform etching. 200mTo
rr, the magnitude of the applied RF power is, for example, 800 W, and the etching process gas is, for example, CHF ₃ 100 sccm.
When etching is performed under the conditions of, for example, C ₂ F ₆ 25 sccm and chamber temperature of 15 ° C., the etching rate of the silicon oxide film is 450 nm / min.
Etching is performed for about 4 seconds.

Next, as shown in FIG. 2D, the second photoresist 212 is removed, and the third insulating film 211 is formed only on the sidewall of the first polycrystalline silicon film by an etching method.
Leave. For example, as the third insulating film 211, a silicon oxide film is used by a high temperature CVD method (about 700 ° C. to 900 ° C.). For the etching, for example, a gas is introduced into the reaction chamber, a high frequency is applied between electrodes placed in parallel to plasmaize the gas, and an RIE type dry etching apparatus is used to perform etching. 200mTo
rr, the magnitude of the applied RF power is, for example, 800 W, and the etching process gas is, for example, CHF ₃ 100 sccm.
When etching is performed under the conditions of, for example, C ₂ F ₆ 25 sccm and a chamber temperature of 15 ° C., the etching rate of the silicon oxide film is 450 nm / min. For example, after the end point determination, overetching is performed at 5%. As a result, the width of the sidewall insulating film of the MOS type high voltage transistor becomes about 0.4 μm, and the width of the sidewall insulating film of the MOS type normal transistor becomes about 0.2 μm.

Finally, an ion implantation method is used to implant impurities such as phosphorus and arsenic, and the source 213 and the drain 214 of the MOS high voltage transistor and the MOS.
A source 215 and a drain 216 of the type normal transistor are formed.

(Embodiment 2) FIG. 3 is a sectional view showing the structure of a semiconductor device of the present invention.

Reference numeral 301 is a semiconductor substrate, 302 is a field insulating film, 303 is a gate insulating film of a MOS type high voltage transistor, 304 is a gate insulating film of a MOS type normal transistor, 305 is a gate electrode of the MOS type high voltage transistor. 306 is a gate electrode of the MOS type normal transistor, 307 is a sidewall insulating film of the MOS type high voltage transistor, 308 is a gate electrode of the MOS type normal transistor, 309 is a source offset of the MOS type high voltage transistor. , 310 is the above M
Drain offset of OS type high voltage transistor, 3
11 is the source offset of the MOS type normal transistor, 312 is the drain offset of the MOS type normal transistor, 313 is the source of the MOS type high voltage transistor, 314 is the drain of the MOS type high voltage transistor, and 315 is the MOS. The source of the MOS type normal transistor, 316 is the drain of the MOS type normal transistor, and the gate electrode 307 of the MOS type high voltage transistor is thicker than the gate electrode 308 of the MOS type normal transistor. The width of the sidewall insulating film 307 is equal to that of the MOS
The width of the sidewall insulating film 308 of the MOS type normal transistor is larger than that of the MOS type high voltage transistor, and the lengths of the source offset 309 and the drain offset 310 of the MOS type high voltage transistor are the same as the source offset 311 of the MOS type normal transistor. And longer than the length of the drain offset 312.

Next, an example of the method of manufacturing the semiconductor device of the present invention will be described in detail with reference to FIGS. 4 (a) to 4 (d).

In all the drawings of the embodiments, those having the same function are designated by the same reference numeral, and the repeated description thereof will be omitted. Hereinafter, description will be made in order according to FIGS. 4A to 4D.

First, as shown in FIG. 4A, the semiconductor substrate 40
A silicon nitride film is formed on the substrate 1 in a predetermined shape. Then, thermal oxidation is performed to form the field insulating film 402. The field insulating film 402 is formed to have a thickness of 600 nm to 800 nm. The silicon nitride film is removed, and a first insulating film 403 is formed on the semiconductor substrate 401 by a thermal oxidation method. For example, the first insulating film 40 having a thickness of about 30 nm is formed by performing oxidation in a dry atmosphere having an oxygen concentration of 40% at 1000 degrees.
3 is formed. Then, by using a photo and etching method, the first photoresist 404 is left only in the region where the MOS type high voltage transistor is formed, and the first photoresist formed in the region where the MOS type normal transistor is formed.
The insulating film 403 is removed.

Next, as shown in FIG. 4B, the first photoresist 404 is removed, and a second insulating film 405 is formed on the semiconductor substrate 401 by using a thermal oxidation method. For example,
Oxidation is performed in a dry atmosphere having an oxygen concentration of 40% at 1000 ° C. to form the second insulating film 404 having a thickness of about 18 nm. By this oxidation, the first insulating film 403 is formed with a thickness of about 35 nm. The first insulating film 403 is used as a gate insulating film of the MOS high voltage transistor, and the second insulating film 403 is used.
The insulating film 405 is used as a gate insulating film of the MOS type normal transistor. Then, the field insulating film 4
02, the first insulating film 403, and the second insulating film 405, a polycrystalline silicon film 406 is formed by a CVD method,
For example, about 1000 nm is formed. Then, in order to reduce the resistance of the polycrystalline silicon film 406, for example, an element of Group 5 (for example, a conductive impurity such as phosphorus element or arsenic).
Using the ion implantation method from 1 × 10 ¹⁵ to 1 × 10
Inject about ¹⁶ atoms · cm ⁻² . Next, using a photo and etching method, a second photoresist 407 is formed in the region where the MOS type high voltage transistor is formed, and the polycrystalline silicon film 406 formed in the region where the MOS type normal transistor is formed is formed. For example, 300 nm
To a degree. For example, using an ECR type dry etching apparatus in which a gas is introduced into a reaction chamber, plasma is generated by microwaves, high frequency is applied as needed, and etching is performed, the pressure in the apparatus is, for example, 2.0 mTorr. The RF power is, for example, 300 W, the microwave power is, for example, 200 mA, the etching process gas is, for example, sulfur hexafluoride (SF ₆ ) 20 sccm and CFC 113 (C ₂ Cl ₃ F ₃ ) 50 sccm, and the chamber temperature is 20 ° C. The etching rate of the polycrystalline silicon film is 260 nm / min.
Therefore, etching is performed for about 160 seconds.

Next, as shown in FIG. 4C, the second photoresist 407 is removed, and an unnecessary portion of the polycrystalline silicon film 406 is removed by an etching method.
A gate electrode of the MOS type high voltage transistor and a gate electrode of the MOS type normal transistor are formed. Next, using an ion implantation method, impurities such as phosphorus and arsenic are implanted to form a source offset 408 and a drain offset 409 of the high voltage transistor, and a source offset 410 and a drain offset 411 of the normal transistor. For example, phosphorus element or boron element with an energy of about 60 KeV is 1 × 10 ¹³ atom.
By implanting about s · cm ^−2, the source offset 408 and the drain offset 409 of the MOS type high voltage transistor, and the source offset 410 and the drain offset 411 of the MOS type normal transistor.
To form.

Next, as shown in FIG. 4D, the field insulating film 402, the first insulating film 403, the second insulating film 405, the gate electrode of the MOS high voltage transistor, and the MOS type. Usually, a third insulating film 412 is formed on the gate electrode of the transistor by the CVD method by 500
about nm. For example, as the third insulating film 412, a silicon oxide film is used by a high temperature CVD method (about 700 ° C. to 900 ° C.). Then, the third insulating film 412 is left only on the side wall of the first polycrystalline silicon film 404 by an etching method. For example, a gas is introduced into the reaction chamber, a high frequency is applied between electrodes placed in parallel, the gas is converted into plasma, and an RIE type dry etching apparatus for etching is used.
The magnitude of the applied RF power is 800 W, the etching process gas is CHF ₃ 100 sccm and C ₂ F ₆ 25 sccm, and the chamber temperature is 15 ° C.
When the etching is performed under the conditions of, the etching rate of the silicon oxide film is 450 nm / min.
Overetching is performed at 5%.

As a result, the width of the side wall insulating film of the MOS type high voltage transistor becomes about 0.35 μm, and the width of the side wall insulating film of the MOS type normal transistor becomes about 0.2 μm.

Finally, an ion implantation method is used to implant impurities such as phosphorus and arsenic, and the source 413 and drain 414 of the MOS high voltage transistor and the MOS
The source 415 and the drain 416 of the type normal transistor are formed.

The above manufacturing process is the semiconductor device and the manufacturing method thereof according to one embodiment of the present invention.

(Embodiment 3) The semiconductor device shown in FIG.
It can be formed by using a method other than the manufacturing method shown in FIG. 4, and FIG. 5 is a main cross-sectional view of each step of the method of manufacturing a semiconductor memory device in one embodiment of the present invention. An example of a method of manufacturing this semiconductor device is shown in FIGS.
This will be described in detail with reference to (d).

First, as shown in FIG. 5A, the semiconductor substrate 50
A silicon nitride film is formed on the substrate 1 in a predetermined shape. Then, thermal oxidation is performed to form the field insulating film 502. The field insulating film 502 is formed to a thickness of 600 nm to 800 nm. The silicon nitride film is removed, and a first insulating film 503 is formed on the semiconductor substrate 501 by a thermal oxidation method. For example, the first insulating film 50 having a thickness of about 35 nm is formed by performing oxidation in a dry atmosphere having an oxygen concentration of 40% at 1000 degrees.
3 is formed. The first insulating film is used as a gate insulating film of the MOS high voltage transistor. next,
A first polycrystalline silicon film 504 having a thickness of about 500 nm is formed on the field insulating film 502 and the first insulating film 503 by the CVD method. Then, in order to reduce the resistance of the first polycrystalline silicon film 504, for example, a Group 5 element (for example, a conductive impurity such as phosphorus element or arsenic) is used by an ion implantation method from 1 × 10 ¹⁵ to 1 ×. 10 ¹⁶ a
Inject about toms cm ^-2 . Then, the first insulating film 50 formed in a region other than the region where the MOS type high voltage transistor is formed by using a photo and etching method.
3 and the first polycrystalline silicon film 504 are removed.

Next, as shown in FIG. 5B, a second insulating film 505 and a third insulating film 506 are formed on the semiconductor substrate 501 by using a thermal oxidation method. For example, the second insulating film 505 having a thickness of about 18 nm is formed by performing oxidation in a dry atmosphere having an oxygen concentration of 40% at 1000 degrees. The first insulating film 505 is used as a gate insulating film of the MOS type normal transistor. Next, the third insulating film 506 is entirely removed or the third insulating film 506 is removed by a photo and etching method.
A part of the insulating film 506 is removed. Then, the field insulating film 502 and the first polycrystalline silicon film 50.
4, a second polycrystalline silicon film 5 on the second insulating film 505
07 is formed to a thickness of about 500 nm by the CVD method. Then, in order to reduce the resistance of the second polycrystalline silicon film 507, for example, an element of Group 5 (for example, a conductive impurity such as phosphorus element or arsenic) is ion-implanted to 1 ×.
Implantation is performed from 10 ¹⁵ to about 1 × 10 ¹⁶ atoms · cm ⁻² .

Next, as shown in FIG. 4C, the second polycrystalline silicon film 507 formed in the region for forming the MOS type normal transistor by photo and etching methods.
The unnecessary portion of is removed and the gate electrode of the MOS type normal transistor is formed.

Further, by photo and etching methods,
The first polycrystalline silicon film 504, the third insulating film 506, and the second polycrystalline silicon film 507 formed in the region for forming the MOS type high voltage transistor.
The unnecessary portion of is removed to form the gate electrode of the MOS type high voltage transistor.

Next, using an ion implantation method, impurities such as phosphorus and arsenic are implanted to form a source offset 508 and a drain offset 509 of the high voltage transistor, and a source offset 510 and a drain offset 511 of the normal transistor. . For example, 1 × 10 ^{13 of} phosphorus element or boron element with energy of about 60 KeV.
By injecting about atoms · cm ⁻² , the MO
A source offset 508 and a drain offset 509 of the S-type high voltage transistor, and a source offset 510 and a drain offset 511 of the MOS type normal transistor are formed.

Next, as shown in FIG. 5D, the field insulating film 502, the first insulating film 503, and the second insulating film 503.
A fourth insulating film 512 is formed on the insulating film 505, the gate electrode of the MOS high-voltage transistor, and the gate electrode of the MOS normal transistor by a CVD method.
The thickness is about 0 nm. Then, the sidewall insulating film is formed by leaving the fourth insulating film 512 only on the side walls of the gate electrode of the MOS type high voltage transistor and the gate electrode of the MOS type normal transistor by an etching method. For example, introducing gas into the reaction chamber,
A high pressure is applied between the electrodes placed in parallel to turn the gas into plasma, and an RIE type dry etching apparatus is used to perform etching.
r, the magnitude of the applied RF power is 800 W, the etching process gas is CHF ₃ 100 sccm and C ₂ F ₆ 25 sccm, and the chamber temperature is 1
When etching is performed at 5 ° C, the etching rate is 4
At 50 nm / min, for example, after the end point determination, overetching is performed at 5%. As a result, the M
The width of the sidewall insulating film of the OS type high voltage transistor is about 0.35 μm on one side, and the width of the sidewall insulating film of the MOS type normal transistor is 0.2 μm on one side.
It will be about.

Finally, an ion implantation method is used to implant impurities such as phosphorus and arsenic, and the source 513 and drain 514 of the MOS high voltage transistor and the MOS
The source 515 and the drain 516 of the type normal transistor are formed.

The above manufacturing steps are the method for manufacturing the semiconductor conductor of one embodiment of the present invention.

(Embodiment 4) FIG. 6 is a sectional view showing the structure of a semiconductor device of the present invention.

Reference numeral 601 denotes a semiconductor substrate, 602 a field insulating film, 603 a gate insulating film of a semiconductor memory element, and 60.
Reference numeral 4 is a first polycrystalline silicon film (floating gate) of the semiconductor memory element, 605 is a gate insulating film of a MOS high voltage transistor, 606 is a gate insulating film of a MOS normal transistor, and 607 is a poly of the semiconductor memory element. An inter-silicon insulating film (floating gate and control gate insulating film), 608 is a second polycrystalline silicon film (control gate) of the semiconductor memory element, 609
Is a gate electrode of the MOS type normal transistor, 610
Is a gate electrode of the MOS type high voltage transistor, 6
Reference numeral 11 denotes a side wall insulating film of a gate electrode of the semiconductor memory element, 612 a side wall insulating film of a gate electrode of the MOS type normal transistor, 613 a side wall insulating film of a gate electrode of the MOS type high voltage transistor, and 614. The source offset of the MOS normal transistor, 615 the drain offset of the MOS normal transistor, 616 the source offset of the MOS high voltage transistor, 617 the drain offset of the MOS high voltage transistor, and 618 the source of the semiconductor memory element. , 619 is the drain of the semiconductor memory element, 620 is the source of the MOS normal transistor, 621 is the drain of the MOS normal transistor,
622 is a source of the MOS high-voltage transistor, 6
Reference numeral 23 denotes a drain of the MOS high voltage transistor, and a gate electrode 6 of the MOS high voltage transistor.
10 is a gate electrode 60 of the MOS type normal transistor
9, the width of the sidewall insulating film 613 of the MOS type high voltage transistor is wider than the width of the sidewall insulating film 612 of the MOS type normal transistor. Source offset 616 and drain offset 6
The length of 17 corresponds to the source offset 614 and the drain offset 61 of the MOS type normal transistor.
It is longer than the length of 5.

Next, an example of the method of manufacturing the semiconductor device of the present invention will be described in detail with reference to FIGS. 7 (a) to 7 (h).

In all the drawings of the embodiments, those having the same function are designated by the same reference numeral, and the repeated description thereof will be omitted. Hereinafter, description will be made in order according to FIGS. 7A to 7H.

First, as shown in FIG. 7A, the semiconductor substrate 70
A first silicon nitride film is formed on the first layer 1 in a predetermined shape. Then, thermal oxidation is performed to form the field insulating film 702. The field insulating layer 702 has a thickness of 600 nm to 80 nm.
The thickness is about 0 nm. The first silicon nitride film is removed, and a first insulating film 703 is formed on the semiconductor substrate 701 by a thermal oxidation method. For example, the first insulating film 703 having a thickness of about 30 nm is formed by performing oxidation in a dry atmosphere having an oxygen concentration of 40% at 1000 degrees. The first insulating film 70
3 is used as a gate insulating film of the MOS type high voltage transistor. Then, by using a photo and etching method, a photoresist 704 is left in a region where the MOS type high voltage transistor is formed and a region where the MOS type normal transistor is formed, and is formed in the region where the semiconductor memory element is formed. The first insulating film 703 is removed.

Next, as shown in FIG. 7B, the photoresist 704 is removed, and a second insulating film 705 is formed on the semiconductor substrate 701 by a thermal oxidation method.

The second insulating film 705 is used as a gate insulating film of a semiconductor memory element. The second insulating film 705 is E
In case of PROM, 30nm to 50nm, EEPROM
In the case of, about 10 nm would be appropriate. Then, a first polycrystalline silicon film 706 is formed on the first insulating film 703, the second insulating film 705, and the field insulating film 702.
Of about 250 nm. 62 normal monosilane gas
The first polycrystalline silicon 706 is thermally decomposed at around 0 degree.
Deposit. Then, in order to reduce the resistance of the first polycrystalline silicon film 706, for example, an element of Group 5 (for example, a conductive impurity such as phosphorus element or arsenic) is used by an ion implantation method from 1 × 10 ¹⁵ to 1 ×. 10 ¹⁶ atoms ・
Inject about cm ^-2 . The first polycrystalline silicon film 706 formed in the region for forming the semiconductor memory element is used as a floating gate of the semiconductor memory element.

Next, as shown in FIG. 7C, the first polycrystalline silicon film 706 formed in the region for forming the MOS type normal transistor is removed by photo and etching methods.

Next, as shown in FIG. 7D, a first silicon oxide film 707 having a thickness of about 10 nm is formed on the first polycrystalline silicon film 706 by a thermal oxidation method. Then, on the field insulating film 702, the first insulating film 703, and the first silicon oxide film 707, by a CVD method,
The second silicon nitride film 708 is formed to have a thickness of 10 nm to 15 nm.

Next, as shown in FIG. 7E, the first insulating film 703 and the second insulating film 703 formed in the region for forming the MOS type normal transistor are formed by photo and etching methods.
The silicon nitride film 708 is removed. Then, a third insulating film 709 and a second silicon oxide film 710 are formed on the first insulating film by using a thermal oxidation method. For example, the third insulating film 709 is formed to have a thickness of about 15 nm and the second silicon oxide film 710 is formed to have a thickness of about 3 nm by performing oxidation in a dry atmosphere having an oxygen concentration of about 40% at 1000 ° C. The third insulating film 709 is used as a gate insulating film of the MOS type normal transistor, and the first silicon oxide film 707, the second silicon nitride film 710, and the second silicon oxide film 7 are used.
10 is used as an insulating film between the floating gate and the control gate of the semiconductor memory element. Then, all of the first silicon oxide film 707, the second silicon nitride film 708, and the second silicon oxide film 710 formed on the region for forming the MOS type high voltage transistor are formed by photo and etching methods. Alternatively, a part of the first silicon oxide film 707, the second silicon nitride film 708, and the second silicon oxide film 710 is removed.

Next, as shown in FIG. 7F, the field insulating film 702 and the first polycrystalline silicon film 706,
And a second polycrystalline silicon film 711 having a thickness of 400 nm on the third insulating film 709 and the second silicon oxide film 710.
Form a degree. Usually, monosilane gas is thermally decomposed at around 620 ° C. to deposit the second polycrystalline silicon 711. Then, in order to reduce the resistance of the first polycrystalline silicon film 711, for example, a group 5 element (for example, a conductive impurity such as phosphorus element or arsenic) is used by an ion implantation method from 1 × 10 ¹⁵ to 1 ×. Implant about 10 ¹⁶ atoms · cm ⁻² .

Next, as shown in FIG. 7G, the second polycrystalline silicon film 711 formed in the region for forming the MOS type normal transistor by photo and etching methods.
The unnecessary portion of is removed and the gate electrode of the MOS type normal transistor is formed.

Further, by photo and etching methods,
The first polycrystalline silicon film 706, the first silicon oxide film 707, the second silicon nitride film 708, and the second silicon nitride film 708, which are formed in a region where the semiconductor memory element and the MOS high-voltage transistor are formed. A second silicon oxide film 710 and the second polycrystalline silicon film 711.
By removing the unnecessary portion of, the gate electrode of the semiconductor memory element and the gate electrode of the MOS high voltage transistor are formed.

Next, using an ion implantation method, impurities such as phosphorus and arsenic are implanted to form the source 7 of the semiconductor memory element.
12 and a drain 713, a source offset 714 and a drain offset 715 of the normal transistor, and a source offset 716 and a drain offset 717 of the high voltage transistor. For example, 1 × 1 of elemental phosphorus or elemental boron with energy of about 60 KeV
By implanting about 0 ¹³ atoms · cm ⁻² , a source offset 714 and a drain offset 715 of the MOS type normal transistor and a source offset 716 and a drain offset 717 of the MOS type high voltage transistor are formed.

Next, as shown in FIG. 7H, the field insulating film 702, the first insulating film 703, and the second insulating film 703.
An insulating film 705, and a gate electrode of the semiconductor memory element,
And a gate electrode of the MOS type high voltage transistor,
A fourth insulating film 718 is formed on the gate electrode of the MOS type normal transistor by the CVD method to a thickness of about 500 nm. For example, as the fourth insulating film 718, a silicon oxide film is used by a high temperature CVD method (about 700 ° C. to 900 ° C.). Then, the fourth insulating film 718 is formed only on the side wall of the gate electrode of the semiconductor memory element, the side wall of the gate electrode of the MOS type high voltage transistor, and the side wall of the gate electrode of the MOS type normal transistor by an etching method. By leaving it, the sidewall insulating film of each gate electrode is formed. For the etching, for example, a gas is introduced into the reaction chamber, a high frequency is applied between electrodes placed in parallel to plasmaize the gas, and an RIE type dry etching apparatus for etching is used, and the pressure inside the apparatus is adjusted to, for example, 200 mTorr, applied RF power is 800 W, etching process gas is C
HF ₃ 100 sccm and, for example, C ₂ F ₆ 25 scc
m and the chamber temperature is, for example, 15 ° C., the etching rate of the silicon oxide film is 450 n.
At m / min, for example, after the end point determination, overetching is performed at 5%. As a result, the width of the sidewall insulating film of the semiconductor memory element and the width of the sidewall insulating film of the MOS type high voltage transistor become about 0.35 μm, and the width of the sidewall insulating film of the MOS type normal transistor is reduced. Is about 0.2 μm.

Finally, an ion implantation method is used to implant impurities such as phosphorus and arsenic to form the source 719 and drain 720 of the MOS type normal transistor and the source 721 and drain 722 of the MOS type high voltage transistor. .

The above manufacturing steps are the semiconductor device and the manufacturing method thereof according to one embodiment of the present invention.

As described above, by making the width of the sidewall insulating film of the MOS type high voltage transistor wider than that of the MOS type normal transistor, the drain and source of the MOS type high voltage transistor are The offset length can be longer than the offset length of the drain and source of the normal transistor. As a result, it is possible to realize a semiconductor device having a MOS-type high-voltage transistor and a MOS-type normal transistor, in which the driving capability of the normal transistor is excellent and the high-voltage transistor has a high junction breakdown voltage and high operating breakdown voltage, and a manufacturing method thereof. Becomes

The invention made by the present inventor has been specifically described based on the above-mentioned embodiment, but the present invention is not limited to the above-mentioned embodiment, and may be modified without departing from the scope of the invention. Of course, you can do that. For example, in the embodiment of the manufacturing method and the manufacturing method of the present invention,
Although the polycrystalline silicon film is used as the control gate of the semiconductor memory element, it is also effective when a refractory metal silicide or the like is used.

Further, although the ONO film (Si0 ₂ / SiN / Si0 ₂ ) is used as the insulating film between the floating gate and the control gate of the semiconductor memory element in the third embodiment, the silicon oxide film or the NO film (SiN / Si0 ₂ ) is used. Is also effective when used.

[0091]

According to the present invention, the width of the side wall insulating film of the MOS type high voltage transistor is made wider than the width of the side wall insulating film of the MOS type normal transistor. The offset length of the drain and the source can be made longer than the offset length of the drain and the source of the normal transistor. As a result, the driving capability of the normal transistor is excellent,
Further, it is possible to realize a semiconductor device having a MOS type high voltage transistor and a MOS type normal transistor in which the high voltage transistor has a high junction breakdown voltage and a high operating breakdown voltage, and a manufacturing method thereof.

[Brief description of drawings]

FIG. 1 is a main cross-sectional view for explaining an embodiment of a semiconductor device of the present invention.

FIG. 2 is a main cross-sectional view for explaining an embodiment of the method for manufacturing a semiconductor device of the present invention in the order of steps.

FIG. 3 is a main cross-sectional view for explaining one embodiment of the semiconductor device of the present invention.

FIG. 4 is a main cross-sectional view for explaining one embodiment of the method for manufacturing a semiconductor device of the present invention in the order of steps.

FIG. 5 is a main cross-sectional view for explaining an embodiment of the method for manufacturing the semiconductor device of the present invention in the order of steps.

FIG. 6 is a main cross-sectional view for explaining an embodiment of the semiconductor device of the present invention.

FIG. 7 is a main cross-sectional view for explaining an embodiment of the method for manufacturing the semiconductor device of the present invention in the order of steps.

FIG. 8 is a main cross-sectional view for explaining a conventional semiconductor device.

FIG. 9 is a main cross-sectional view for explaining the conventional method for manufacturing a semiconductor device in the order of steps.

FIG. 10 is a main cross-sectional view for explaining a conventional semiconductor device.

FIG. 11 is a main cross-sectional view for explaining the conventional method for manufacturing a semiconductor device in the order of steps.

[Explanation of symbols]

101 semiconductor substrate 102 field insulating film 103 gate insulating film of MOS type high voltage transistor 104 gate insulating film of MOS type normal transistor 105 gate electrode of MOS type high voltage transistor 106 gate electrode of MOS type normal transistor 107 MOS type high voltage Insulation film 108 for MOS type normal transistor side wall insulation film 109 MOS type high voltage transistor source offset 110 MOS type high voltage transistor drain offset 111 MOS type normal transistor source offset 112 MOS type normal transistor Drain offset 113 Source of MOS type high voltage transistor 114 Drain of MOS type high voltage transistor 115 MOS type normal transistor Source 116 Drain of MOS type normal transistor 201 Semiconductor substrate 202 Field insulating film 203 First insulating film 204 First photoresist 205 Second insulating film 206 Polycrystalline silicon film 207 Source offset of MOS type high voltage transistor 208 MOS type high voltage Drain offset of transistor for MOS 209 source offset of MOS type normal transistor 210 drain offset of MOS type normal transistor 211 third insulating film 212 second photoresist 213 source of MOS type high voltage transistor 214 drain of MOS type high voltage transistor 215 Source of MOS type normal transistor 216 Drain of MOS type normal transistor 301 Semiconductor substrate 302 Field insulating film 303 MOS type high voltage transistor Gate insulating film 304 of MOS type normal transistor 305 gate electrode of MOS type high voltage transistor 306 gate electrode of MOS type normal transistor 307 sidewall insulating film of MOS type high voltage transistor 308 MOS type normal transistor Side wall insulating film 309 Source offset of MOS type high voltage transistor 310 Drain offset of MOS type high voltage transistor 311 Source offset of MOS type normal transistor 312 Source drain of MOS type normal transistor 313 Source of MOS type high voltage transistor 314 Drain of MOS type high voltage transistor 315 Source of MOS type normal transistor 316 Drain of MOS type normal transistor 401 Semiconductor substrate 402 Field insulating film 403 First insulating film 404 First photoresist 405 Second insulating film 406 Polysilicon film 407 Second photoresist 408 Source offset of MOS type high voltage transistor 409 Drain offset of MOS type high voltage transistor 410 MOS Type Normal transistor source offset 411 MOS type normal transistor drain offset 412 Third insulating film 413 MOS type high voltage transistor source 414 MOS type high voltage transistor drain 415 MOS type normal transistor source 416 MOS type normal transistor Drain 501 Semiconductor substrate 502 Field insulating film 503 First insulating film 504 First polycrystalline silicon film 505 Second insulating film 506 Third insulating film 507 Second polycrystalline silicon 508 Source offset of MOS type high voltage transistor 509 Drain offset of MOS type high voltage transistor 510 Source offset of MOS type normal transistor 511 Drain offset of MOS type normal transistor 512 Fourth insulating film 513 Source of MOS type high voltage transistor 514 MOS type high voltage transistor drain 515 MOS type normal transistor source 516 MOS type normal transistor drain 601 Semiconductor substrate 602 Field insulating film 603 Semiconductor memory element gate insulating film 604 First polycrystalline silicon film of semiconductor memory element ( Floating gate) 605 Gate insulating film of MOS type high voltage transistor 606 Gate insulating film of MOS type normal transistor 607 Flow chart of semiconductor memory device Insulating film between switching gate and control gate 608 Second polycrystalline silicon film (control gate) of semiconductor memory element 609 Gate electrode of MOS type normal transistor 610 Gate electrode of MOS type high voltage transistor 611 Side wall insulating film of semiconductor memory element 612 Sidewall insulating film of MOS type normal transistor 613 Sidewall insulating film of MOS type high voltage transistor 614 Source offset of MOS type normal transistor 615 Drain offset of MOS type normal transistor 616 Source offset of MOS type high voltage transistor 617 MOS Type high voltage transistor drain offset 618 semiconductor memory element source 619 semiconductor memory element drain 620 MOS type normal transistor source 621 Drain of MOS type normal transistor 622 Source of MOS type high voltage transistor 623 Drain of MOS type high voltage transistor 701 Semiconductor substrate 702 Field insulating film 703 First insulating film 704 Photoresist 705 Second insulating film 706 First polycrystalline silicon Film 707 First silicon oxide film 708 Second silicon nitride film 709 Third insulating film 710 Second silicon oxide film 711 Second polycrystalline silicon film 712 Source of semiconductor memory element 713 Drain of semiconductor memory element 714 Source of MOS type normal transistor Offset 715 MOS type normal transistor drain offset 716 MOS type high voltage transistor source offset 717 MOS type high voltage transistor drain offset 718 Fourth insulating film 719 MO Type normal transistor source 720 MOS type normal transistor drain 721 MOS type high voltage transistor source 722 MOS type high voltage transistor drain 801 Semiconductor substrate 802 Field insulating film 803 First gate insulating film 804 Second gate insulating film 805 Gate electrode of MOS type high voltage transistor 806 Gate electrode of MOS type normal transistor 807 First sidewall insulating film 808 Second sidewall insulating film 809 Source offset of MOS type high voltage transistor 810 Drain of MOS type high voltage transistor Offset 811 Source offset of MOS type normal transistor 812 Drain offset of MOS type normal transistor 813 Source of MOS type normal transistor 814 MOS type normal Drain of transistor 815 Source of MOS type high voltage transistor 816 Drain of MOS type high voltage transistor 901 Semiconductor substrate 902 Field insulating film 903 First insulating film 904 Photoresist 905 Second insulating film 906 Polycrystalline silicon film 907 MOS type high Source offset of voltage transistor 908 Drain offset of MOS type high voltage transistor 909 Source offset of MOS type normal transistor 910 Drain offset of MOS type normal transistor 911 Third insulating film 912 Source of MOS type high voltage transistor 913 MOS type high Drain of voltage transistor 914 Source of MOS type normal transistor 915 Drain of MOS type normal transistor 1001 Semiconductor substrate 1002 Field loss Edge film 1003 First insulating film 1004 Second insulating film 1005 Third insulating film 1006 First conductor layer (floating gate) 1007 Fourth insulating film 1008 Second conductor layer (control gate) 1009 MOS type normal transistor gate electrode 1010 MOS Type high voltage transistor gate electrode 1011 semiconductor memory element side wall insulating film 1012 MOS type normal transistor side wall insulating film 1013 MOS type high voltage transistor side wall insulating film 1014 semiconductor memory element source 1015 semiconductor memory element Drain 1016 Source offset of MOS type normal transistor 1017 Drain offset of MOS type normal transistor 1018 Source offset of MOS type high voltage transistor 1019 MOS type high voltage Drain offset 1020 MOS type normal transistor source 1021 MOS type normal transistor drain 1022 MOS type high voltage transistor source 1023 MOS type high voltage transistor drain 1101 Semiconductor substrate 1102 Field insulating film 1103 First insulating film 1104 First polycrystalline silicon film 1105 Second insulating film 1106 Third insulating film 1107 Fourth insulating film 1108 Fifth insulating film 1109 Second polycrystalline silicon film 1110 Source of semiconductor memory element 1111 Drain of semiconductor memory element 1112 MOS type normal transistor Source offset 1113 MOS type normal transistor drain offset 1114 MOS type high voltage transistor source offset 1115 MOS type high voltage transistor Drains offset 1116 sixth insulating film 1117 MOS type normally source 1120 MOS-type high-voltage transistor of the drain 1119 MOS-type high-voltage transistor source 1118 MOS type normal transistor transistor of Njisuta

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical display location H01L 29/792 H01L 29/78 371

Claims (12)

[Claims] 1. A semiconductor device having a MOS transistor, wherein the MOS transistor has MOS transistors having different widths of sidewall insulating films. 2. A semiconductor device having a MOS transistor and a MOS high voltage transistor, wherein the MOS
The width of the sidewall insulating film of the transistor is M
A semiconductor device characterized by being shorter than a width of an insulating film sidewall of an OS type high voltage transistor. 3. A method of manufacturing a semiconductor device having a MOS type transistor, the step of forming a field insulating film on a semiconductor substrate, the step of forming a gate insulating film of the MOS type transistor on the semiconductor substrate, and the field insulating film. Film and a step of forming a conductor layer on the gate insulating film of the MOS transistor, a step of forming a gate electrode of the MOS transistor by removing unnecessary portions of the conductor layer, the field insulating film and the Forming a gate insulating film of the MOS transistor and an insulating film on the gate electrode of the MOS transistor;
A method of manufacturing a semiconductor device, comprising: a step of thinning a part of the insulating film; and a step of forming a sidewall insulating film of the MOS transistor by etching the insulating film. 4. A method of manufacturing a semiconductor device having a MOS type transistor and a MOS type high voltage transistor,
Forming a field insulating film on a semiconductor substrate; forming a gate insulating film of the MOS type transistor and a gate insulating film of the MOS type high voltage transistor on the semiconductor substrate; the field insulating film;
A step of forming a conductor layer on the gate insulating film of the S-type transistor and the gate insulating film of the MOS type high voltage transistor, and by removing an unnecessary portion of the conductor layer to form a gate electrode of the MOS type transistor. The MO
Forming a gate electrode of an S-type high voltage transistor, the field insulating film, a gate electrode of the MOS type transistor, and forming an insulating film on the gate electrode of the MOS type high voltage transistor, the MO
From the step of thinning the insulating film formed on the region where the S-type transistor is formed, and the step of forming the sidewall insulating film of the MOS transistor and the MOS high-voltage transistor by etching the insulating film. A method of manufacturing a semiconductor device, comprising: 5. The height of the gate electrode of the first MOS type transistor is lower than the height of the gate electrode of the second MOS type transistor, and the width of the side wall insulating film of the first MOS type transistor is the side wall of the second MOS type transistor. A semiconductor device characterized by being shorter than the width of an insulating film. 6. A semiconductor device having a MOS transistor and a MOS high voltage transistor, wherein the MOS
The height of the gate electrode of the MOS type transistor is lower than the height of the gate electrode of the MOS type high voltage transistor, and the width of the sidewall insulating film of the MOS type transistor is side wall insulation of the MOS type high voltage transistor. A semiconductor device characterized by being shorter than the width of the film. 7. A method of manufacturing a semiconductor device having a MOS type transistor, the step of forming a field insulating film on a semiconductor substrate, the step of forming a gate insulating film of the MOS type transistor on the semiconductor substrate, and the field insulating film. Film and a step of forming a conductor layer on the gate insulating film of the MOS transistor, a step of thinning a part of the conductor layer, and a step of removing an unnecessary portion of the conductor layer Forming a gate electrode, forming an insulating film on the field insulating film, the gate insulating film of the MOS transistor and the gate electrode of the MOS transistor, and etching the insulating film to form the MOS transistor Semiconductor comprising a step of forming a sidewall insulating film of Method of manufacturing location. 8. A method of manufacturing a semiconductor device having a MOS type transistor and a MOS type high voltage transistor,
Forming a field insulating film on a semiconductor substrate; forming a gate insulating film of the MOS type transistor and a gate insulating film of the MOS type high voltage transistor on the semiconductor substrate; the field insulating film;
Forming a conductor layer on the gate insulating film of the S-type transistor and the gate insulating film of the MOS high-voltage transistor, thinning the conductor layer formed on a region where the MOS-type transistor is formed, A step of forming a gate electrode of the MOS type transistor and a gate electrode of the MOS type high voltage transistor by removing unnecessary portions of the conductor layer, the field insulating film,
And a step of forming an insulating film on the gate electrode of the MOS type transistor and the gate electrode of the MOS type high voltage transistor, the MOS type transistor and the MOS type high voltage transistor by etching the insulating film. A method of manufacturing a semiconductor device, comprising a step of forming a sidewall insulating film. 9. A step of forming a field insulating film on a semiconductor substrate, a step of forming a gate insulating film of a first MOS type transistor on the semiconductor substrate, the field insulating film, and a gate insulating film of the first MOS type transistor. A step of forming a first conductor layer thereon, a step of removing the first conductor layer formed in a region where a second MOS transistor is formed, and a gate insulating film of the first MOS transistor, the semiconductor substrate, and Forming a gate insulating film of the second MOS transistor on the first conductor layer; removing all or part of the gate insulating film of the second MOS transistor formed on the first conductor layer; A second insulating film, the first conductor layer, and the second insulating film on the gate insulating film of the second MOS transistor are provided.
A step of forming a conductor layer, the first conductor layer, and the second
The first MOS is formed by removing unnecessary portions of the conductor layer.
Type transistor and gate electrode of the second MOS type transistor, the field insulating film, the gate insulating film of the first MOS type transistor, the gate insulating film of the second MOS type transistor, and the first
Gate electrode of MOS transistor and the second MOS
Forming an insulating film on the gate electrode of the transistor of the type, etching the insulating film
A method of manufacturing a semiconductor device, comprising a step of forming a sidewall insulating film of a MOS transistor and a sidewall insulating film of the second MOS transistor. 10. A method of manufacturing a semiconductor device having a MOS type transistor and a MOS type high voltage transistor, a step of forming a field insulating film on a semiconductor substrate,
Forming a gate insulating film of the MOS high voltage transistor on the semiconductor substrate; forming a field insulating film and a first conductor layer on the gate insulating film of the MOS high voltage transistor; Removing the first conductor layer formed in a region for forming a MOS transistor and the gate insulating film of the MOS high voltage transistor, the semiconductor substrate, and the MOS transistor on the first conductor layer Forming a gate insulating film, removing all or part of the gate insulating film of the MOS transistor formed on the first conductor layer, the field insulating film, the first conductor layer, and the MOS type Forming a second conductor layer on a gate insulating film of a transistor, removing unnecessary portions of the first conductor layer and the second conductor layer Forming the gate electrodes of the MOS type transistor and the MOS type high voltage transistor, the field insulating film, the gate insulating film of the transistor, the gate insulating film of the MOS type high voltage transistor, and the MOS Forming an insulating film on the gate electrode of the MOS transistor and the gate electrode of the MOS high voltage transistor, etching the insulating film to form a sidewall insulating film of the MOS transistor and the MOS high voltage A method of manufacturing a semiconductor device, comprising the step of forming a sidewall insulating film of a transistor. 11. A MOS type transistor structure having a floating gate and a control gate, wherein a control threshold voltage of a characteristic of the MOS transistor of the control gate is changed depending on how an electric charge is injected into the floating gate. Semiconductor memory device,
And a semiconductor device having a MOS type transistor for driving the semiconductor memory element and a MOS type high voltage transistor, wherein the height of the gate electrode of the MOS type transistor is the gate electrode of the MOS type high voltage transistor. And a width of a sidewall insulating film of the MOS type transistor is shorter than a width of a sidewall insulating film of the MOS type high voltage transistor. 12. A MOS type transistor structure having a floating gate and a control gate, wherein a control threshold voltage of a characteristic of the MOS transistor of the control gate is changed depending on how an electric charge is injected into the floating gate. Semiconductor memory device,
And a semiconductor device having a MOS high voltage transistor for driving the semiconductor memory element and a MOS transistor, a step of forming a field insulating film on the semiconductor substrate, the semiconductor substrate in a region where the semiconductor memory element is formed Forming a tunnel insulating film of the semiconductor memory element on the semiconductor substrate, and forming a gate insulating film of the MOS high voltage transistor on the semiconductor substrate in a region where the MOS high voltage transistor is formed; A step of forming a first conductor layer (floating gate) on the film, the tunnel insulating film of the semiconductor memory element, and the gate insulating film of the MOS high-voltage transistor, formed in the region where the MOS transistor is formed. Removing the first conductor layer, the MOS transistor on the semiconductor substrate Forming a gate insulating film for the MOS transistor, and forming a first insulating film on the first conductor layer, and a part or all of the first insulating film formed in a region where the MOS high voltage transistor is formed. Removing, forming a second conductor layer (control gate) on the field insulating film, the first conductor layer, the gate insulating film of the MOS transistor and the first insulating film, and
By removing unnecessary portions of the conductor layer, the first insulating film, and the second conductor layer, the gate electrode of the semiconductor memory element, the gate electrode of the MOS type transistor, and the gate electrode of the MOS type high voltage transistor are formed. Forming step, the field insulating film, the tunnel insulating film of the semiconductor memory element, the gate insulating film of the MOS type transistor, the gate insulating film of the MOS type high voltage transistor, the gate electrode of the semiconductor memory element, and the MOS type Forming a second insulating film on the gate electrode of the transistor and the gate electrode of the MOS type high voltage transistor; etching the second insulating film to form a sidewall insulating film of the semiconductor memory element and the MOS type Transistor sidewall insulating film and the MOS type high voltage The method of manufacturing a semiconductor device characterized by comprising the step, to form the sidewall insulation film transistor.