JP2003060092A - Semiconductor memory and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent decline of reliability of device characteristics and to improve the degree of freedom of design of a memory cell device. SOLUTION: A semiconductor memory relating to the embodiment is provided with a first gate electrode of a memory transistor 28 arranged with a first interval X on a semiconductor substrate 11, a second gate electrode of peripheral transistors 29 and 30 arranged with a second interval Y on the semiconductor substrate 11, a first diffusion layer 21 formed inside the semiconductor substrate 11 holding the first gate electrode therein, second diffusion layers 24 and 26 formed inside the semiconductor substrate 11 holding the second gate electrode therein, a first insulating film 22a formed on the first diffusion layer, a second insulating film 22b formed on a side face of the second gate electrode, and silicide films 27a, 27b and 27c respectively formed on the first gate electrode, the second gate electrode and the second diffusion layers 24 and 26.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a memory transistor having a floating gate and a control gate, and a peripheral transistor for controlling the memory transistor, and a method of manufacturing the same.

[0002]

2. Description of the Related Art A NAND flash memory, which is a type of non-volatile memory, includes a memory transistor in which a floating gate and a control gate are stacked, and a peripheral transistor arranged around the memory transistor. Here, the gate of the peripheral transistor is often formed by using the same electrode material as that of the floating gate of the memory transistor. A method of manufacturing such a flash memory will be briefly described below with reference to the drawings.

42 to 50 are sectional views showing steps of manufacturing a semiconductor memory device according to the prior art. 42 to 5
0, a cross section A shows a cross section perpendicular to the element isolation region of the memory cell region, and a cross section B shows a cross section perpendicular to the gate electrode of the memory cell region.

First, as shown in FIG. 42, a semiconductor substrate 1
A first insulating film 12 serving as a gate insulating film is formed on the first insulating film 12, and a first electrode material 13 is formed on the first insulating film 12. Here, the first electrode material 13 is made of polysilicon having no impurities introduced therein. Next, the second insulating film 14 is deposited on the first electrode material 13. Next, in the second insulating film 14, the first electrode material 13, the first insulating film 12, and the semiconductor substrate 11, an S for the element isolation insulating film 15 is formed.
An element isolation region having a TI (Shallow Trench Isolation) structure is formed.

Next, as shown in FIG. 43, part of the element isolation insulating film 15 is etched so that the surface of the element isolation insulating film 15 is located below the surface of the first electrode material 13. Then, the second insulating film 14 is peeled off.

Next, as shown in FIG. 44, a resist 16a is formed on the first electrode material 13 in the PMOS region.
Using the resist 16a as a mask, ion implantation and heat treatment using, for example, P (phosphorus) are performed on the first electrode material 13 in the memory cell region to form the N ⁺ -type first conductive layers 13a and 13b. It is formed. Here, reference numeral 13a indicates the first conductive layer in the memory cell region, and reference numeral 13b indicates NM.
A first conductive layer in the OS region is shown. Further, the first conductive layer 13a in the memory cell region functions as a floating gate of the memory transistor. After that, the resist 16a is removed.

Next, as shown in FIG. 45, a resist 16b is formed on the first conductive layers 13a and 13b. Using the resist 16b as a mask, ion implantation and heat treatment using, for example, B (boron) are performed on the first electrode material 13 in the PMOS region, and the P ⁺ -type first conductive layer 13 is formed.
c is formed. Then, the resist 16b is removed.

Next, as shown in FIG. 46, a third insulating film 17 is deposited on the first conductive layers 13a, 13b, 13c and the element isolation insulating film 15, and on this third insulating film 17. The second electrode material 18 is deposited. Here, the second electrode material 18 is made of polysilicon having no impurities introduced therein.

Next, as shown in FIG. 47, a resist 19 is formed on the second electrode material 18, and the resist 19 is patterned. The second electrode material 18, the third insulating film 17, and the first conductive layers 13a, 13b, 13c are removed by using the patterned resist 19 as a mask. As a result, gate patterns of the memory transistor and the peripheral transistor are formed. Then, the resist 19 is removed and post-oxidation is performed.

Next, as shown in FIG.
An insulating film 22 is formed on the side surface of the gate of the star. next,
First insulating film 12 and second electrode in the PMOS region
A resist 23 is formed on the material 18. This resist
23 as a mask and As (arsenic) as an impurity
Ion implantation is performed, and the introduced impurities are heat treated.
Spread with. As a result, in the memory cell area
Is a second conductive layer that serves as a control gate of the memory transistor.
Layers 18a and N⁺Type source / drain diffusion layer 21
It is formed. On the other hand, in the NMOS region, the second conductor is
Electrical layer 18b and N ⁺Type source / drain diffusion layers 24 and
Is formed. Then, the resist 23 is removed.

Next, as shown in FIG. 49, the first insulating film 12 and the second insulating film 12 in the memory cell region and the NMOS region are formed.
A resist 25 is formed on the conductive layers 18a and 18b. Using the resist 25 as a mask, ion implantation is performed using, for example, B as an impurity, and the introduced impurity is diffused by heat treatment. As a result, in the PMOS region, the second conductive layer 18c and the P ⁺ type source / drain diffusion layer 26 are formed. Then, the resist 25 is removed.

Next, as shown in FIG. 50, the first insulating film 12 is removed so that the source / drain diffusion layers 21, 24 and 26 are exposed. Next, the second conductive layers 18a, 1
8b, 18c and source / drain diffusion layers 21, 24,
On top of 26, salicide made of refractory metal (SALICIDE:
Self Aligned Silicide) films 27a, 27b, 27c,
27d are formed respectively. In this way, the memory transistor 28 is formed in the memory cell area, and the NMOS transistor 29 and the PMOS transistor 30 are formed in the peripheral circuit area.

[0013]

In the memory cell region of the above conventional semiconductor memory device, the second conductive layer 18a is formed.
The salicide film 27a is formed on the control gate, and the salicide film 27d is also formed on the source / drain diffusion layer 21.

However, the source of the memory cell area /
When the salicide film 27d is present on the drain diffusion layer 21, the data retention characteristic (Data
There arises a problem that the reliability of device characteristics such as Retention characteristics) and data writing / erasing characteristics (Endurance characteristics) is reduced. Further, when the salicide film 27d is formed also on the source / drain diffusion layer 21 in the memory cell region, the degree of freedom in designing the memory cell device is remarkably limited in order to achieve both electrode material formation and device operation. There will be problems.

The present invention has been made to solve the above problems, and an object of the present invention is to prevent the reliability of device characteristics from being lowered and to improve the degree of freedom in designing a memory cell device. To provide a semiconductor memory device and a method for manufacturing the same.

[0016]

The present invention uses the following means in order to achieve the above object.

A semiconductor memory device according to a first aspect of the present invention includes a memory cell region having a first gate electrode and a second memory cell region.
And a peripheral circuit region having a gate electrode, wherein the first gate electrode is disposed on a semiconductor substrate with a first distance, and the first gate electrode is disposed on the semiconductor substrate. The second gate electrode arranged with a second gap wider than the second gap, the first diffusion layer formed in the semiconductor substrate with the first gate electrode interposed therebetween, and the second gate electrode. A second diffusion layer formed in the semiconductor substrate with the gate electrode sandwiched therebetween, a first insulating film formed on the first diffusion layer, and formed on a side surface of the second gate electrode. And a silicide film formed on the first gate electrode, the second gate electrode, and the second diffusion layer, respectively.

A method of manufacturing a semiconductor memory device according to a second aspect of the present invention is a method of manufacturing a semiconductor memory device including a memory cell region having a first gate electrode and a peripheral circuit region having a second gate electrode. Forming a first gate electrode having a first gap and a second gate electrode having a second gap wider than the first gap on a semiconductor substrate; Forming a first diffusion layer in the semiconductor substrate sandwiching a first gate electrode, and forming a first insulating film on the first diffusion layer and on the side surface of the second gate electrode. And a step of forming a second diffusion layer in the semiconductor substrate sandwiching the second gate electrode, and on the first gate electrode, the second gate electrode, and the second diffusion layer. And a step of forming a silicide film.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. When explaining this,
Common parts are designated by common reference numerals.

[First Embodiment] In the first embodiment, the insulation between the first and second conductive layers forming the gate of the peripheral transistor is formed without forming a silicide film on the diffusion layer of the memory transistor. This is an example of a structure in which the film is entirely removed. Further, in the first embodiment, a NAND flash memory will be described as an example, but it can be applied to other memories as long as it has a structure in which memory cells are arranged in a line, such as an AND type. is there.

FIG. 1 is a sectional view of a semiconductor memory device according to the first embodiment of the present invention. In FIG. 1, cross section A
Shows a cross-sectional view perpendicular to the element isolation region in the memory cell region, and cross-section B shows a cross-sectional view perpendicular to the gate electrode in the memory cell region.

As shown in FIG. 1, the semiconductor memory device according to the first embodiment includes a memory cell region and a peripheral circuit region including an NMOS region and a PMOS region. A gate of the memory transistor 28 having a first distance X is formed in the memory cell area, and a first gate is formed in the peripheral circuit area.
And P with a second spacing Y wider than the spacing X of
The gates of the MOS peripheral transistors 29 and 30 are formed. The gate of the memory transistor 28 includes a first conductive layer 13a that serves as a floating gate and a second conductive layer 18a that serves as a control gate.
The insulating film 17 is formed between 18a. On the other hand, the gates of the peripheral transistors 29, 30 have the first conductive layers 13b, 1
3c and the second conductive layers 18b and 18c, no insulating film is formed between the first and second conductive layers 13b, 13c, 18b and 18c. The insulating film 22a is embedded between the gates of the memory transistors 28, and the peripheral transistors 2
An insulating film 22b is formed on the side surfaces of the gates 9 and 30, respectively. The insulating film 22a and the insulating film 22b are simultaneously formed of the same material. A first diffusion layer 21 is formed in the semiconductor substrate 11 under the gate of the memory transistor 28,
Semiconductor substrate 1 under the gates of peripheral transistors 29, 30
Second diffusion layers 24 and 26 are formed in the first layer 1, respectively.
Memory transistor 28 gate, peripheral transistor 2
On the gates 9 and 30 and the second diffusion layers 24 and 26,
SALICIDE (Self Aligned Silicide) film 2
7a, 27b, 27c are formed, and the salicide film is not formed on the diffusion layer 21 of the memory transistor 28.

The insulating film 22a is embedded between the gates of the memory transistors 28, but the invention is not limited to the case where the gates are completely filled. If the salicide film is not formed on the diffusion layer 21, the insulating film 22a is formed in the insulating film 22a. Microvoids (eg voids) may be present. Although the insulating film 22a shown in FIG. 1 is deposited up to the gate surface of the memory transistor, it may not be deposited up to the gate surface of the memory transistor as long as it covers the surface of the diffusion layer 21. Further, the gate of the memory transistor 28 and the gate of the peripheral transistor 29 may be arranged with a second interval Y, for example.

2 to 14 are sectional views showing the steps of manufacturing the semiconductor memory device according to the first embodiment of the present invention. The method of manufacturing the semiconductor memory device according to the first embodiment will be described below.

First, as shown in FIG. 2, the semiconductor substrate 11
A first insulating film 12 serving as a gate insulating film is formed on top. The first insulating film 12 has a film thickness of, for example, about 100Å. Next, the first electrode material 13 is formed on the first insulating film 12. The first electrode material 13 is made of polysilicon with no impurities introduced. Then, the second insulating film 1 made of a silicon nitride film is formed on the first electrode material 13.
4 are deposited. Incidentally, in order to control the channel in the memory transistor and the peripheral transistor, the channel ion implantation and the well ion implantation are performed before the first insulating film 12 is formed.

Next, as shown in FIG. 3, the second insulating film 1
4, the first electrode material 13, the first insulating film 12 and the semiconductor substrate 11 are selectively removed to form an element isolation groove. An element isolation insulating film 15 made of, for example, a silicon oxide film is deposited in the element isolation trench, and the element isolation insulating film 15 is planarized until the surface of the second insulating film 14 is exposed. That is, the second insulating film 14 functions as a stopper film when the element isolation insulating film 15 is flattened.
In this way, the STI made of the element isolation insulating film 15 is formed.
An element isolation region having a (Shallow Trench Isolation) structure is formed.

Next, as shown in FIG. 4, part of the element isolation insulating film 15 is etched so that the surface of the element isolation insulating film 15 is located below the surface of the first electrode material 13. Then, the second insulating film 14 is peeled off.

Next, as shown in FIG. 5, the first electrode material 1
3 has a resist 16 formed on it, and this resist 16 is surrounded.
It is patterned so as to remain only on the side circuit region. This
Using the patterned resist 16 of
Ion implantation and implantation into the first electrode material 13 in the molycell region
And heat treatment are performed to form the first conductive layer 13a.
Here, the memory transistor is an NMOS transistor
In this case, for example, P (phosphorus) is used as an impurity, and
The conductive layer 13a has an impurity concentration of, for example, 2 × 10 ²⁰cm^-3
Ion implantation is performed under conditions such that the ion implantation degree is in the range. Incidentally, N
As (arsenic) is used instead of P as the type impurity.
There may be cases. First conductive formed as described above
Layer 13a serves as the floating gate of the memory transistor.
To work. After the first conductive layer 13a is formed, the
Gist 16 is removed.

Next, as shown in FIG. 6, the first electrode material 1
3, on the first conductive layer 13a and the element isolation insulating film 15,
For example, a third layer made of ONO (Oxide Nitride Oxide) film
The insulating film 17 is deposited. Next, the third part of the peripheral circuit area
The insulating film 17 is removed, and the third insulating film 17 remains only in the memory cell region.

Next, as shown in FIG. 7, the third insulating film 1
7, the second electrode material 18 is deposited on the first electrode material 13 and the element isolation insulating film 15. Here, the second electrode material 1
8 is made of polysilicon with no impurities introduced.

Next, as shown in FIG. 8, the second electrode material 1
A resist 19 is formed on the surface 8, and the resist 19 is patterned. This patterned resist 1
9 as a mask, the first and second electrode materials 13, 18,
The first conductive layer 13a and the third insulating film 17 are removed.
As a result, gate patterns of the memory transistor and the peripheral transistor are formed.

Next, as shown in FIG. 9, the resist 19 is removed. Next, post-oxidation is performed to form an oxide film (not shown) on the gate.

Next, as shown in FIG. 10, a resist 20 is formed on the first insulating film 12 and the second electrode material 18, and is patterned so that the resist 20 remains only in the peripheral circuit region. Ion implantation is performed using the patterned resist 20 as a mask to form source / drain diffusion layers 21 in the semiconductor substrate 11 in the memory cell region. When the memory transistor is an NMOS transistor, P or As is used as an impurity. Then, the resist 20 is removed.

Next, as shown in FIG. 11, a fourth insulating film 22 is formed on the first insulating film 12 and the second electrode material 18. At this time, the fourth insulating film 22 completely fills the gaps between the gates of the memory cell region and does not fill the gaps between the gates of the peripheral circuit region. That is, when the distance between the gates of the memory cell region is X, the distance between the gates of the peripheral circuit region is Y, and the film thickness of the fourth insulating film 22 is A, the relationship of the following expression (1) is satisfied.

X / 2 ≦ A <Y / 2 (1) For example, the distance X between the gates of the memory cell region is F (minimum processing size), and the distance Y between the gates of the peripheral circuit region is 2F to
In the case of 3F, the film thickness A of the fourth insulating film 22 is set so as to satisfy the relationship of the following expression (2).

F / 2 ≦ A <F to 3F / 2 (2) The distance Y between the gates of the peripheral circuit region is 1.3 to 5.0 times the distance X between the gates of the memory cell region. You may In this case, the gate of the peripheral circuit region may include the gate of the selection transistor.

The fourth insulating film 22 is preferably made of an oxide film. That is, the fourth insulating film 22 is, for example, a silicon oxide film (SiO _x ) or TEOS (Tetra Eth).
yl Ortho Silicate) film, ozone TEOS film, HTO (H
igh Temperature Oxide) film, SOG (Spin On Glass)
Film, coating type organic oxide film, SA-CVD (Semi Atmos
pheric-Chemical Vapor Deposition) film, plasma C
It is a VD film, a PSG (Phosphorous Silicate Glass) film, or the like.

Next, as shown in FIG. 12, the fourth insulating film 22 is etched back to expose the surface of the second electrode material 18 and the first insulating film 12 or the diffusion layer region of the peripheral transistor. . Thus, the buried insulating film 22a is formed between the gates in the memory cell region, and the sidewall insulating film 22b is formed on the side surface of the gate in the peripheral circuit region.

Next, as shown in FIG. 13, the first insulating film
A resist 23 is formed on the second electrode material 18 and the second electrode material 18.
So that this resist 23 remains only in the PMOS region.
Patterned. This patterned resist
23 as a mask and As (arsenic) as an impurity
The acceleration voltage is about tens of KeV and the dose is about 10¹⁵cm
^-2Ion implantation is performed under the conditions of. That is, the memory cell
Region second electrode material 18, NMOS region second electrode material
Impurities are introduced into 18 and the semiconductor substrate 11. That
By diffusing the introduced impurities by heat treatment.
The second conductive layer 18a is formed in the memory cell area.
The first and second conductive layers formed in the NMOS region
13b, 18b, N⁺Type source / drain diffusion layer 24
Is formed. Here, the first conductive layer 1 in the NMOS region
3b was introduced into the second electrode material 18 in the NMOS region
Diffuse impurities into the first electrode material 13 in the NMOS region
Formed by. After the above steps, the resist 23
Are removed.

Next, as shown in FIG. 14, a resist 25 is formed on the first insulating film 12 and the second electrode material 18, and patterned so that the resist 25 remains only in the memory cell region and the NMOS region. To be done. Using the patterned resist 25 as a mask, ion implantation is performed with B (boron) as an impurity under the conditions of an acceleration voltage of about ten and several KeV and a dose amount of about 10 ¹⁵ cm ^-2 .
That is, impurities are introduced into the second electrode material 18 and the semiconductor substrate 11 in the PMOS region. Then, the introduced impurities are diffused by heat treatment, so that the first and second conductive layers 13c, 18c and P are formed in the PMOS region.
^{A +} type source / drain diffusion layer 26 is formed. Here, the first conductive layer 13c in the PMOS region is formed by diffusing the impurities introduced into the second electrode material 18 in the PMOS region into the first electrode material 13 in the PMOS region. After the above steps, the resist 25 is removed.

Next, as shown in FIG. 1, the oxide film on the gate is removed so that the surface of the gate is exposed, and the source / drain diffusion layers 24 of the peripheral transistors are formed.
The first insulating film 12 is removed to expose 26.
Next, on the second conductive layers 18a, 18b, 18c, the buried insulating film 22a, the sidewall insulating film 22b, the source / drain diffusion layers 24, 26, for example, Co (cobalt) or T
A refractory metal film made of i (titanium) or the like is deposited. Next, heat treatment is performed to react the refractory metal with silicon. As a result, the second conductive layer 18 in the memory cell area is formed.
Salicide films 27a, 27b, 27c are formed on the second conductive layers 18b, 18c and the source / drain diffusion layers 24, 26 in the peripheral circuit region, respectively. Then, the unreacted refractory metal film is removed. In this way, the memory transistor 28 in which the salicide film does not exist on the diffusion layer 21 in the memory cell region is formed, and the NMOS transistor 29 and the PMOS transistor 30 in which the salicide film 27c exists on the diffusion layers 24 and 26 in the peripheral circuit region. Is formed.

After the element forming process as described above, an interlayer insulating film (not shown) is deposited on the gate electrode by using a known technique, and W (tungsten), for example, is deposited in the interlayer insulating film. A contact (not shown) consisting of
A wiring layer (not shown) connected to this contact is formed.

The memory transistor 28 may be P-type. In this case, for example, when introducing impurities into the first and second electrode materials 13 and 18 of the PMOS transistor 30, it is necessary to introduce impurities into the first and second electrode materials 13 and 18 of the memory transistor 28 at the same time. Good.

Further, the diffusion layers 24 and 26 of the peripheral transistors 29 and 30 may have an LDD (Lightly Doped Drain) structure. That is, before depositing the fourth insulating film 22, the predetermined semiconductor substrate 11 in the NMOS and PMOS regions is formed.
The N ⁻ type and P ⁻ type diffusion layers may be formed therein, and then the N ⁺ type and P ⁺ type diffusion layers 24 and 26 may be formed as described above.

In the step shown in FIG. 12, the fourth insulating film 22 is etched back, so that the surface of the semiconductor substrate 11 in the diffusion layer region of the peripheral transistor and the second insulating film 22 are etched back.
Since the surface of the electrode material 18 is exposed, a protective film may be formed on these surfaces. That is, after the etch-back process, these surfaces are thinly oxidized or an oxide film is deposited to form a protective film, and after the ion implantation and activation processes shown in FIGS. 13 and 14, the salicide films 27a and 27b, This protective film may be removed before forming 27c.

The etch back process shown in FIG. 12 may be omitted. In this case, the fourth insulating film 2 shown in FIG.
After depositing 2, the ion implantation and activation steps shown in FIGS. 13 and 14 are performed. Here, at the time of ion implantation, ions pass through the second electrode material 18 and the fourth insulating film 22 deposited on the first insulating film 12, and the ions are introduced into the second electrode material 18 and the semiconductor substrate 11. It is necessary to adjust the acceleration energy to reach.

According to the first embodiment described above, since the buried insulating film 22a is formed between the gates of the memory transistor 28, the salicide film is not formed on the diffusion layer 21 and the floating gate of the memory transistor 28. Therefore,
Since the characteristics of the memory cell region as the flash memory are hardly changed, it is possible to prevent the reliability of the device characteristics of the memory transistor 28 from being lowered. At the same time, in the peripheral transistors 29 and 30, the salicide films 27b and 27c are formed on the gates and the diffusion layers 24 and 26, and in the memory transistor 28, the salicide film 27a is formed only on the control gate. Therefore, the gates of the peripheral transistors 29 and 30 and the diffusion layer 2
It is possible to reduce the resistances of Nos. 4 and 26 and to reduce the resistance of the control gate of the memory transistor 28. Therefore, lowering the resistances of the gates of the peripheral transistors 29 and 30 and the diffusion layers 24 and 26 contributes to higher performance of the device, and lowering the resistance of the control gate of the memory transistor 28 increases the capacity of the memory cell array. In addition, since the number of divided arrays is small, it can greatly contribute to the reduction of the chip area.

Further, the salicide film 27d is not formed on the source / drain diffusion layer 21 in the memory cell region. Therefore, even when the electrode material formation and the device operation are compatible with each other, the problem that the degree of freedom in designing the memory cell device is significantly limited can be avoided.

Further, since the separation of the first electrode layer 13 is performed in a self-aligned manner with the formation of the element isolation region shown in FIG.
It is possible to miniaturize the cell size.

Further, the NAND type flash memory can be manufactured by using the salicide technique which is often used as a standard in the system LSI. That is, the first embodiment is also applicable to manufacture of a mixed chip of a flash memory and a system LSI, which requires high performance and high functionality of elements such as high speed operability, low power consumption, and low voltage driving. It is a very effective manufacturing method.

Since the salicide film 27c is formed on the diffusion layers 24 and 26 in the peripheral circuit region, the resistance of the contacts connected to the diffusion layers 24 and 26 can be reduced without degrading the characteristics of the memory cell. You can Therefore, due to the voltage drop due to the contact resistance, the peripheral transistor 2
It is possible to prevent the drive currents of 9 and 30 from decreasing.

[Second Embodiment] The second embodiment is an example in which an insulating film having an opening is provided between the first and second conductive layers of the peripheral transistor in the first embodiment.

FIG. 15 is a sectional view of a semiconductor memory device according to the second embodiment of the present invention. As shown in FIG.
The semiconductor memory device according to the second embodiment differs from the first embodiment in that the first and second conductive layers 13b, 18b, 13c, 18c of the peripheral transistors 29, 30 are different.
The insulating film 17 having the opening 31 is provided therebetween. The insulating film 17 is the first film of the memory transistor 28.
And the insulating film 17 provided between the second conductive layers 13a and 18a
And the same material are formed at the same time. Further, the opening 31 of the insulating film 17 has the first and second conductive layers 13b, 18b, 1
It is desirable to be arranged in the center between 3c and 18c. Further, the opening 31 of the insulating film 17 is formed by the first conductive layer 13b,
13c and the second conductive layers 18b and 18c are provided for electrical continuity, so that if the electrical continuity is possible, the opening 3
The number and shape of 1 may be arbitrary, and a plurality of openings 31 may be provided.

16 to 21 are sectional views showing the steps of manufacturing a semiconductor memory device according to the second embodiment of the present invention.
The method of manufacturing the semiconductor memory device according to the second embodiment will be described below. In the method of manufacturing the semiconductor memory device according to the second embodiment, description of steps similar to those of the method of manufacturing the semiconductor memory device according to the first embodiment will be simplified.
Only different steps will be described.

First, as shown in FIGS. 2 to 5, as in the first embodiment, the first conductive layer 13 is formed in the memory cell region.
a is formed.

Next, as shown in FIG. 16, a third insulating film 17 made of, for example, an ONO film is deposited on the first electrode material 13, the first conductive layer 13a and the element isolation insulating film 15. . Next, the third insulating film 17 in the peripheral circuit region is selectively removed to form the opening 31.

Next, as shown in FIG. 17, the second electrode material 18 is deposited on the third insulating film 17, the first electrode material 13, the first conductive layer 13ba, and the element isolation insulating film 15. To be done. Here, the second electrode material 18 is made of polysilicon having no impurities introduced therein.

Next, as shown in FIG. 18, a resist 19 is formed on the second electrode material 18 and patterned. Using the patterned resist 19 as a mask, the first and second electrode materials 13, 18 and the third insulating film 1 are formed.
7 and the first conductive layer 13a are removed. This allows
Gate patterns of memory transistors and peripheral transistors are formed.

Next, as shown in FIG.
Are removed. Next, post-oxidation is performed to form an oxide film (not shown) on the gate.

Next, as shown in FIG. 20, the first insulating film
A resist 20 is formed on the second electrode material 18 and the second electrode material 18.
Is patterned. This patterned register
Ion implantation is performed using the mask 20 as a mask,
N in the semiconductor substrate 11 in the region ⁺Type source / drain expansion
The diffused layer 21 is formed. After that, the resist 20 is removed.
Be done.

Next, as shown in FIG. 21, a fourth insulating film 22 is formed on the first insulating film 12 and the second electrode material 18 so as to satisfy the relationship of the formula (1).

Next, as shown in FIG. 22, the fourth insulating film 22 is etched back to expose the surface of the second electrode material 18 and the first insulating film 12 or the diffusion layer region of the peripheral transistor. . Thus, the buried insulating film 22a is formed between the gate electrodes in the memory cell region, and the sidewall insulating film 22 is formed on the side surface of the gate electrode in the peripheral circuit region.
b is formed.

Next, as shown in FIG. 23, a resist 23 is formed and patterned on the first insulating film 12 and the second electrode material 18. Using the patterned resist 23 as a mask, ion implantation is performed using As as an impurity, for example. Then, the introduced impurities are diffused by heat treatment to form the second conductive layer 18a in the memory cell region, and the first and second conductive layers 13b, 18b and the N ⁺ type source in the NMOS region. / Drain diffusion layer 24 is formed. Where NMO
The first conductive layer 13b in the S region diffuses the impurities introduced into the second electrode material 18 in the NMOS region from the opening 31 of the third insulating film 17 into the first electrode material 13 in the NMOS region. Formed by. After the above steps, the resist 23 is removed.

Next, as shown in FIG. 24, a resist 25 is formed and patterned on the first insulating film 12 and the second electrode material 18. Ion implantation is performed using, for example, B as an impurity using the patterned resist 25 as a mask. Then, the introduced impurities are diffused by heat treatment, so that in the PMOS region, the first and second conductive layers 13c and 18c, the P ⁺ -type source /
The drain diffusion layer 26 is formed. Here, the first conductive layer 13c in the PMOS region transfers impurities introduced into the second electrode material 18 in the PMOS region from the opening 31 of the third insulating film 17 to the first electrode material 13 in the PMOS region. It is formed by diffusing. After the above process, the resist 25
Are removed.

Next, as shown in FIG. 15, on the second conductive layer 18a in the memory cell region, the second conductive layers 18b and 18c in the peripheral circuit region, the source / drain diffusion layer 24 in the peripheral circuit region, 26 on the salicide films 27a, 27b,
27c are formed respectively.

According to the second embodiment, the same effect as that of the first embodiment can be obtained.

Further, in the peripheral transistors 29, 30, the first and second conductive layers 13b, 18b, 13c, 1
A third insulating film 17 having an opening 31 is provided between 8c. Therefore, at the end of the gate electrode, the first and second
It has a three-layer structure in which the third insulating film 17 is interposed between the conductive layers 13b, 18b, 13c and 18c. On the other hand, in the memory transistor, the first and second conductive layers 13 a, 1
It has a three-layer structure in which the third insulating film 17 is provided on the entire surface between 8a. Therefore, regarding the end portion of the gate electrode where the gate processing is performed, the peripheral transistors 29, 30 and the memory transistor 28 have the same gate laminated structure. Therefore, the gate processing can be simultaneously performed on the memory transistor 28 and the peripheral transistors 29 and 30 without changing the etching conditions.

[Third Embodiment] The third embodiment has the same structure as that of the second embodiment, but the first electrode material in the memory transistor and the peripheral transistor of the same conductivity type as this memory transistor. The difference is that they are made conductive at the same time.

25 to 35 are sectional views showing the steps of manufacturing a semiconductor memory device according to the third embodiment of the present invention.
The method of manufacturing the semiconductor memory device according to the third embodiment will be described below. In the method of manufacturing the semiconductor memory device according to the third embodiment, description of the same steps as those in the method of manufacturing the semiconductor memory device according to the first and second embodiments will be omitted, and only different steps will be described.

First, as shown in FIGS. 2 to 4, after the first electrode material 13 is formed on the first insulating film 12 as in the first embodiment, the element isolation insulating film 15 is removed. Element isolation region is formed.

Next, as shown in FIG. 25, a resist 16a is formed on the first electrode material 13, and the resist 16a is formed.
It is patterned so that a remains only on the PMOS region. Using the patterned resist 16a as a mask, ion implantation and heat treatment are performed on the first electrode material 13 in the memory cell region and the NMOS region to form the first conductive layers 13a and 13b. At this time, for example, P is used as the N-type impurity, the acceleration voltage is about several tens KeV,
Ion implantation is performed under the condition that the dose amount is about 10 ¹⁵ cm ^-2 . Reference numeral 13a indicates a first conductive layer in the memory cell area, and reference numeral 13b indicates a first conductive layer in the NMOS area. After that, the resist 16a is removed.

Next, as shown in FIG. 26, a resist 16 is formed on the first electrode material 13 and the first conductive layers 13a and 13b.
b is formed, and the resist 16b is patterned so as to remain only on the memory cell region and the NMOS region. Using the patterned resist 16b as a mask, ion implantation and heat treatment are performed on the first electrode material 13 in the PMOS region to form the first conductive layer 13c. At this time, for example, B is used as the P-type impurity,
Ion implantation is performed under the conditions of an accelerating voltage of about ten KeV and a dose of about 10 ¹⁵ cm ^-2 . After that, the resist 16b
Are removed.

Next, as shown in FIG. 27, on the first conductive layers 13a, 13b and 13c and the element isolation insulating film 15,
For example, the third insulating film 17 made of an ONO film is deposited. Next, the third insulating film 17 in the peripheral circuit region is selectively removed to form the opening 31.

Next, as shown in FIG. 28, a second electrode material 18 is deposited on the third insulating film 17, the first conductive layers 13b and 13c and the element isolation insulating film 15. Here, the second electrode material 18 is made of polysilicon having no impurities introduced therein.

Next, as shown in FIG. 29, a resist 19 is formed on the second electrode material 18 and patterned. The second electrode material 18, the third insulating film 17, and the first conductive layers 13a, 13b, 13c are removed by using the patterned resist 19 as a mask. As a result, gate patterns of the memory transistor and the peripheral transistor are formed.

Next, as shown in FIG. 30, a resist 19 is formed.
Are removed. Next, post-oxidation is performed to form an oxide film (not shown) on the gate.

Next, as shown in FIG. 31, the first insulating film
A resist 20 is formed on the second electrode material 18 and the second electrode material 18.
Is patterned. This patterned register
Ion implantation is performed using the mask 20 as a mask,
N in the semiconductor substrate 11 in the region ⁺Type source / drain expansion
The diffused layer 21 is formed. After that, the resist 20 is removed.
Be done.

Next, as shown in FIG. 32, a fourth insulating film 22 is formed on the first insulating film 12 and the second electrode material 18 so as to satisfy the relationship of the formula (1).

Next, as shown in FIG. 33, the fourth insulating film 22 is etched back to expose the surface of the second electrode material 18 and the first insulating film 12 or the diffusion layer region of the peripheral transistor. . Thus, the buried insulating film 22a is formed between the gate electrodes in the memory cell region, and the sidewall insulating film 22 is formed on the side surface of the gate electrode in the peripheral circuit region.
b is formed.

Next, as shown in FIG. 34, a resist 23 is formed on the first insulating film 12 and the second electrode material 18, and the resist 23 is patterned so as to remain on the PMOS region. This patterned resist 2
Using 3 as a mask, ion implantation is performed using As as an impurity, for example. Then, the introduced impurities are diffused by heat treatment, so that the second impurities are formed in the memory cell region.
Conductive layer 18a of the N ⁺ type source / drain diffusion layer 2 is formed in the NMOS region.
4 is formed. Then, the resist 23 is removed.

Next, as shown in FIG. 35, a resist 25 is formed on the first insulating film 12 and the second electrode material 18, and patterned so that the resist 25 remains on the memory cell region and the NMOS region. To be done. Ion implantation is performed using, for example, B as an impurity using the patterned resist 25 as a mask. Then, the introduced impurities are diffused by heat treatment to form the second conductive layer 18c and the P ⁺ -type source / drain diffused layer 26 in the PMOS region. Then resist 25
Are removed.

Next, as shown in FIG. 15, as in the second embodiment, on the second conductive layer 18a in the memory cell region,
Salicide films 27a, 27b, and 27c are formed on the second conductive layers 18b and 18c in the peripheral circuit region and on the source / drain diffusion layers 24 and 26 in the peripheral circuit region, respectively.

According to the third embodiment, the same effects as those of the first and second embodiments can be obtained.

Further, the first electrode material 13 in the memory transistor 28 and the peripheral transistor 29 is made conductive at the same time. Therefore, the number of manufacturing steps can be reduced and the manufacturing can be facilitated.

When the memory transistor 28 is P-type, the first electrode material 13 in the memory cell region is P-type.
It suffices that the first electrode material 13 in the MOS region is made conductive at the same time.

[Fourth Embodiment] The fourth embodiment is the same as the structure of the third embodiment, except that the first electrode material having conductivity is used from the beginning.

36 to 39 are sectional views showing the steps of manufacturing a semiconductor memory device according to the fourth embodiment of the present invention.
The method of manufacturing the semiconductor memory device according to the fourth embodiment will be described below. In the method of manufacturing the semiconductor memory device according to the fourth embodiment, description of steps similar to those of the method of manufacturing the semiconductor memory device according to the third embodiment will be omitted.
Only different steps will be described.

First, as shown in FIG. 36, the semiconductor substrate 1
A first insulating film 12 to be a gate insulating film is formed on
It Next, impurities are introduced into the first insulating film 12.
N ⁺A first conductive layer 41 of the mold is formed and the first conductive layer 41 is formed.
The second insulating film 14 made of a silicon nitride film is formed on the conductive layer 41.
Are deposited.

Next, as shown in FIG. 37, the second insulating film 14, the first conductive layer 41, the first insulating film 12 and the semiconductor substrate 11 are selectively removed to form a device isolation groove. To be done. An element isolation insulating film 15 made of a silicon oxide film is deposited in the element isolation groove, and the element isolation insulating film 1 is formed.
5 is flattened until the surface of the second insulating film 14 is exposed. In this way, S made of the element isolation insulating film 15 is formed.
An element isolation region having a TI structure is formed.

Next, as shown in FIG. 38, part of the element isolation insulating film 15 is etched so that the surface of the element isolation insulating film 15 is located below the surface of the first conductive layer 41. Then, the second insulating film 14 is peeled off.

Next, as shown in FIG. 39, a resist 16 is formed on the first conductive layer 41, and the resist 16 is patterned so as to remain only on the memory cell region and the NMOS region. This patterned resist 1
Using 6 as a mask, ion implantation and heat treatment are performed on the first conductive layer 41 in the PMOS region to form the P ⁺ -type first conductive layer 42. At this time, for example, B is used as the P-type impurity, and the ion implantation is performed under the conditions that the acceleration voltage is about ten and several KeV and the dose amount is about 10 ¹⁵ cm ⁻² . The dose amount of impurities in the step shown in FIG. 39 is about twice the dose amount of impurities in first conductive layer 41.
Next, the resist 16 is removed.

After that, as in the third embodiment, as shown in FIG.
Through the steps shown in FIG. 35 to FIG. 35, a semiconductor memory device as shown in FIG. 15 is formed.

According to the above-mentioned fourth embodiment, the same effects as those of the first and second embodiments can be obtained.

Furthermore, the step of making the first electrode material 13 conductive in the memory cell region and the NMOS region can be omitted. Therefore, the number of manufacturing steps can be reduced and the manufacturing can be facilitated.

[Fifth Embodiment] The fifth embodiment is an example of a semiconductor memory device in which a selection transistor for controlling a memory transistor is arranged near the memory transistor.

40 and 41 are sectional views of a semiconductor memory device according to the fifth embodiment of the present invention. Here, FIG.
0 is a structure in which an insulating film is not formed between the first and second conductive layers of the selection transistor, and FIG. 40 is a structure in which an insulating film having an opening is formed between the first and second conductive layers of the selection transistor. is there. The semiconductor memory device according to the fifth embodiment will be described below. In the semiconductor memory device according to the fifth embodiment, description of structures similar to those of the semiconductor memory devices according to the first to fourth embodiments is omitted.
Only different structures will be described.

As shown in FIGS. 40 and 41, in the semiconductor memory device according to the fifth embodiment, select transistors are arranged near the memory transistors. In these memory transistors and select transistors, an insulating film 22a is formed between the gates, and the insulating film 22a covers the surface of the diffusion layer 21. Therefore, the salicide films 27a are formed on the gates, but the diffusion layers 21a
No salicide film is formed on top. Further, the gate of the memory transistor and the gate of the selection transistor may be arranged with the above-mentioned first distance X.

According to the fifth embodiment, the same effect as that of the first and second embodiments can be obtained.

In addition, the present invention is not limited to each of the above-described embodiments, and can be variously modified at the stage of implementation without departing from the spirit of the invention. further,
The embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some components are deleted from all the components shown in the embodiment,
When the problem described in the column of the problem to be solved by the invention can be solved and the effect described in the column of the effect of the invention can be obtained, a configuration in which this constituent element is deleted can be extracted as the invention.

[0100]

As described above, according to the present invention, it is possible to prevent the reliability of device characteristics from being deteriorated and to improve the degree of freedom in designing a memory cell device, and a manufacturing method thereof. Can be provided.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing a manufacturing process of the semiconductor memory device according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view showing the manufacturing process of the semiconductor memory device according to the first embodiment of the present invention, following FIG. 2;

FIG. 4 is a cross-sectional view showing the manufacturing process of the semiconductor memory device according to the first embodiment of the present invention, following FIG. 3;

FIG. 5 is a cross-sectional view showing the manufacturing process of the semiconductor memory device according to the first embodiment of the present invention, following FIG. 4;

FIG. 6 is a cross-sectional view showing the manufacturing process of the semiconductor memory device according to the first embodiment of the present invention, following FIG. 5;

FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor memory device according to the first embodiment of the present invention, following FIG. 6;

FIG. 8 is a cross-sectional view showing the manufacturing process of the semiconductor memory device according to the first embodiment of the present invention, following FIG. 7;

9 is a cross-sectional view showing the manufacturing process of the semiconductor memory device according to the first embodiment of the present invention, following FIG. 8;

FIG. 10 is a cross-sectional view showing the manufacturing process of the semiconductor memory device according to the first embodiment of the present invention, following FIG. 9;

11 is a cross-sectional view showing the semiconductor memory device according to the first embodiment of the present invention following FIG.

FIG. 12 is a cross-sectional view showing the manufacturing process of the semiconductor memory device according to the first embodiment of the present invention, following FIG. 11;

FIG. 13 is a cross-sectional view showing the manufacturing process of the semiconductor memory device according to the first embodiment of the present invention, following FIG. 12;

FIG. 14 is a cross-sectional view showing the manufacturing process of the semiconductor memory device according to the first embodiment of the present invention, following FIG. 13;

FIG. 15 is a sectional view showing a semiconductor memory device according to a second embodiment of the present invention.

16 is a cross-sectional view showing the manufacturing process of the semiconductor memory device according to the second embodiment of the present invention, following FIG. 5;

FIG. 17 is a cross-sectional view showing the manufacturing process of the semiconductor memory device according to the second embodiment of the present invention, following FIG. 16;

FIG. 18 is a cross-sectional view showing the manufacturing process of the semiconductor memory device according to the second embodiment of the present invention, following FIG. 17;

FIG. 19 is a cross-sectional view showing the manufacturing process of the semiconductor memory device according to the second embodiment of the present invention, following FIG. 18;

FIG. 20 is a cross-sectional view showing the manufacturing process of the semiconductor memory device according to the second embodiment of the present invention, which is subsequent to FIG. 19;

FIG. 21 is a cross-sectional view showing the semiconductor memory device according to the second embodiment of the present invention subsequent to FIG. 20;

FIG. 22 is a cross-sectional view showing the manufacturing process of the semiconductor memory device according to the second embodiment of the present invention, which is subsequent to FIG. 21;

FIG. 23 is a cross-sectional view showing the manufacturing process of the semiconductor memory device according to the second embodiment of the present invention, which is subsequent to FIG. 22;

FIG. 24 is a cross-sectional view showing the manufacturing process of the semiconductor memory device according to the second embodiment of the present invention, which is subsequent to FIG. 23;

FIG. 25 is a cross-sectional view showing the manufacturing process of the semiconductor memory device according to the third embodiment of the present invention, following FIG. 4;

FIG. 26 is a cross-sectional view showing the manufacturing process of the semiconductor memory device according to the third embodiment of the present invention, which is subsequent to FIG. 25;

FIG. 27 is a cross-sectional view showing the manufacturing process of the semiconductor memory device according to the third embodiment of the present invention, which is subsequent to FIG. 26;

FIG. 28 is a cross-sectional view showing the manufacturing process of the semiconductor memory device according to the third embodiment of the present invention, following FIG. 27;

FIG. 29 is a cross-sectional view showing the manufacturing process of the semiconductor memory device according to the third embodiment of the present invention, following FIG. 28;

FIG. 30 is a cross-sectional view showing the manufacturing process of the semiconductor memory device according to the third embodiment of the present invention, which is subsequent to FIG. 29;

FIG. 31 is a cross-sectional view showing the semiconductor memory device according to the third embodiment of the present invention, following FIG. 30;

FIG. 32 is a cross-sectional view showing the manufacturing process of the semiconductor memory device according to the third embodiment of the present invention, following FIG. 31;

FIG. 33 is a cross-sectional view showing the manufacturing process of the semiconductor memory device according to the third embodiment of the present invention, which is subsequent to FIG. 32;

FIG. 34 is a cross-sectional view showing the manufacturing process of the semiconductor memory device according to the third embodiment of the present invention, which is subsequent to FIG. 33;

FIG. 35 is a cross-sectional view showing the manufacturing process of the semiconductor memory device according to the third embodiment of the present invention, following FIG. 34;

FIG. 36 is a cross-sectional view showing the manufacturing process of the semiconductor memory device according to the fourth embodiment of the present invention.

FIG. 37 is a cross-sectional view showing the manufacturing process of the semiconductor memory device according to the fourth embodiment of the present invention, which is subsequent to FIG. 36;

FIG. 38 is a cross-sectional view showing the manufacturing process of the semiconductor memory device according to the fourth embodiment of the present invention, which is subsequent to FIG. 37;

FIG. 39 is a cross-sectional view showing the manufacturing process of the semiconductor memory device according to the fourth embodiment of the present invention, which is subsequent to FIG. 38;

FIG. 40 is a sectional view showing a semiconductor memory device according to a fifth embodiment of the present invention.

FIG. 41 is a cross-sectional view showing another semiconductor memory device according to the fifth embodiment of the present invention.

FIG. 42 is a cross-sectional view showing the manufacturing process of the semiconductor memory device according to the conventional technique.

FIG. 43 is a cross-sectional view showing the manufacturing process of the conventional semiconductor memory device, following FIG. 42;

FIG. 44 is a cross-sectional view showing the manufacturing process of the conventional semiconductor memory device, following FIG. 43;

45 is a cross-sectional view showing the manufacturing process of the semiconductor memory device according to the prior art, which is subsequent to FIG. 44;

FIG. 46 is a cross-sectional view showing the manufacturing process of the semiconductor memory device according to the prior art, which is subsequent to FIG. 45;

FIG. 47 is a cross-sectional view showing the manufacturing process of the semiconductor memory device according to the prior art, which is subsequent to FIG. 46;

48 is a cross-sectional view showing the manufacturing process of the conventional semiconductor memory device, following FIG. 47;

49 is a cross-sectional view showing the manufacturing process of the conventional semiconductor memory device, following FIG. 48;

50 is a cross-sectional view showing the manufacturing process of the conventional semiconductor memory device, following FIG. 49;

[Explanation of symbols]

11 ... Semiconductor substrate, 12 ... First insulating film, 13 ... First electrode material, 13a, 13b, 13c, 41, 42 ... First conductive layer, 14 ... Second insulating film, 15 ... Element isolation insulation Film, 16, 16a, 16b, 19, 20, 23, 25 ... Resist, 17 ... Third insulating film, 18 ... Second electrode material, 18a, 18b, 18c ... Second conductive layer, 21, 24 ... N ⁺ type source / drain diffusion layer, 22 ... Fourth insulating film, 22a ... Buried insulating film, 22b ... Side wall insulating film, 26 ... P ⁺ type source / drain diffusion layer, 27a, 27b, 27c, 27d ... Salicide film, 28 ... Memory transistor, 29, 30 ... Peripheral transistor, 31 ... Opening part.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 29/788 29/792 (72) Inventor Riichiro Shirata 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Stock company F term in Toshiba Yokohama office (reference) 5F048 AB01 AC03 BA01 BB06 BB07 BB08 BB12 BB13 BC06 BF06 BF16 BG01 BG13 DA25 5F083 EP02 EP22 EP23 EP33 EP34 EP55 EP56 EP76 GA02 JA35 JA53 NA01 NA06 PR36 PR39 PR43 PR44 BA29 PR36 PR02 PR53 BA54 5 BD22 BD24 BD34 BD35

Claims (45)

[Claims] 1. A semiconductor memory device comprising a memory cell region having a first gate electrode and a peripheral circuit region having a second gate electrode, the semiconductor memory device having a first interval on a semiconductor substrate. The first arranged
A second gate electrode arranged on the semiconductor substrate with a second gap wider than the first gap; and inside the semiconductor substrate with the first gate electrode interposed therebetween. A formed first diffusion layer, a second diffusion layer formed in the semiconductor substrate with the second gate electrode interposed therebetween, and a first insulating film formed on the first diffusion layer A second insulating film formed on a side surface of the second gate electrode, and a silicide film formed on each of the first gate electrode, the second gate electrode and the second diffusion layer. A semiconductor memory device comprising: 2. Where X is the first interval, Y is the second interval, and A is the film thickness when the first and second insulating films are formed, X / 2 ≦ A <Y / The semiconductor memory device according to claim 1, wherein the relationship of 2 is satisfied. 3. The second interval is 1.3 to 5.0 times greater than the first interval.
The semiconductor memory device described. 4. The semiconductor memory device according to claim 1, wherein the first gate electrode and the second gate electrode are arranged with the second gap. 5. The semiconductor memory device according to claim 1, wherein the first insulating film fills a space between the first gate electrodes. 6. The semiconductor memory device according to claim 1, wherein the first and second insulating films are made of the same material. 7. The semiconductor memory device according to claim 1, wherein the first and second insulating films are oxide films. 8. The first and second insulating films are a silicon oxide film, a TEOS film, an ozone TEOS film, an HTO film, and an S film.
2. The semiconductor memory device according to claim 1, comprising an OG film, a coating type organic oxide film, an SA-CVD film, a plasma CVD film, or a PSG film. 9. The semiconductor memory device according to claim 1, wherein the silicide film is a cobalt silicide film or a titanium silicide film. 10. The semiconductor memory device according to claim 1, wherein the silicide film is a salicide film. 11. The first gate electrode comprises a first conductive layer formed on the semiconductor substrate via a third insulating film, and a fourth conductive layer formed on the first conductive layer. An insulating film and a second conductive layer formed on the fourth insulating film, wherein the second gate electrode is formed on the semiconductor substrate via a fifth insulating film. 2. The semiconductor memory device according to claim 1, further comprising: a conductive layer of 4 and a fourth conductive layer formed on the third conductive layer. 12. The first conductive layer and the third conductive layer,
12. The semiconductor memory device according to claim 11, wherein the second conductive layer and the fourth conductive layer are the same layer. 13. A sixth insulating film is formed between the third and fourth conductive layers in the second gate electrode, and the sixth insulating film is one of the third and fourth conductive layers. The semiconductor memory device according to claim 11, wherein the semiconductor memory device has an opening through which the portion is electrically connected. 14. The semiconductor memory device according to claim 13, wherein the opening of the sixth insulating film is located in the center between the third and fourth conductive layers. 15. The semiconductor memory device according to claim 13, wherein a plurality of the openings of the sixth insulating film are provided between the third and fourth conductive layers. 16. The semiconductor memory according to claim 11, wherein in the first gate electrode, the first conductive layer functions as a floating gate and the second conductive layer functions as a control gate. apparatus. 17. The second gate electrode is disposed in the vicinity of the second gate electrode, the silicide film is formed on a surface thereof, the second insulating film is formed on a side surface of the second gate electrode, and the second conductive film has a conductivity type different from that of the second gate electrode. 3. A gate electrode of No. 3 and a third diffusion layer, which is formed in the semiconductor substrate with the third gate electrode interposed therebetween and has the silicide film formed on the surface thereof. The semiconductor memory device described. 18. The semiconductor memory device according to claim 17, wherein the second gate electrode and the third gate electrode are arranged with the second gap. 19. A fourth gate electrode disposed in the vicinity of the first gate electrode and having the silicide film formed on the surface thereof, and formed in the semiconductor substrate with the fourth gate electrode interposed therebetween. The semiconductor memory device according to claim 1, further comprising a fourth diffusion layer having a surface on which the first insulating film is formed. 20. The semiconductor memory device according to claim 19, wherein the first gate electrode and the fourth gate electrode are arranged with the first gap. 21. The semiconductor memory device according to claim 1, wherein the first gate electrode is a floating gate electrode in a memory cell region of a NAND flash memory. 22. The fourth gate electrode is a gate electrode of a selection transistor.
The semiconductor memory device described. 23. A method of manufacturing a semiconductor memory device, comprising: a memory cell region having a first gate electrode; and a peripheral circuit region having a second gate electrode, wherein the first memory device has a first gap. The gate electrode of the first
Forming on the semiconductor substrate the second gate electrode having a second gap wider than the gap between the first gate electrode and the first gate electrode in the semiconductor substrate.
A step of forming a diffusion layer, a step of forming a first insulating film on the first diffusion layer and on a side surface of the second gate electrode, and in the semiconductor substrate sandwiching the second gate electrode. To the second
And a step of forming a silicide film on the first gate electrode, on the second gate electrode, and on the second diffusion layer, respectively. Device manufacturing method. 24. A memory cell region having a first gate electrode made of first and second conductive layers, and a peripheral circuit region having a second gate electrode made of third and fourth conductive layers. And a step of forming a first insulating film on a semiconductor substrate, and a step of forming a first electrode material on which impurities are not introduced on the first insulating film. Forming an element isolation region formed of an element isolation insulating film in the first electrode material, the first insulating film, and the semiconductor substrate; and ion implantation into the first electrode material in the memory cell area. And a step of forming the first conductive layer by performing heat treatment, a step of forming a second insulating film on the first conductive layer, the second insulating film and the first conductive layer. Form a second electrode material on which no impurities have been introduced A step of removing the first and second electrode materials, the first conductive layer, and the second insulating film, and forming a pattern of the first gate electrode having a first gap, Forming a pattern of the second gate electrode having a second gap wider than the gap between the first gate electrode and the first gate electrode in the semiconductor substrate with the first gate electrode interposed therebetween.
A step of forming a diffusion layer, a step of forming a third insulating film on the first diffusion layer and on a side surface of the second gate electrode, and by performing ion implantation and heat treatment, The second conductive layer is formed on the conductive layer, and the third and fourth conductive layers are formed.
And forming a second diffusion layer in the semiconductor substrate, and forming a silicide film on the second conductive layer, the fourth conductive layer and the second diffusion layer. A method of manufacturing a semiconductor memory device, comprising: 25. A memory cell region having a first gate electrode formed of first and second conductive layers, a second gate electrode formed of third and fourth conductive layers, and fifth and sixth conductive layers. A method of manufacturing a semiconductor memory device, comprising: a third gate electrode made of a layer; and a peripheral circuit region having a layer, the method comprising: forming a first insulating film on a semiconductor substrate; and forming a first insulating film on the first insulating film. A step of forming a first electrode material in which impurities are not introduced, a step of forming an element isolation region made of an element isolation insulating film in the first electrode material, the first insulating film and the semiconductor substrate, Forming the first conductive layer by performing ion implantation and heat treatment on the first electrode material in the memory cell region; and forming a second insulating film on the first conductive layer. On the second insulating film and the first conductive material A step of forming a second electrode material in which no impurities are introduced, and removing the first and second electrode materials, the first conductive layer, and the second insulating film to form a first gap. Forming the first gate electrode pattern having and the second and third gate electrode patterns having a second gap wider than the first gap; and sandwiching the first gate electrode between the first and second gate electrode patterns. First in semiconductor substrate
And a step of forming a third insulating film on the first diffusion layer and on the side surfaces of the second and third gate electrodes, and by performing ion implantation and heat treatment, The second conductive layer is formed on the first conductive layer, and the third and fourth conductive layers are formed.
And forming a second diffusion layer in the semiconductor substrate, and performing ion implantation and heat treatment to form the fifth and sixth conductive layers, and in the semiconductor substrate. Forming a third diffusion layer on the second conductive layer, a silicide film on the second conductive layer, the fourth conductive layer, the sixth conductive layer, the second diffusion layer and the third diffusion layer. And a step of forming the semiconductor memory device. 26. When the first interval is X, the second interval is Y, and the film thickness when the third insulating film is formed is A, a relationship of X / 2 ≦ A <Y / 2 is satisfied. 26. The method of manufacturing a semiconductor memory device according to claim 24 or 25, wherein 27. The second interval is 2 to 3 times as large as the first interval.
5. The method for manufacturing a semiconductor memory device according to 5. 28. The third insulating film fills a space between the first gate electrodes.
25. A method of manufacturing a semiconductor memory device according to item 25. 29. The method of manufacturing a semiconductor memory device according to claim 24, wherein the third insulating film is an oxide film. 30. The third insulating film is a silicon oxide film, a TEOS film, an ozone TEOS film, an HTO film, an SOG.
26. The method of manufacturing a semiconductor memory device according to claim 24, comprising a film, a coating type organic oxide film, an SA-CVD film, a plasma CVD film, or a PSG film. 31. The method of manufacturing a semiconductor memory device according to claim 24, wherein the silicide film is a cobalt silicide film or a titanium silicide film. 32. The method of manufacturing a semiconductor memory device according to claim 24, wherein the silicide film is a salicide film. 33. The method of manufacturing a semiconductor memory device according to claim 24, wherein the first gate electrode is a floating gate electrode in a memory cell region of a NAND flash memory. 34. In the first gate electrode, the first conductive layer functions as a floating gate, and the second conductive layer functions as a control gate. Manufacturing method of semiconductor memory device. 35. The surface of the element isolation insulating film is positioned below the surface of the first electrode material by removing a part of the element isolation insulating film after forming the element isolation region. 26. The method for manufacturing a semiconductor memory device according to claim 24. 36. The method of manufacturing a semiconductor memory device according to claim 24, wherein the third insulating film having an opening is formed between the third and fourth conductive layers. 37. The third insulating film having an opening is formed between the third and fourth conductive layers and between the fifth and sixth conductive layers, respectively. Manufacturing method of semiconductor memory device. 38. The semiconductor memory device according to claim 36, wherein the opening of the third insulating film is located in the center between the third and fourth conductive layers. 39. The opening of the third insulating film is located in the center between the third and fourth conductive layers and between the fifth and sixth conductive layers, respectively. The semiconductor memory device described. 40. The semiconductor memory device according to claim 36, wherein a plurality of the openings of the third insulating film are provided between the third and fourth conductive layers. 41. The plurality of openings of the third insulating film are provided between the third and fourth conductive layers and between the fifth and sixth conductive layers. Semiconductor memory device. 42. When the first gate electrode and the second gate electrode are of the same conductivity type, the third conductive layer is formed at the same time when the first conductive layer is formed. 26. The method of manufacturing a semiconductor memory device according to claim 24 or 25. 43. The first conductive layer of the first gate electrode and the third conductive layer of the second gate electrode are formed using a conductive material having impurities introduced thereinto. 25. The method of manufacturing a semiconductor memory device according to claim 24. 44. The first conductive layer of the first gate electrode and the third conductive layer of the second gate electrode are made of a conductive material into which an impurity of the first conductivity type has been introduced in advance. 26. The method of manufacturing a semiconductor memory device according to claim 25, wherein the fifth conductive layer of the third gate electrode is formed by introducing an impurity of the second conductivity type into the conductive material. . 45. The method of manufacturing a semiconductor memory device according to claim 44, wherein the first conductivity type is N type and the second conductivity type is P type.