JP2007095251A - Optical disk reproducing device and optical disk recorder - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an optical disk reproducing device capable of performing error correction processing in two different directions and the generation processing of an error correction code, and an optical disk recorder capable of generating the error correction code capable of accelerating the error correction processing. <P>SOLUTION: The optical disk reproducing device is provided with a disk motor 1, a pickup 2, a servo processing part 3, a system controller 4, a memory controller 5, a memory 6, a demodulation part 7, an error correction part 8, an error correction buffer 9, a descramble - EDC part 10, a host I/F part 11 and a host computer 12. Since the error correction of a PO sequence is performed with partial block data composed of the data of L bytes in a PI code direction and N pieces in a PO code direction as a unit from the correction buffer 9, the frequency of access to the memory 6 is reduced and the error correction processing is performed at a high speed. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an optical disc reproducing apparatus and an optical disc recording apparatus having an error correction function.

  DVD records data in units of ECC blocks. The ECC block is configured by 192 pieces of data having a length of 172 bytes in the row direction arranged in the column direction. An error correction code called PI parity is added to each row, and an error correction code called PO parity is added to each column.

  In recent years, there is a great need for high-speed recording / reproducing apparatuses for various optical discs such as DVDs, and it is common to use SDRAM which is easily available at high speed as a memory used for the recording / reproducing apparatus.

  SDRAM has a higher burst transfer speed than general-purpose DRAM, but the time from the input of an address to the output of the first data is not much different from that of general-purpose DRAM. DRAM reads out consecutive columns on the same row (row), and high-speed reading is possible without requiring precharge. However, when reading different rows, DRAM needs to be precharged and high-speed reading is possible. I can't. Therefore, when error correction using PI parity and PO parity is performed using DRAM, error correction using PI parity cannot be performed at high speed even though error correction using PI parity can be performed at high speed.

  In order to solve such a problem, an optical disk reproducing device including an error correction memory has been proposed (see Patent Document 1). In this device, data writing from the memory storing the ECC block to the error correction memory and PI series error correction processing in the error correction device are simultaneously performed, so that the data processing speed can be improved and the error correction memory can be improved. By providing, there is an advantage that the access amount to the memory storing the ECC block can be reduced. However, the capacity of the error correction memory needs to be at least one ECC block, which increases the circuit scale and the parts cost.

In addition, there has been proposed an optical disc reproducing apparatus in which an error correction apparatus that performs error correction using PI parity and an error correction apparatus that performs error correction using PO parity are separately provided (see Patent Document 2). Since two types of error correction devices are provided, the error correction processing can be speeded up, but the circuit scale increases. Also, since two error correction devices access the memory, while one error correction device is accessing the memory, the other error correction device cannot perform memory access at high speed, resulting in an error. There is a problem that the correction process cannot be accelerated.
Japanese Patent Laid-Open No. 9-265730 JP 2001-243729

  The present invention relates to an optical disc reproducing apparatus capable of performing high-speed error correction processing or error correction code generation processing in two different directions without increasing the circuit scale, and an error correction code capable of speeding up error correction processing. Is provided.

  According to one aspect of the present invention, M pieces of data (M is an integer of 2 or more) arranged in the first direction according to the reading order of data recorded on the optical disc, and the first direction different from the first direction. N pieces of data (N is an integer of 2 or more) arranged in two directions, a first error correction code used when error correction is performed in units of the M pieces of data, and the units of the N pieces of data A first storage means for temporarily storing an error correction block including a second error correction code used when error correction is performed as described above, and based on the first error correction code and the second error correction code An error correction unit that performs error correction of data read from the optical disc, and at least one of the error correction blocks stored in the first storage unit in order to perform error correction by the error correction unit A second storage means for temporarily storing a portion, and the first error correction code for performing error correction using the second error correction code in units of L × N (L is a positive integer smaller than M) data. There is provided an optical disc reproducing apparatus comprising: data transmission means for transmitting and receiving data between a storage means and the second storage means.

  According to one aspect of the present invention, M data (M is an integer of 2 or more) arranged in the first direction according to the recording order of data to be recorded on the optical disc, and the first direction Are N data (N is an integer of 2 or more) arranged in different second directions, a first error correction code used when error correction is performed in units of the M data, and the N data First storage means for temporarily storing an error correction block including a second error correction code used when error correction is performed in units of data; and the first error based on the M × N data An error correction code generation unit that generates a correction code and the second error correction code, and at least a part of the error correction block stored in the first storage unit is temporarily stored in order to perform processing by the error correction unit In A second storage means for storing, and the first storage means and the second storage for generating the second error correction code in units of L × N (L is a positive integer smaller than M) data. There is provided an optical disk recording apparatus comprising: data transmission means for transmitting / receiving data to / from the means.

  According to the present invention, error correction processing in two different directions or error correction code generation processing can be performed at high speed without increasing the circuit scale.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The present invention is applicable to various types of optical disks such as CDs and DVDs. Hereinafter, an optical disk reproducing apparatus and an optical disk recording apparatus for reproducing or recording a DVD will be described as an example.

  Before describing these devices in detail, the DVD recording format will be described. DVD manages data in units of sectors. FIG. 1 is a diagram showing a data format of one sector. One sector is composed of 172 bytes in the row direction (horizontal direction) and 12 rows in the column direction (vertical direction). At the head of each sector, a 4-byte ID representing a physical address, a 2-byte parity IED for the ID, and 6-byte copy management data CPR_MAI are provided, followed by 2048-byte main data. Has been. At the end of each sector, a 4-byte error detection code EDC (Error Detection Code) is added.

  An ECC block is formed by collecting 16 sectors as shown in FIG. The ECC block is a unit of writing to the optical disc. FIG. 2 is a diagram showing a data format of the ECC block. The ECC block is a two-dimensional array of 16-sector data (16 sectors × 12 rows × 172 bytes), and has 172 bytes × 192 rows of data.

  Each row of the ECC block is provided with a 10-byte PI code (RSC (182, 172, 11)), and each column is provided with a 16-byte PO code (RSC (208, 192, 17)). The PI code is an error correction code used for error correction of the corresponding row, and the PO code is an error correction code used for error correction of the corresponding column.

  Actually, as shown in FIG. 3, the PO code is arranged by interleaving one line at a time with respect to 12 lines of data. A predetermined synchronization pattern (Sync pattern) is added to each row data of the interleaved ECC block shown in FIG. 3, and each data is modulated from 8 bits to 16 bits to form a physical sector.

  FIG. 4 shows the data format of the physical sector. One row of data (172 bytes + 10 bytes = 182 bytes) shown in FIG. 3 is divided into two in the row direction, and a 32-bit synchronization pattern is added to each. Further, the divided data (182/2 = 91 bytes) is modulated from 8 bits to 16 bits, respectively, so that 91 × 16 = 1456 bits. The last line (13th line) of the physical sector is a PO code. A sync frame is generated by adding 32 bits of the sync pattern and 1456 bits of the divided data.

  When recording the physical sector of FIG. 4 on an optical disk, as shown in FIG. 5, each row is scanned from left to right to record each data.

(First embodiment)
FIG. 6 is a block diagram showing a schematic configuration of the optical disk reproducing apparatus according to the first embodiment of the present invention. 6 includes a disk motor 1, a pickup 2, a servo processing unit 3, a system controller 4, a memory controller 5, a memory 6, a demodulation unit 7, an error correction unit 8, and a correction buffer. 9, a descrambling / EDC unit 10, a host I / F unit 11, and a host computer 12.

  In response to a request from the system controller 4, the servo processing unit 3 controls the disc motor 1 to rotate the optical disc 13 at a desired speed, and controls the focus position and track position of the pickup 2 with respect to the optical disc 13.

  The reproduction signal read from the optical disc 13 by the pickup 2 is demodulated by the demodulator 7 and written to the memory 6 via the memory controller 5. The memory 6 is a DRAM, for example.

  After the reproduction data for 1 ECC (hereinafter referred to as 1 ECC block data) is stored in the memory 6, the first row data in the 1 ECC block data is stored in the correction buffer 9 via the memory controller 5. In the following, it is assumed that one ECC block data is composed of M pieces of data in the row direction (PI code direction) (M is an integer of 2 or more) and N pieces of data in the column direction (PO code direction).

  The error correction unit 8 performs PI series error correction in order from the first row in the ECC block data. For example, when error correction of the first line is performed, error correction is performed using a PI code included in the first line. While the error correction unit 8 is performing error correction, the memory controller 5 transfers the next row data from the memory 6 to the correction buffer 9. The error-corrected line data is overwritten in the correction buffer 9.

  Thereafter, until the error correction of the PI sequence for one ECC block is completed, the error correction of the PI sequence by the error correction unit 8 and the data transfer in units of rows from the memory 6 to the correction buffer 9 are performed in parallel. Eventually, the 1 ECC block data of which the PI sequence has been error-corrected is stored in the correction block.

  Next, the error correction unit 8 selects N pieces of L bytes (however, L <M) in the row direction (PI code direction) from the 1 ECC block data in which the PI sequence error has been corrected in the correction buffer 9 in the column direction. The PO series error correction processing is performed on the partial block data composed of the above data.

  FIG. 7 is a diagram showing an example of partial block data. The partial block data in FIG. 7 shows a case where L = 26. In this case, seven partial block data exist in one ECC block data. The error correction unit 8 sequentially performs PO series error correction on each of the partial block data.

  When the error correction unit 8 finishes PO-sequence error correction for one partial block data, the error correction unit 8 reads other partial block data that has not been corrected yet from the correction buffer 9 and performs PO-sequence error correction. At the same time, the error-corrected partial block data is transferred to the descrambling / EDC unit 10. The descrambling / EDC unit 10 descrambles the scrambled data and performs a final error check based on an EDC (Error Detection Code) added to the end of each sector data. Data processed by the descrambling / EDC unit 10 is stored in the memory 6 via the memory controller 5. The above processing is repeated until the PO series error-corrected data for the entire 1 ECC block data is stored in the memory 6.

  When the error correction processing and descrambling processing of the PO sequence for one ECC block is completed, data is then read from the memory 6 via the memory controller 5 at the required transfer rate, and the host I / F unit 11 To the host computer 12.

  FIG. 8 is an operation timing chart of error correction in the first embodiment. First, between time t1 and t2, data transfer from the memory 6 to the correction buffer 9 and PI series error correction processing are performed in parallel. Thereafter, during time t2 to t3, PO series error correction, descrambling / EDC processing, and storage in the memory 6 are performed in units of L × N partial block data.

  When a DRAM is used for the memory 6, it is desirable to assign the DRAM row direction to the row direction (PI code direction) in FIG. 5 and the DRAM column direction to the column direction (PO code direction) in FIG. Since DRAM can be read continuously from multiple columns on the same row without precharging, if data in the PI code direction (row direction) of one ECC block is stored in the row direction of DRAM, These data can be read out at high speed and transferred to the correction buffer 9. Even when descrambled / EDC-processed data is transferred to the memory 6 in units of partial block data, L-byte data in the row direction can be written at high speed. That is, when the descrambled / EDC processed data is transferred to the memory 6, the process of reading out L burst data at high speed may be repeated N times.

  In this embodiment, when PI series error correction is performed, data is transferred from the memory 6 to the correction buffer 9 in units of rows. Therefore, when the PO series error correction is started, data for one ECC block is stored in the correction buffer 9. Is stored. For this reason, the error correction unit 8 can perform PO series error correction processing using data in the correction buffer 9, and can reduce the frequency of access to the memory 6. In particular, if a high-speed memory 6 (SRAM or the like) is used as the correction buffer 9, the PO series error correction can be further accelerated.

  There is no particular limitation on the size of the data constituting the partial block data, and it can be set arbitrarily. For example, if the partial block data is 26 bytes in the PI code direction and 208 in the PO code direction, 7 partial block data of the same size can be obtained from 182 = 26 × 7, but 16 bytes in the PI code direction. Thus, assuming 208 in the PO code direction, 11 equal-sized blocks (16 × 208) and 1 small block (6 × 208) are obtained from 182 = 16 × 11 + 6. As described above, PO series error correction may be performed by combining a plurality of partial block data having different sizes.

  FIG. 9 is a detailed operation timing chart at times t1 to t2 in FIG. As shown in the figure, at time t11 to t12, the data of the first row is transferred from the memory 6 to the correction buffer 9, and thereafter at time t12 to t13, the error correction unit 8 uses the data transferred to the correction buffer 9. PI series error correction is performed, and at the same time, the next row of data is transferred from the memory 6 to the correction buffer 9. Thereafter, the same processing is repeated until the PI series error correction is completed for all of the 1 ECC block data.

  FIG. 10 is a detailed operation timing chart of the PO series error correction processing performed between times t2 and t3 in FIG. First, at time t21 to t22, PO series error correction is performed on the first partial block data, and then at time t22 to t23, descrambling / EDC processing is performed on the error-corrected partial block data. Later, the data is stored again in the memory 6. At the same time, PO series error correction is performed on the next partial block data.

  Since the correction buffer 9 of this embodiment has a memory capacity capable of storing 1 ECC block data, the partial block data for which PO series error correction has been completed is temporarily held in the correction buffer 9, and the timing is delayed. Descrambling / EDC processing may be performed.

  Similarly, in FIG. 9, the 1 ECC block data demodulated by the demodulator 7 is stored in the memory 6 and then immediately transferred to the correction buffer 9. However, the transfer from the memory 6 to the correction buffer 9 is performed. The timing to perform may be delayed. In addition, after the PO series error-corrected data is stored in the memory 6, the data transfer to the host computer 12 may be delayed instead of immediately transferring the data to the host computer 12.

  As described above, in the first embodiment, the correction buffer 9 for storing 1 ECC block data is provided separately from the memory 6 for storing 1 ECC block data, and L bytes and PO codes are provided from the correction buffer 9 in the PI code direction. Since PO series error correction is performed in units of partial block data consisting of N pieces of data in the direction, the frequency of access to the memory 6 can be reduced and the error correction process can be performed at high speed.

(Second Embodiment)
In the second embodiment, the memory capacity of the correction buffer 9 is reduced as compared with the first embodiment. The optical disk reproducing apparatus according to the second embodiment has the same block configuration as that of FIG. 1 except that the memory capacity of the correction buffer 9 is different. In the following, the differences from the first embodiment are mainly described. explain.

  The correction buffer 9 of this embodiment has a memory capacity capable of storing three partial block data. More specifically, the correction buffer 9 includes a first memory area for storing one partial block data transferred from the memory 6, and one partial block data for which the error correction unit 8 performs PO series error correction. And a third memory area for storing the error-corrected one partial block data.

  FIG. 11 is an operation timing chart of error correction in the second embodiment. First, between time t1 and time t2, the error correction unit 8 performs PI series error correction processing on 1 ECC block data stored in the memory 6. Since the PI series error correction processing is performed in units of one row of one ECC block data, the error correction processing may be performed after the data for one row is transferred to the correction buffer 9, or the error correction is performed without transferring the data. The unit 8 may directly read out data for one row from the memory 6 and perform error correction processing.

  When PI series error correction processing is completed for all 1 ECC block data, the first partial block data (hereinafter referred to as first partial block data) is transferred to the correction buffer 9 (time t2 to t3). Thereafter, the error correction unit 8 performs PO series error correction processing on the first partial block data stored in the correction buffer 9 (time t3 to t4). At the same time, the second partial block data (hereinafter referred to as second partial block data) is transferred from the memory 6 to the correction buffer 9. Thereafter, the PO partial error-corrected first partial block data is transmitted to the descrambling / EDC unit 10 (time t4 to t5). At the same time, the error correction unit 8 performs PO series error correction on the second partial block data in the correction buffer 9. At the same time, the third partial block data (hereinafter referred to as third partial block data) is transferred from the memory 6 to the correction buffer 9.

  Thereafter, the data transfer from the memory 6 to the correction buffer 9, the error correction by the error correction unit 8, and the data transfer from the correction buffer 9 to the descramble / EDC unit 10 are performed in parallel in the same procedure.

  In the first embodiment, since the PO series error correction is performed after the ECC block data is transferred to the correction buffer 9, it is not necessary to read out data from the memory 6 during the error correction. However, the correction buffer 9 needs to have a sufficient memory capacity. Since the correction buffer 9 often uses SRAM more expensive than DRAM, when the memory capacity increases, not only the circuit scale increases, but also the component cost increases. On the other hand, the correction buffer 9 of the present embodiment only needs to have a memory capacity sufficient to store three partial block data, so that the hardware scale and component cost can be reduced.

(Third embodiment)
In the third embodiment, the memory capacity of the correction buffer 9 is further reduced as compared with the second embodiment. The optical disk reproducing apparatus according to the third embodiment has the same block configuration as that of FIG. 1 except that the memory capacity of the correction buffer 9 is different. Hereinafter, differences from the first and second embodiments will be described. The explanation will be focused on.

  The correction buffer 9 of the present embodiment has a memory capacity capable of storing one partial block data (hereinafter, one partial block data). When performing PO series error correction, one partial block data is transferred from the memory 6 to the correction buffer 9. Then, after the transfer ends, one partial block data is read from the correction buffer 9 to perform error correction, and the corrected data is stored again in the correction buffer 9. After the error correction is completed, the error-corrected partial block data is transferred from the correction buffer 9 to the descrambling / EDC unit 10. After the PO series error correction processing for the one partial block data as described above is completed, the error correction processing for the next partial block data is performed.

  FIG. 12 is an operation timing chart of error correction in the third embodiment. First, during time t1 to t2, as in the second embodiment, PI series error correction is performed for each row of one ECC block data.

  When the PI series error correction is completed, the first partial block data is transferred from the memory 6 to the correction buffer 9 (time t2 to t3). After completion of the transfer to the correction buffer 9, the error correction unit 8 performs PO series error correction on the first partial block data in the correction buffer 9 (time t3 to t4). The error-corrected data is re-stored in the correction buffer 9. After completion of the error correction, the error-corrected first partial block data in the correction buffer 9 is transferred to the descrambling / EDC unit 10 (time t4 to t5).

  Thereafter, the second partial block data is transferred from the memory 6 to the correction buffer 9 this time between times t5 and t6. Thereafter, the same processing is repeatedly performed.

  As described above, in the third embodiment, partial block data is transferred from the memory 6 to the correction buffer 9 to perform PO series error correction, and then transferred to the descramble / EDC unit 10, and then the next partial Work on block data error correction. That is, after the error correction processing for one partial block data is completed, the next partial block data is processed. For this reason, the correction buffer 9 needs only to have a memory capacity for storing one partial block data, and the circuit scale and component cost can be reduced. However, since the memory 6 needs to be accessed every time the PO series error correction is performed on each partial block data, the access frequency of the memory 6 is increased, and the entire processing time may be increased.

(Fourth embodiment)
In the first to third embodiments described above, the optical disk reproducing apparatus has been described. However, the fourth to sixth embodiments described below relate to an optical disk recording apparatus.

  FIG. 13 is a block diagram showing a schematic configuration of an optical disk recording apparatus according to the fourth embodiment of the present invention. The optical disk recording apparatus of FIG. 13 includes a disk motor 21, a pickup 22, a servo processing unit 23, a system controller 24, a memory controller 25, a memory 26, a modulation unit 27, a parity adding unit 28, and column data. A buffer 29, a scramble / EDC unit 30, a host I / F unit 31, and a host computer 32 are provided.

  The memory controller 25 stores data supplied from the host computer 32 via the host I / F unit 31 in the memory 26. When data for one ECC block (hereinafter referred to as 1ECC block data) is stored in the memory 26, thereafter, one part of the ECC block data stored in the memory 26 is L bytes in the PI code direction and N parts in the PO code direction. The block data is read and transferred to the scramble / EDC unit 30.

  The scramble / EDC unit 30 performs scramble processing, stores the processed data in the column data buffer 29, and performs EDC calculation. When one partial block data has been stored in the column data buffer 29, the parity adding unit 28 performs a PO-sequence parity adding process on the scrambled one partial block data stored in the column data buffer 29. In parallel with this, partial block data that has not yet been transferred to the column data buffer 29 is read from the memory 26 via the memory controller 25 and transferred to the scramble / EDC unit 30. Then, the partial block data after the scramble processing is stored in the column data buffer 29 and EDC calculation is performed.

  The above process, that is, the process of performing the PO sequence parity addition process for each partial block data read from the memory 26 and storing it in the column data buffer 29 is repeated for one ECC block.

  When the PO sequence parity addition processing is completed for the data for one ECC block, the parity addition unit 28 performs the PI sequence parity addition processing on the PI code of the data in the first row among the data in the column data buffer 29. The memory controller 25 reads the data for which the PI series and PO series parity addition processing has been completed in the column data buffer 29 and stores it in the memory 26.

  When the parity addition processing of the PI sequence of the first row and the transfer to the memory 26 are completed, the parity addition unit 28 performs the PI sequence parity addition processing on the PI code of the next row of data in the column data buffer 29, The processed data is stored in the memory 26.

  The above processing is repeated for all data for one ECC block until the PO sequence and PI sequence parity addition processing is completed and the processed data is stored in the memory 26.

  After that, the modulation unit 27 reads the PI series and PO series data that has been subjected to the parity addition processing stored in the memory 26 via the memory controller 25 and performs modulation processing. The recording data after the modulation processing is recorded on the optical disc 13 via the pickup 22.

  If DRAM is used as the memory 26, the PI code of one ECC block is arranged in the DRAM column direction, and the PO code is arranged in the DRAM row direction, data transfer between the memory 26 and the column data buffer 29 is performed in a burst of L bytes. Can be done by transfer. As a result, it is not necessary to frequently access the memory 26 during the error correction process, and the memory access speed can be increased.

  In addition, the data transfer process from the memory 26 to the column data buffer 29 and the PO-sequence parity addition process can be performed in parallel in units of partial block data in one ECC block. Similarly, PI series parity addition processing and data transfer processing from the column data buffer 29 to the memory 26 can be performed in parallel in units of one row. Thereby, the parity addition process can be speeded up.

  Note that the number of bytes in the PI code direction of the partial block data is not necessarily a constant value. For example, if the partial block data is 26 bytes in the PI code direction and 208 bytes in the PO code direction, seven equal-sized blocks (26 × 208 bytes) are obtained from 182 = 26 × 7. Assuming 16 bytes in the direction and 208 bytes in the PO code direction, 11 equal-sized blocks (16 × 208) and 1 small block (6 × 208) are obtained from 182 = 16 × 11 + 6. Thus, it may be composed of partial block data of the same size, or a plurality of types of partial block data having different sizes may be combined.

  FIG. 14 is an operation timing chart of the parity addition processing in the fourth embodiment. This operation timing chart shows an example in which seven pieces of partial block data having an equal size (26 bytes in the PI code direction and 208 bytes in the PO code direction) are used.

  From time t1 to t2, the processing for storing the data for one ECC block stored in the memory 26 in the column data buffer 29 by performing the PO-sequence parity addition processing for each partial block data. Next, at time t <b> 2 to t <b> 3, PI series parity addition processing is performed for each row of data corresponding to one ECC block stored in the column data buffer 29, and the processed data is stored in the memory 26. Such processing is repeated in units of 1 ECC block.

  FIG. 14 shows an example in which the host I / F unit 31 writes data to the memory 26, immediately reads the data from the memory 26, and inputs the data to the scramble / EDC unit 30. The reading timing may be delayed a little.

  In FIG. 14, the modulator 27 reads the processed data from the memory 26 immediately after transferring the PI series and PO series parity-added data from the column data buffer 29 to the memory 26. The timing at which the modulation unit 27 reads data may be slightly delayed.

  FIG. 15 is a detailed operation timing chart at time t1 to t2 in FIG. As shown in the figure, at time t11 to t12, partial block data is read out from the memory 26 as a unit, and thereafter, scramble processing is performed between time t12 and t13, and the processed data is stored in the column data buffer 29. At the same time, EDC calculation is performed and PO sequence parity addition processing is performed. Thereafter, this process is repeated, and finally, data for which the parity addition processing of the PO sequence for one ECC block has been performed is stored in the column data buffer 29.

  In FIG. 15, after the partial block data is stored in the column data buffer 29, the PO sequence parity addition processing is started immediately. However, the PO sequence parity addition processing is directly performed on the data read from the memory 26. Since the partial block data is stored in the column data buffer 29, the PO sequence parity adding process may be started after a short time.

  FIG. 16 is a detailed operation timing chart at times t2 to t3 in FIG. As shown in the figure, at times t21 to t22, PI sequence parity addition processing is performed on the PO sequence parity addition processed data in the column data buffer 29, and the processed data is stored in the memory 26 at times t22 to t23. Forward. Thereafter, this process is repeated, and finally the data for which the parity addition processing for the PO sequence and PI sequence for one ECC block has been performed is stored in the memory 26.

  In FIG. 16, after the PI sequence parity addition processing for one row is performed, data transfer from the column data buffer 29 to the memory 26 is performed immediately, but the data after the PI sequence parity addition processing is temporarily stored. Since this can be easily performed, the data transfer timing from the column data buffer 29 to the memory 26 may be slightly delayed.

  As described above, in the fourth embodiment, the column data buffer 29 capable of storing data for one ECC block is provided, and the partial block data is read from the memory 26 as a unit and stored in the column data buffer 29, and the PO sequence parity is set. Since the additional processing is performed, the data transfer from the memory 26 to the column data buffer 29 and the PO-sequence parity addition processing can be performed in parallel, and the parity addition processing can be performed at high speed by reducing the access frequency to the memory 26. it can. In addition, after PO series parity addition processing data for one ECC block is stored in the column data buffer 29, the data is read out in units of rows, PI series parity addition processing is performed, and the processed data is stored in the memory 26. Therefore, the data transfer from the column data buffer 29 to the memory 26 and the PI series parity addition process can be performed in parallel, and the parity addition process can be performed at a high speed while also reducing the access frequency to the memory 26.

(Fifth embodiment)
In the fifth embodiment, the memory capacity of the column data buffer 29 is reduced as compared with the fourth embodiment. Since the optical disk recording apparatus according to the fifth embodiment has the same block configuration as that of FIG. 13 except that the memory capacity of the column data buffer 29 is different, the following description will focus on differences.

  The column data buffer 29 of this embodiment has a memory capacity sufficient to store one partial block data.

  The scramble / EDC unit 30 performs scramble processing, stores the processed data in the column data buffer 29, and performs EDC calculation. When one partial block data has been stored in the column data buffer 29, the parity adding unit 28 performs a PO-sequence parity adding process on the scrambled one partial block data stored in the column data buffer 29.

  When the memory 26 finishes storing the scrambled data with the PO sequence parity for one ECC block, the parity adding unit 28 performs the PI sequence parity adding process. The PI sequence parity addition processing is performed for each row of one ECC block.

  FIG. 17 is an operation timing chart of the parity addition processing in the fifth embodiment. This operation timing chart shows an example in which the column data buffer 29 has a memory capacity of three partial block data.

  At time t1 to t2, among the 1 ECC block data stored in the memory 26, L bytes in the PI code direction and N first partial block data in the PO code direction are transferred to the column data buffer 29. Thereafter, at times t2 to t3, a PO-sequence parity is added to the first partial block data stored in the column data buffer 29. At the same time, the next second partial block data is transferred from the memory 26 to the column data buffer 29.

  Thereafter, at time t3 to t4, the first partial block data to which the PO sequence is added is transferred to the memory 26. At the same time, PO series parity is added to the second partial block data stored in the column data buffer 29. At the same time, the next third partial block data is transferred from the memory 26 to the column data buffer 29.

  Thereafter, the same processing is repeated. In this way, in FIG. 17, the transfer of the partial block data from the memory 26 to the column data buffer 29, the parity addition processing of the PO sequence by the parity adding unit 28, and the column data buffer 29 of the partial block data to which parity has been added. Transfer to the memory 26 is performed at the same timing.

  When the PO sequence parity addition processing is completed for one ECC block data, the parity addition unit 28 performs PI sequence parity addition processing for each row at times t5 to t6.

  As described above, in the fifth embodiment, data is transferred from the memory 26 to the column data buffer 29 in units of partial block data to perform PO series parity addition processing, and the partial block from the memory 26 to the column data buffer 29 is processed. Since the data transfer process, the parity addition process by the parity adding unit 28, and the transfer process from the column data buffer 29 to the memory 26 of the partial block data with the parity added are performed in parallel, the access frequency to the memory 26 is reduced. Thus, the parity addition process can be performed at high speed.

  It should be noted that data corresponding to one ECC block data may be stored in the column data buffer 29 to perform the PO sequence parity addition processing. Thereby, the access frequency to the memory 26 can be further reduced.

(Sixth embodiment)
In the sixth embodiment, the memory capacity of the column data buffer 29 is reduced as compared with the fifth embodiment. Since the optical disk recording apparatus according to the sixth embodiment has the same block configuration as that of FIG. 13 except that the memory capacity of the column data buffer 29 is different, the following description focuses on the differences.

  The column data buffer 29 of the present embodiment has a memory capacity that can store only one partial block data.

  FIG. 18 is an operation timing chart of parity addition processing in the sixth embodiment. From time t1 to t2, the first partial block data is transferred from the memory 26 to the column data buffer 29 via the memory controller 25. At times t <b> 2 to t <b> 3, the parity adding unit 28 performs PO sequence parity adding processing on the partial block data stored in the column data buffer 29. From time t3 to t4, the partial block data to which the parity is added is transferred from the column data buffer 29 to the memory 26. Thereafter, the same processing is performed for the next partial block data.

  When the PO sequence parity addition processing is completed for all partial block data in one ECC block data, PI sequence parity addition processing is performed for each row of the ECC block data at times t5 to t6.

  As described above, in the sixth embodiment, since the parity addition processing for the next partial block data is performed after the PO sequence parity addition processing for one partial block data is completed, the column data buffer 29 has one partial data. Only the memory capacity for storing block data is required, and the circuit scale and component cost can be reduced.

(Other embodiments)
In each of the embodiments described above, error correction is performed after data is transferred from the memory to the correction buffer or the column data buffer 29 when performing error correction of the PI series. Instead of using the correction buffer or the column data buffer 29, the error correction processing may be performed by directly reading data from the memory.

The figure which shows the data format of 1 sector. The figure which shows the data format of an ECC block. The figure which interleaved PO code | cord | chord 1 line at a time with respect to 12 lines of data. The figure which shows the data format of a physical sector. The figure which shows the scanning procedure which scans each line from left to right and records each data. 1 is a block diagram showing a schematic configuration of an optical disk reproducing device according to a first embodiment of the present invention. The figure which shows an example of partial block data. FIG. 5 is an operation timing chart of error correction in the first embodiment. FIG. 9 is a detailed operation timing chart at time t1 to t2 in FIG. FIG. 9 is a detailed operation timing diagram of PO series error correction processing performed between times t2 and t3 in FIG. FIG. 10 is an operation timing chart of error correction in the second embodiment. The operation | movement timing diagram of the error correction in 3rd Embodiment. The block diagram which shows schematic structure of the optical disk recording device which concerns on the 6th Embodiment of this invention. The operation | movement timing diagram of the parity addition process in 4th Embodiment. The detailed operation | movement timing diagram of the time t1-t2 of FIG. The detailed operation | movement timing diagram of the time t2-t3 of FIG. The operation | movement timing diagram of the parity addition process in 6th Embodiment. The operation | movement timing diagram of the parity addition process in 6th Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,21 Disk motor 2,22 Pickup 3,23 Servo processing part 4,24 System controller 5,25 Memory controller 6,26 Memory 7 Demodulation part 8 Error correction part 9 Correction buffer 10 Descramble / EDC part 11,31 Host I / F section 12, 32 Host computer 27 Modulation section 28 Parity addition section 29 Column data buffer 30 Scramble / EDC section

Claims (5)

M data (M is an integer of 2 or more) arranged in the first direction according to the reading order of data recorded on the optical disc, and N (M is arranged in a second direction different from the first direction). N is an integer of 2 or more), a first error correction code used when error correction is performed in units of the M data, and used when error correction is performed in units of the N data. First storage means for temporarily storing an error correction block including a second error correction code;
Error correction means for performing error correction of data read from the optical disk based on the first error correction code and the second error correction code;
Second storage means for temporarily storing at least a part of the error correction block stored in the first storage means in order to perform error correction by the error correction means;
In order to perform error correction using the second error correction code in units of L × N (L is a positive integer smaller than M) data, data is transmitted between the first storage unit and the second storage unit. An optical disc reproducing apparatus comprising: data transmission means for performing transmission / reception. The second storage means has a capacity to store all of the error correction blocks;
The data transmission means transfers all of the error correction blocks from the first storage means to the second storage means before performing error correction by the second error correction code, and L × N error corrected blocks 2. The optical disk reproducing apparatus according to claim 1, wherein the data is transferred from the second storage means to the first storage means in units. The second storage means has a capacity to store at least 3 × L × N data,
The data transmission means includes a first transmission process for transferring L × N data as a unit from the first storage means to the second storage means in order to perform error correction by the second error correction code; A second transmission process of transferring L × N pieces of error-corrected L × N data in units of two error correction codes from the second storage unit to the first storage unit at the same timing;
2. The error correction unit according to claim 1, wherein the error correction unit performs an error correction process using the second error correction code on L × N data at the same timing as the first and second transmission processes. Optical disk playback device. The second storage means has a capacity to store L × N data,
The data transfer means includes a first transmission process for transferring L × N data as a unit from the first storage means to the second storage means in order to perform error correction using the second error correction code; A second transmission process for transferring L × N pieces of error-corrected data by two error correction codes from the second storage means to the first storage means in units of time,
2. The error correction unit performs error correction processing using the second error correction code on L × N data at a timing different from that of the first and second transmission processing. An optical disk reproducing device according to claim 1. M pieces of data (M is an integer of 2 or more) arranged in the first direction according to the recording order of data to be recorded on the optical disc, and N pieces arranged in a second direction different from the first direction (N is an integer of 2 or more) data, a first error correction code used when error correction is performed in units of the M data, and used when error correction is performed in units of the N data First storage means for temporarily storing an error correction block including:
Error correction code generation means for generating the first error correction code and the second error correction code based on the M × N data;
Second storage means for temporarily storing at least a part of the error correction block stored in the first storage means in order to perform processing by the error correction code generation means;
In order to generate the second error correction code in units of L × N data (L is a positive integer smaller than M), data transmission / reception is performed between the first storage unit and the second storage unit. And an optical disc recording apparatus comprising:

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