JP4140344B2 - Decoding device and computer program - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a decoding device and a computer program.To lambIn particular, a decoding device and a computer program for performing error correction and descrambling processing of data reproduced from a recording mediumTo lambRelated.
[0002]
[Prior art]
Optical disks such as CD (compact disk) and DVD (digital versatile disk) have been put to practical use as large-capacity recording media. In these optical discs, an error correction code is added to data and recorded in order to correct a reproduction error. In addition, the data is recorded by being scrambled for the purpose of randomizing the data.
[0003]
An example of a DVD related to these error correction codes and scrambles will be described. The data of about 32 kbytes, which is a total of 16 sectors of logical sectors composed of 2 kbytes of user data and 4 bytes of check code EDC, is shown in FIG. As shown in FIG. 15, information is rearranged into a so-called 192 × 172 configuration of 192 bytes in the vertical direction and 172 bytes in the horizontal direction, and information corresponding to the physical address (ID 0 to 15 in the figure) is added to each sector. The user data and EDC of each sector are scrambled based on a part of the address information, and an error correction code described below is added to the scrambled data.
[0004]
In DVD, as the error correction code, a PI correction code constituting Reed-Solomon code RS (182, 172, 11) in the horizontal direction in FIG. 15 and a PO correction constituting Reed-Solomon code RS (208, 192, 17) in the vertical direction. An error correction code configuration using a product code to which a code is added is employed. When recording on the optical disk, as shown in FIG. 16, the PO correction code is interleaved into 16 sectors and sequentially recorded in the horizontal direction of the figure. That is, from a physical sector consisting of data of 182 bytes (182 columns) in the horizontal direction, 12 bytes (12 rows) in the vertical direction, and PI correction code, 182 bytes (182 columns) in the horizontal direction, and 1 byte (1 row) in the vertical direction. As a set, the PO correction code is composed of 16 sets.
[0005]
During reproduction, reproduction data is usually first subjected to PI correction, then PO erasure correction, and further PI correction is performed to correct an error in the reproduction data. However, correction may not be possible on a disc having extremely many reproduction errors.
[0006]
Consider a case where there are data errors in the address information (ID) as a result of an uncorrectable error remaining after error correction because a large number of errors including burst errors have occurred. An ID error can be detected by an error detection code (IED) added to the ID. In the case of a DVD, as shown in FIG. 15, since the ID is a part of the PI correction code sequence and the PO correction code sequence, if the ID or IED contains an error after correction, the PI correction code sequence and the PO correction are included. Both code sequences were uncorrectable.
[0007]
This uncorrectable state is considered to be because the data part other than the ID has an error and exceeds the correction capability. Therefore, considering a PI correction code sequence including ID and IED, it can be said that there is a high possibility that data belonging to this PI correction code sequence also includes an error. Therefore, even if the address interpolation as in the present invention to be described later is performed to interpolate the scramble initial value, there is a high possibility that the data is still in error, so there is not much meaning.
[0008]
Further, when compressed data such as MPEG (Moving Picture Experts Group) data is recorded as user data, even a slight data error may cause a fatal result. If the data check code determines that the data contains an error, a so-called retry is often performed in which the track on the disk is accessed again and the data is read again.
[0009]
Also known is an apparatus for recording and reproducing information signals in a format other than the formats shown in FIGS. 15 and 16 (see Patent Document 1). This format includes first error correction means for user data to be recorded / reproduced mainly for first data, and second error correction means for second data which is address information to be recorded / reproduced and other additional information. The formats are independent of each other and are shown in FIGS. 17 and 18, for example.
[0010]
17 and 18 show an example of an error correction block structure of an optical disc that uses a blue laser as a recording / reproducing laser and realizes higher density and larger capacity than DVD. In FIG. 17, the error correction block includes user data and error detection code (EDC) as first data to be described later, a first error correction code for the first data, address information as second data, and others. The additional information and the second error correction code for the second data are included, and the error correction block has a structure of 16 physical sectors as shown in FIG.
[0011]
The first data included in the error correction block includes user data for 32 logical sectors and an error detection code (EDC) for each logical sector. The user data for each sector is 2048 bytes and the EDC is 4 bytes. . A first error correction code is added to the first data.
[0012]
FIG. 18A shows the configuration of the first error correction code. As shown in FIG. 6A, the first data of 32 logical sectors is interleaved and rearranged in a configuration of 216 bytes in the vertical direction and 304 bytes in the horizontal direction. A 32-byte parity is generated and added to form a code sequence of a total of 304 Reed-Solomon codes RS (248, 216, 33). As described above, in this first error correction code, the 64 kbytes of user data and EDC are divided into 216 bytes, and the parity of the first error correction code of 32 bytes is added to the 216 bytes of data. It is a thing. One error correction (ECC) block includes 304 first error correction code sequences LDC (248, 216, 33).
[0013]
On the other hand, the Reed-Solomon code RS (62, 30, 33) code in which the physical address information for 16 physical sectors and the additional information associated with each logical sector are used as the second data, and the second error correction code is added thereto. Construct a series. That is, as shown in FIG. 18B, physical address information for 16 sectors, an error correction code for address information (AF in the figure) described later, and additional information associated with each logical sector are interleaved in the vertical direction. After being rearranged into data of 30 bytes and 24 bytes in the horizontal direction, a correction code (parity) of 32 bytes is added to each of 24 pieces of data in the vertical direction, resulting in a total of 24 Reed Solomons. It is composed of a code RS (62, 30, 33).
[0014]
That is, 24 first data including 720 (= 30 × 24) bytes of second data per ECC block and 768 (= 32 × 24) bytes of second error correction code (parity in the figure). Two error correction code sequences BIS (62, 30, 33) are formed.
[0015]
Since the physical address information is particularly important data for reproduction, as shown in FIG. 18 (c), each of the 5-byte address information ID0 to ID15 has a purpose of 4-byte error correction or error detection. 16 third error correction code sequences RS (9, 5, 5) for 16 physical sectors to which the parity is added. Therefore, the second data includes data constituting these 16 third error correction code sequences and additional data associated with each logical sector.
[0016]
The second error correction code sequence BIS (62, 30, 33) × 24 including the second data such as the address information is a first error correction code sequence LDC including the first data which is the user data. (248, 218, 33) × 304 and interleaving and multiplexing are performed as shown in FIG. 17 and divided into three BIS areas as shown in FIG.
[0017]
As a result of these interleaving and multiplexing, the physical address information shown in FIG. 18 (c) and its 9 bytes of error correcting code are arranged in the BIS part in the first three rows of Sync frames of each of the 16 physical sectors ( ID0 to ID15 in FIG. 17), and during reproduction, these values are extracted by the demodulation circuit and the disk is accessed. As data to be recorded on the disc, a frame synchronization code SYNC is added to the head of the data in the horizontal direction, and the data is recorded in order from the left to the right in FIG.
[0018]
As described above, in the ECC block structure shown in FIG. 17, the first error correction code (LDC) for the first data including the user data and the second data including the address information (scramble initial value) are stored. The second error correction code (BIS) constitutes an independent error correction RS code sequence, which is different from an error correction code sequence based on a product code such as a DVD.
[0019]
[Patent Document 1]
JP 2002-74664 A (FIGS. 8 and 9)
[0020]
[Problems to be solved by the invention]
By the way, the first data is scrambled based on the address information, and the first data in the ECC block is generated based on the address information included in the second data. A scramble process is performed by the scramble data. The scramble process is performed by adding scramble data output from a linear feedback shift register (LFSR) 1 shown in FIG. 19 modulo 2 to user data and EDC in an adder 2.
[0021]
In addition, since the scramble processing starts with the initial value of LFSR1 as the value of PS5 to PS19 in the address information for each logical sector, PS0 to PS4 corresponding to the sector number are not set in the initial value, and therefore are in the same ECC block. The same scramble process is performed on the data of each logical sector. In the same ECC block, the descrambling initial setting value is the same value as the scrambling initial setting value.
[0022]
Here, the first error correction means for the first data including user data and EDC as shown in FIGS. 17 and 18, and the second error correction means for the second data including the address information as the scramble initial value. In an independent format without overlapping each other, even if error correction is performed by the first error correction means including the first data, if correction is impossible in the second error correction means, Therefore, the initial value of descrambling cannot be obtained, and the user data is erroneously caused by erroneous descrambling even though there is no error in the correctly corrected first user data. is there.
[0023]
For this reason, in DVD, the initial value of descrambling is selected using only 4 bits out of 32 bits of ID, so even if there is an ID error, if there is no error in those 4 bits, the initial value of descrambling is set. For example, in the method using most bits of the ID as the descrambling initial value, it is necessary to further improve the reliability of the ID.
[0024]
  The present invention has been made in view of the above points, and the first error correction means for the first data and the second error correction means for the second data including the address information serving as the scramble initial value overlap. And a decoding device that can prevent descrambling from being performed correctly when all of the address information (ID) that is the descrambling initial value is uncorrectable after error correction in independent formats Computer programLambThe purpose is to provide.
[0025]
[Means for Solving the Problems]
  In order to achieve the above object, the decoding device according to the first invention provides:A scrambled error check code, a first error correction code sequence obtained by performing error correction processing on the first data, and a sector part of which is used as a scramble initial setting value for scramble processing for the first data From the recording medium in which the second error correction code sequence obtained by performing error correction processing on the second data including the address is multiplexed after being independently multiplexed in predetermined error correction block units and recorded. The first and second error correction code sequences are reproduced and demodulated, and the sector address extracted from the demodulated second data and further error-corrected or interpolated based on the continuity of the sector address is the first Demodulation means for outputting as sector address, storage means, error correction processing means, extraction means, error inspection means, and first and second descrambling And management means, and having an error checking and retry means, and a write-back unit.
[0026]
  The storage means stores a first sector address together with the first and second error correction code sequences output from the demodulation means, a buffer memory having a capacity for a plurality of error correction blocks, and one And a working memory having a capacity for error correction blocks. The error correction processing means is configured to correct one error out of information including first and second error correction code sequences and a first sector address for a plurality of error correction blocks stored in the buffer memory. The block information is stored in the work memory, and error correction processing is performed on the information for one error correction block stored in the work memory.ThatThis is performed sequentially in units of one error correction block. The extraction means is included in the second data subjected to error correction processing by the error correction processing means.Let the sector address be the second sector address,All of the plurality of second sector addresses are extracted. The error checking means performs error checking for all of the plurality of second sector addresses extracted by the extracting means. The first descrambling processing means has one descrambling initial setting value based on one of the second sector addresses obtained as a result of error check and no error, and is output from the working memory. The error check code of the correction block and the first data are descrambled and stored in the working memory. When the plurality of second sector addresses are all determined to be errors as a result of the error check, the second descrambling processing unit is based on the first sector address output from the working memory. The error check code and the first data of one error correction block output from the working memory with the descrambling initial setting value are descrambled and stored in the working memory. The error checking and retry means performs error checking on the first data after descrambling by the first or second descrambling means using the error check code after descrambling, and the first data If there is an error, one error correction block stored in the working memory is reproduced again from the recording medium. The write-back means stores at least first data in the working memory including the error check code and the first data after descrambling processing by the first or second descrambling processing means.
[0030]
  In the present invention, the demodulated data of the first and second error correcting code sequences output from the demodulating means to the buffer memory, and the first sector address obtained by error correction following the demodulated data or the first obtained by interpolation. The sector addresses are sequentially written in units of error correction blocks, and when it is determined that all of the plurality of second sector addresses are errors as a result of the error check, the error correction data written in the buffer memory is corrected. The first data of the error correction block can be descrambled with a descrambling initial setting value using one sector address or the first sector address obtained by interpolation.Further, in the present invention, the first or second descramble processing means performs error checking on the first data after descrambling using the error check code after descrambling, and there is an error in the first data. In some cases, one error correction block stored in the working memory can be reproduced from the recording medium again.
[0033]
  In order to achieve the above objective,2The computer program of the invention1InventionEach means of the decryption device is functioned by a computerIt is characterized by making it.
[0035]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an example of a recording / reproducing apparatus to which the present invention is applied. In the figure, an input / output signal processing unit 3 performs processing such as MPEG encoding / decoding on signals such as images and sounds. At the time of recording, the user data MPEG-encoded by the input / output signal processing unit 3 is added with an error check code (EDC), then scrambled by the scramble circuit 4, and further a physical address where the user data is recorded. An information ID is also added and supplied to the ECC encoder 5.
[0036]
As shown in FIG. 19, the scramble process by the scramble circuit 4 is performed by adding the scramble data output from the LFSR (Linear Feedback Shift Register) 1 to the user data and the EDC modulo 2 by the adder 2. The physical address value or a part of the physical address value is used as the initial setting value of LFSR1.
[0037]
The ECC encoder 5 adds error correction codes to input data and physical address information to generate error correction block (ECC block) data, supplies the error correction block to the modulation circuit 6, modulates the optical data, and then reads the optical disk. The recording medium 7 is recorded by a known means.
[0038]
On the other hand, at the time of reproduction, a signal reproduced from a recording medium 7 such as an optical disk by a known means is supplied to the demodulation circuit 8 in FIG. 1 and demodulated, and error correction block data obtained thereby is decoded by the ECC decoder 9 at the optical disk 7. Is corrected by the descrambling circuit 10 and further subjected to a data error check (EDC check) and sent to the MPEG decoder in the input / output signal processing unit 3 at the subsequent stage. It is decoded into a signal such as an image / sound.
[0039]
The demodulator 8 outputs the error correction block data to the subsequent ECC block, extracts physical address information from the demodulated data, and outputs the physical address information to the system controller (system controller) 11. Based on the address information supplied from the demodulation circuit 8, the system controller 11 accesses the physical address corresponding to the logical address designated by the input / output signal processing unit (MPEG encoder / decoder) 3 in the subsequent stage, and corrects the error. Record or play block data.
[0040]
Since the address information is particularly important data for recording and reproduction, an error correction or error detection code for address information or the like is generally added. When extracting the physical address information, the demodulation circuit 8 performs error correction or error detection of the address information, and when recording / reproducing along the track of the optical disc 7, the address takes a continuous value. When an error cannot be corrected and when an error is detected, interpolation based on address continuity is also performed and output to the system controller 11.
[0041]
In the present invention, the address value corrected or interpolated by the demodulation circuit 8 is output to the descrambling circuit 10 at the subsequent stage. The descrambling is performed by modulo 2 addition of the scrambled data output from the LFSR in the descrambling circuit 10 to the data corrected by the ECC decoder 9, and the initial setting value (descrambling initial setting value) of the LFSR is The physical address value obtained from the reproduction data or a partial value thereof is used.
[0042]
In the present invention, the address value after error correction by the ECC decoder 9 or the address value corrected or interpolated by the demodulation circuit 8 is used as the initial value of this descrambling, and the address value after error correction by the ECC decoder 9 and the address information dedicated to the address information are used. The error is inspected from an error correction or error detection code. If there is no error, the address value is used. If the inspection result is an error, the address value corrected or interpolated by the demodulation circuit 8 is used.
[0043]
As a result, even if the address value cannot be corrected by the ECC decoder 9, the address value corrected or interpolated by the demodulation circuit 8 is used for descrambling, so that the descrambling is performed with an initial value different from that at the time of recording. By doing so, it is possible to reduce the fact that all user data is erroneous.
[0044]
FIG. 2 is a block diagram showing another recording / reproducing apparatus to which the present invention can be applied. In the figure, the same components as those in FIG. The recording / reproducing apparatus shown in FIG. 2 performs data input / output, ECC encode / decode, modulation / The demodulating process is performed. The buffer memories 13 and 15 absorb the difference between the transfer speed between the MPEG encoder / decoder and the disk recording / playback transfer speed, provide a time margin for performing the retry operation described later, and record / playback is distributed on the optical disk 7. Even if it is, it is inserted for the purpose of enabling continuous recording and reproduction.
[0045]
Further, the recording / reproducing apparatus shown in FIG. 2 is configured to write the data demodulated by the demodulating circuit 8 to the buffer memory 15 and also write the address value corrected or interpolated by the demodulating circuit 8 to the buffer memory 15. .
[0046]
The ECC decoder 16 performs error correction on the data in the buffer memory 15 and writes it back to the buffer memory 15, and then reads the corrected data from the buffer memory 15 and performs descrambling processing in the descrambling circuit 10. . At this time, the descrambling circuit 10 checks the error from the address value after error correction read from the buffer memory 15 and the error correction or error detection code dedicated to the address information, and if there is no error, uses the address value. When the inspection result is an error, the address value corrected or interpolated by the demodulation circuit 8 and written in the buffer memory 15 is used.
[0047]
As a result, even if the address value cannot be corrected by the ECC decoder 16, the address value corrected or interpolated by the demodulation circuit 8 is used for descrambling, so that the descrambling is performed with an initial value different from that at the time of recording. It is possible to reduce all errors in user data due to Since the address value corrected or interpolated by the demodulation circuit 8 is written in the buffer memory 15 of the same page as the data in the ECC block, even if a large number of error correction block data is accommodated in the buffer memory 15, each error value is stored. Correspondence between the corrected block data and the corrected or interpolated address value is not confused, and the timing adjustment can be performed reliably.
[0048]
Next, each embodiment of the decoding apparatus according to the present invention will be described. FIG. 3 shows a block diagram of a first embodiment of a decoding apparatus according to the present invention. In the figure, the same components as those in FIG. The first embodiment of the decoding apparatus shown in FIG. 3 includes a demodulation circuit 8, a buffer memory 15, an ECC encoder 16, a system controller 17, and a descrambling circuit 10a, and has the error correction block structure shown in FIGS. This is a corresponding embodiment.
[0049]
The demodulation circuit 8 includes a demodulation unit 81, an ID extraction unit 82, and a multiplex (MUX) 83. The descrambling circuit 10a is a circuit corresponding to the descrambling circuit 10 of FIGS. 1 and 2, and includes a descrambling unit 101, an ID extraction unit 102, and an EDC circuit 103. The MPEG decoder 31 in FIG. 3 is an MPEG decoder in the input / output signal unit 3 in FIGS.
[0050]
  To explain the operation of this embodiment, in FIG. 3, a signal reproduced from the optical disk 7 by a known means is demodulated by the demodulator 81, and ID data including physical address information from the demodulated data. The part is extracted by the ID extraction unit 82 and the system controllerLowIs output to In this embodiment, 16 physical addresses shown in FIG. 18C are included in one ECC block, and a 4-byte parity of Reed-Solomon code RS (9, 5, 5) is added to each ECC block. ing.
[0051]
  The ID extraction unit 82 corrects the extracted ID data based on the parity of the RS (9, 5, 5) and outputs an ID data portion to the system controller 17.AThe ID data portion IDdem including the sector address value interpolated based on the continuity of the dress is output to the system controller 17.
[0052]
In addition, the ID extraction unit 82 performs error correction or error detection of the ID by using the error correction or error detection code, and reproduces the recording signal of the optical disc 7 along the track when extracting the ID included in the ECC block. In this case, since the address takes a continuous value, when the ID cannot be corrected, the ECC block is searched by performing interpolation based on the continuity of the address.
[0053]
When reading is requested from the MPEG decoder 31 at the subsequent stage, the system controller 17 controls an optical head (not shown) using physical address information included in the ID data portion IDdem input from the ID extraction unit 82 to 4 is accessed, the demodulated data of the requested ECC block is taken out from the demodulator 81, and this demodulated data and the ID data portion IDdem from the ID extractor 82 are schematically shown in FIG. Are written in the buffer memory 15 of FIG. 3 after being multiplexed in units of ECC blocks (BLK).
[0054]
An example of the memory map of the buffer memory 15 of this embodiment is shown in FIG. Similar to the data arrangement of the error correction block shown in FIG.
[0055]
As for the SYNC pattern at the head of the frame, when the SYNC pattern is evaluated by the demodulation circuit 8 and is different from the original pattern, as shown in FIG. 9 as a SYNC error flag for generating an erasure pointer at the time of LDC correction described later. It is written in the buffer memory 15.
[0056]
In ID0 to ID15 in FIG. 9, data obtained by demodulating the reproduction signal corresponding to ID0 to ID15 is written as it is. As described above, these ID0 to ID15 are part of the second error correction code sequence BIS (62, 30, 33), and are corrected or interpolated in these ID0 to ID15 portions on the buffer memory 15. If the ID value is written, an erasure pointer for IDC correction, which will be described later, cannot be generated. Therefore, the demodulated result must be written as it is.
[0057]
As described above, the demodulation circuit 8 performs ID error correction using the error correction code of the ID data included in the ECC block. When the ID cannot be corrected, interpolation based on the continuity of the address is performed. Although output to the system controller 17, in this embodiment, the address values IDdem0 to IDdem15 subjected to error correction or address interpolation by the demodulation circuit 8 are also written in the buffer memory 15. Note that the demodulation circuit 8 originally has an ID interpolation function, which is used in the present embodiment.
[0058]
3 writes the demodulated data obtained by demodulating the reproduction signal by the demodulating unit 81 into the buffer memory 15 as it is, and then buffers the sector address value error-corrected or address-interpolated by the ID extracting unit 82. This represents writing to the memory 15. IDdem 0 to IDdem 15 in FIG. 9 indicate the positions where the sector address values that have been error-corrected or address-interpolated by the ID extracting unit 82 are written, and are written using an appropriate empty area on the buffer memory 15.
[0059]
As described above, the data written in the buffer memory 15 is once read and the error correction circuit (BIS / LDC / ID correction unit) 161 in the ECC decoder 16 in FIG. Data errors associated with recording / reproduction of the optical disc are corrected during the schematically shown period. That is, the BIS / LDC / ID correction unit 161 first performs BIS correction on the data written in the buffer memory 15, and the correction process corrects the data in the BIS, and the error in the BIS data. The position is determined and stored as a BIS error flag for generation of an erasure pointer at the time of LDC correction described later.
[0060]
After the BIS correction, the LDC correction is subsequently performed, the data sandwiched between the SYNC error and the BIS error indicated by the SYNC error flag and the BIS error flag is regarded as a burst error, and an erasure pointer is set. Erasure correction based on the Reed-Solomon code RS (248, 216, 33) of 18 (a) is performed.
[0061]
As described above, since the error correction code or error detection code dedicated to the address information is added to the address information, the correction code RS (9, 5, 5) dedicated to the address information following the BIS correction and LDC correction described above. 5) is used to correct the address information. This correction can be omitted.
[0062]
The corrected data is read out from the buffer memory 15 for each logical sector and output. The ID extraction by the ID extraction unit 102 and the descrambling circuit 10a in FIG. 3 are performed during the period schematically shown in FIG. 4 is input to the EDC circuit 103 after being descrambled by the descrambling unit 101, and after performing error checking by EDC for each logical sector, as schematically shown in FIG. And decoded by the MPEG decoder 31 at the subsequent stage.
[0063]
At this time, in the present embodiment, prior to descrambling by the descrambling unit 101, all the 16 pieces of address information shown in FIG. 9 are read in advance by the ID extraction unit 102 in FIG. 3, and RS (9, 5 , 5) is also performed, and address information that is not an error among the read address information is output to the descrambling unit 101 as an initial value for descrambling.
[0064]
Here, if all the 16 pieces of address information are detected as errors, the values obtained by reading out any of the address values (IDdem0 to IDdem15 in FIG. 9) that have been error-corrected or interpolated by the demodulation circuit 8 are decoded. It is output to the descrambling unit 101 as an initial value for scrambling. Or it is good also as a value which took the majority of IDdem0-IDdem15 as an address value output to the descramble part 101. FIG.
[0065]
The above operation will be described with reference to the flowchart of FIG. In FIG. 10, as described above, after demodulation is performed by the demodulation circuit 8 of FIG. 3 (step S1), BIS / LDC / ID correction unit 161 first performs BIS correction (step S2), and then LDC correction is performed (step S3), and finally the address information ID is corrected using the correction code RS (9, 5, 5) dedicated to address information (step S4). Subsequently, the ID extraction by the ID extraction unit 102 is performed (step S5).
[0066]
  The ID extraction in step S5 will be described in more detail. First, the ID extraction unit 102 reads all 16 ID values in the same ECC block extracted from the buffer memory 15, and those ID values are all errors. It is determined whether or not there is (step S51). When any one of the 16 ID values is not an error, address information IDk (where k is a value of 0 to 15 and no error) is used as the descrambling initial value SCRID (step S).53).
[0067]
  On the other hand, if all the 16 ID values are determined to be errors in step S51, the value of any one of IDdem0 to IDdem15 (IDdem15 as an example in FIG. 10) written in the buffer memory 15 by the demodulation circuit 8 is decoded. The initial value SCRID for scrambling is used (step S52).
[0068]
The descrambling unit 101 performs descrambling using the descrambling initial value SCRID (step S6), and causes the EDC circuit 103 to perform error checking by EDC on the obtained data of each logical sector (step S7). The EDC circuit 103 determines whether or not there is an EDC error (step S8). When it is determined that there is an EDC error, it is determined that there is a data error due to uncorrectability or error correction, so the same error correction is performed again. A track including a block is accessed to reread data, so-called a retry operation. The retry operation starts again from the process of step S1. On the other hand, when it is determined that there is no EDC error, the data is sent to the MPEG decoder 31 and decoded (step S9).
[0069]
FIG. 11 shows a block diagram of an embodiment of the circuits 101 and 102 for performing the ID extraction and descrambling operation. In the figure, the same components as in FIG. In FIG. 11, the ID values extracted from the buffer memory 15 after BIS correction and IDC correction are read one after another by the ID latch 1021 and the ID error check circuit 1022 includes the RS (9, 5, 5) including the address. An error check is performed, and when there is no error (when OK / Error = OK in the figure), the ID data in the ID latch 1021 is held in the ID register 1023.
[0070]
In this way, all 16 ID values are read from the buffer memory 15 and checked for errors. If any of the 16 IDs is OK, the value is output as a descrambling initial value SCRID to the linear feedback shift register (LFSR) 1011 in the descrambling unit 101 at the subsequent stage via the data selector 1026.
[0071]
On the other hand, the address values (IDdem0 to IDdem15 in FIG. 9) written to the buffer memory 15 by the demodulation circuit 8 are also read from the buffer memory 15 and held in the IDdemk register 1024 in FIG. A majority vote of the bit part that becomes the initial descrambling value of IDdem15 is taken. In the ID error check, when all 16 IDs are determined to be errors (All Error), the value of the ID demk register 1024 that has been voted by the majority circuit 1025 is selected by the selector 1026 and the descramble initial value is set. It is output to LFSR 1011 as SCRID.
[0072]
As a result, the LFSR 101 outputs the descrambled data with the SCRID as the descrambling initial value and supplies it to the adder 1012, where the first data (user data) read from the buffer memory 15 is output. And EDC) and modulo 2 are added to obtain original data before scrambling.
[0073]
Next, a second embodiment of the decoding apparatus according to the present invention will be described. FIG. 5 shows a block diagram of a second embodiment of a decoding apparatus according to the present invention. In the figure, the same components as those in FIG. The second embodiment of the decoding apparatus shown in FIG. 5 is an embodiment corresponding to the error correction block structure shown in FIGS. A descrambling circuit 10b shown in FIG. 5 is a circuit corresponding to the descrambling circuit 10 shown in FIG. 2, and includes a descrambling unit 104, an ID extraction unit 105, and an EDC circuit 106.
[0074]
  In the first embodiment shown in FIG. 3, the descrambling process is performed by an MPEG coder.31In the embodiment shown in FIG. 5, the descrambling processing result by the descrambling unit 104 is once written back to the buffer memory 15, and then the MPEG decoder is used.15Output to.
[0075]
That is, in FIG. 5, after data and address values are written from the demodulation circuit 8 as schematically shown in FIG. 6A, the BIS / LDC / ID correction unit 161 performs BIS correction, LDC correction, and ID correction. It is done sequentially. As schematically shown in FIG. 6B, the corrected data is read out from the buffer memory 15 for each logical sector and output, and the ID extraction unit 105 performs the same ID extraction as the ID extraction unit 102. A descrambling process is performed by the descrambling unit 104 in the descrambling circuit 10b in FIG.
[0076]
Subsequently, the descrambling process result by the descrambling unit 104 is once written back to the buffer memory 15 as schematically shown in FIG. 6C, and then the descrambling process result is read from the buffer memory 15, After performing error checking by EDC for each logical sector, it is output to the subsequent MPEG decoder 31 and decoded as schematically shown in FIG.
[0077]
Next, a third embodiment of the decoding apparatus according to the present invention will be described. FIG. 7 shows a block diagram of a third embodiment of a decoding apparatus according to the present invention. In the figure, the same components as those in FIG. 7 are denoted by the same reference numerals, and the description thereof is omitted. The third embodiment of the decoding apparatus shown in FIG. 7 is an embodiment corresponding to the error correction block structure of FIGS. A descrambling circuit 10c shown in FIG. 7 is a circuit corresponding to the descrambling circuit 10 shown in FIG.
[0078]
In this embodiment, the buffer memory 15 includes a buffer memory 151 and a work memory 152 that can hold data corresponding to one ECC block. Processing such as error correction, descrambling, and EDC inspection is performed by the work memory 152. Configured to do.
[0079]
Next, the operation of the present embodiment will be described. As schematically shown in FIG. 8 (A), the signal reproduced from the optical disk 7 by a known means, the demodulated data demodulated by the demodulator 81 in FIG. 7 is directly stored in the buffer memory 151 for each ECC block. After the writing, as shown by hatching in FIG. 8A, the address values IDdem0 to IDdem15 subjected to error correction or address interpolation by the ID extraction unit 82 in FIG. 7 are written in the buffer memory 151. Thereby, the arrangement of the memory map of the memory buffer 151 is the same as that shown in FIG. However, the size of the buffer memory 151 is a memory size capable of holding a plurality of ECC block data, for example, 64 ECC block data.
[0080]
The demodulated data on the buffer memory 151 is transferred to the work memory 152 for one ECC block. As an example, the LDC, BIS, Sync error flag, and IDdem0 to IDdem15 are transferred to the work memory 152 in the arrangement of the memory map as shown in FIG.
[0081]
The BIS / LDC / ID correction unit 161, ID extraction unit 108, descrambling unit 107, and EDC circuit 109 in FIG. 7 perform the processing shown in the flowchart of FIG. 8B and 8C schematically show the processing time on the memory 152. FIG. For example, as shown in FIG. 8A, during the period when the demodulated data of the ECC block BLK3 is obtained, as shown in FIG. 8B, the BIS / LDC in FIG. 7 is compared with the demodulated data of the ECC block BLK1. / ID correction unit 161 performs correction. After the correction is performed on the data on the work memory 152 in the period shown in FIG. 8B, the corrected data on the work memory 152 is corrected as shown in FIG. The ID extraction and descrambling processing by the ID extraction unit 108 and the descrambling unit 107 in FIG. 7 are performed.
[0082]
The data on the work memory 152 for which the error correction, descrambling, EDC inspection, and the like have been completed are transferred back to the buffer memory 151, and this data is read from the buffer memory 151 to be read later from the MPEG decoder 31. 8D is transferred as shown schematically in FIG. 8D, and is decoded into original data by the MPEG decoder 31.
[0083]
Thus, in this embodiment, since the size of the buffer memory 151 has a capacity equivalent to a plurality of ECC blocks, the output to the MPEG decoder 31 is the error correction and data output as shown in FIG. The scramble process can be transferred with a predetermined amount of delay. As a result, when an EDC error is detected because user data cannot be corrected in the EDC inspection, the system controller 17 that has received the notification of the EDC error on the optical disk 7 on which the ECC block including the data error is recorded. A data error is recovered by accessing the track again and executing a series of processing retries in the flowchart of FIG.
[0084]
In the description in FIGS. 3 to 8, it has been described that ID correction, which is error correction dedicated to address information, is performed by the BIS / LDC / ID correction unit 161, but this is the ID extraction in FIGS. 3 to 8. The processing may be performed in the units 102, 105, and 108.
[0085]
Further, the method for realizing the present invention is not limited to the recording / reproducing apparatus as shown in the embodiment, and this is shown as a computer program for executing the processing of the present invention in the flowchart of FIG. 10 described below. Each of the steps shown may be configured and accommodated in a large-scale semiconductor integrated circuit (LSI) or a computer recording medium.
[0086]
Next, a method for transmitting the computer program of the present invention will be described with reference to the flowchart of FIG. First, as shown in FIG. 13, the computer program is divided into predetermined bytes suitable for transmission and packetized (step S11), and the packet is transmitted to a desired transmission path (step S12). Then, the above processing is performed for all packets of the computer program (step S13).
[0087]
Next, an embodiment of a transmission apparatus for transmitting a computer program of the present invention will be described with reference to the block diagram of FIG. In FIG. 13, the computer program for executing each step shown in the flowchart of FIG. 13 is encrypted by the data encryption unit 21 and then transmitted by the transmission interface (I / F) unit 22 for packetization or the like suitable for transmission. After data conversion, the data is transmitted via the network 23. On the reception side, a packet from the network 23 is received by the reception I / F unit 24, data is extracted from the received packet, and data decryption is performed by the data decryption unit 25 to restore and obtain the computer program before encryption. To do.
[0088]
In the above embodiment, the user data to be recorded / reproduced as shown in FIG. 17 is the first error correction means for the main first data, the address information to be recorded / reproduced, and other additional information. Although the case where the present invention is applied to independent formats that do not overlap with the second error correction means for the second data has been described, the present invention is not limited to this, for example, as shown in FIGS. It can also be applied to the format of the product code structure.
[0089]
In the case of the format shown in FIGS. 15 and 16, when the evaluation of IDs is performed sequentially in the order of sectors, if there is an error exceeding the correction limit and the ID of a certain sector is an error, even the correct reproduction data may be lost in that sector. All errors will be caused by incorrect descrambling, but when any of the IDs is correct when the present invention is applied, it is possible to prevent the correct data from being completely different due to descrambling due to the ID error. it can.
[0090]
【The invention's effect】
  As explained above, according to the present invention,In a buffer memory having a capacity for a plurality of error correction blocks, information including first and second error correction code sequences and a first sector address for a plurality of error correction blocks output from the demodulating means is stored. The information of one error correction block in the storage information of the buffer memory is stored in the working memory, and the sector address obtained by performing the error correction processing on one error correction block stored in the working memory is stored. Perform error checking,Error check result, eithersectorIf there is no error in the address, then the initial descramble value of the error correction block is obtained and the information after error correction is descrambled.sectorEven if the address is in errorObtained by demodulation meansError correction or address interpolationsectorInformation after error correction with the initial descramble value based on the addressofDescrambling processFurther, the first data after the descrambling process is subjected to an error check using the error check code after the descrambling process, and when there is an error in the first data, it is stored in the working memory. Since one error correction block is reproduced again from the recording medium, the data error of the first data can be recovered. The present invention also has the following features.
[0091]
(1) In an error correction block structure in which a first error correction code sequence for user data and a second error correction code sequence for an address (ID) are independent from each other, as a result of error correction, an address is obtained correctly. Even if the data is obtained correctly, if the address (ID) cannot be corrected, the descrambling is not performed correctly, and as a result, a conventional problem that a data error occurs can be greatly reduced.
[0092]
(2) As a result of reducing unnecessary user data errors in the above situation, the retry operation for re-reading the disk can be reduced.
[0093]
(3) Since most of the above processing is performed by hardware, it can be executed without imposing a load on the system controller.
[0094]
(4) When it is determined that the plurality of addresses of the error correction block are all errors as a result of the error check, a data based on a value predicted from the address of the error correction block reproduced before the error correction block is used. When the first data of the error correction block is descrambled with the scramble initial setting value, the descrambling process is performed when starting the reproduction of the recording medium or when reproducing a discontinuous block on the recording medium. The CPU sets the initial set value of the scramble process for the first error correction block in advance as a value predicted from the second data of the error correction block reproduced before the error correction block, and the CPU performs the second descrambling process. In the present invention, a sector far before the sector requested by the MPEG decoder is required. Because by using the second error corrected data or interpolated from the demodulation means have started demodulation from, can be made unnecessary setting of the initial set value of the descrambling process for the beginning of the error correction block of the.
[Brief description of the drawings]
FIG. 1 is a block diagram of an example of a recording / reproducing apparatus to which the present invention can be applied.
FIG. 2 is a block diagram of another example of a recording / reproducing apparatus to which the present invention can be applied.
FIG. 3 is a block diagram of a first embodiment of a decoding apparatus according to the present invention.
4 is a timing chart of an example of FIG.
FIG. 5 is a block diagram of a second embodiment of the decoding apparatus of the present invention.
6 is a timing chart of an example of FIG.
FIG. 7 is a block diagram of a third embodiment of a decoding apparatus according to the present invention.
8 is a timing chart of an example of FIG.
FIG. 9 is a memory map of the buffer memory according to the embodiment of this invention.
FIG. 10 is a flowchart for explaining the operation of the exemplary embodiment of the present invention.
FIG. 11 is a diagram illustrating an example of a detailed configuration of an ID extraction unit and a descrambling circuit in a descrambling circuit according to the present invention.
FIG. 12 is a memory map of the working memory according to the embodiment of this invention.
FIG. 13 is a flowchart illustrating processing for transmitting a computer program according to the present invention.
FIG. 14 is a computer program of the present invention.An example of a transmission device that transmitsIt is a block diagram.
FIG. 15 is a diagram for explaining a conventional error correction code structure;
FIG. 16 is a diagram illustrating a conventional ECC block structure.
FIG. 17 shows an ECC block structure according to the embodiment of the present invention.
FIG. 18 shows a configuration of an error correction code according to the embodiment of the present invention.
FIG. 19 is an explanatory diagram of an example of a scramble circuit of the present invention.
[Explanation of symbols]
3 I / O signal processor
4 Scramble circuit
5, 14 ECC encoder
6 Modulation circuit
7 Optical disc
8 Demodulator circuit
9 ECC decoder
10, 10a, 10b, 10c, 16 Descramble circuit
11, 17 System controller (syscon)
13, 15, 151 Buffer memory
16 BIS / LDC / ID correction circuit
81 Demodulator
82 ID extractor
83 Multiplexer (MUX)
101, 104, 107 Descramble part
102, 105, 108 ID extraction unit
103, 106, 109 EDC circuit
152 Working memory
161 BIS / LDC / ID correction part

Claims (2)

The error check code that has been scrambled and the first error correction code sequence that has been subjected to the error correction process on the first data, and a part of the scramble initial setting value for the scramble process for the first data are partly used. Recording medium that is modulated and recorded after second error correction code sequences obtained by performing error correction processing on second data including a sector address to be encoded are independently multiplexed in predetermined error correction block units From the above, the first and second error correction code sequences are reproduced and demodulated, extracted from the demodulated second data, and further error-corrected or interpolated based on the continuity of the sector address Demodulation means for outputting the sector address as the first sector address;
A buffer memory having a capacity corresponding to a plurality of the error correction blocks, which stores the first sector address together with the first and second error correction code sequences output from the demodulation means, and one error correction block Storage means comprising a working memory having a capacity of minutes,
The information for one error correction block among the information composed of the first and second error correction code sequences for the plurality of error correction blocks stored in the buffer memory and the first sector address is stored in the buffer memory. is stored in the working memory, an error correction processing means for performing sequentially in said one error correction block units to carry out error correction processing of the stored in the working memory one of the information of the error correction block,
Extracting means for extracting all of the plurality of second sector addresses by setting a sector address included in the second data subjected to error correction processing by the error correction processing means as a second sector address;
Error checking means for checking all errors of the plurality of second sector addresses extracted by the extracting means;
As a result of the error check, the error check code of the one error correction block output from the working memory with a descrambling initial setting value based on any second sector address obtained as no error, and First descrambling means for descrambling the first data and storing the first data in the working memory;
As a result of the error check, when it is determined that all of the plurality of second sector addresses are errors, a descrambling initial setting value based on the first sector address output from the working memory, Second descrambling processing means for descrambling and storing the error check code and first data of the one error correction block output from the working memory in the working memory;
When the first data that has been descrambled by the first or second descramble processing unit is subjected to error checking using the error check code after descrambling, and the first data has an error Is an error check and retry means for replaying the one error correction block stored in the working memory from the recording medium;
Write back means for storing at least the first data in the working memory including the error check code and the first data after descrambling processing by the first or second descrambling processing means in the buffer memory. When,
A decoding device characterized by comprising: The error check code that has been scrambled and the first error correction code sequence that has been subjected to the error correction process on the first data, and a part of the scramble initial setting value for the scramble process for the first data are partly used. Recording medium that is modulated and recorded after second error correction code sequences obtained by performing error correction processing on second data including a sector address to be encoded are independently multiplexed in predetermined error correction block units A computer program for use in a decoding device for reproducing and decoding the first and second error correction code sequences,
The computer,
The first and second error correction code sequences reproduced from the recording medium are reproduced and demodulated, extracted from the demodulated second data, and further error-corrected or the continuity of the sector addresses. Demodulating means for outputting the sector address interpolated based on the first sector address;
Write means for writing the first sector address together with the first and second error correction code sequences output from the demodulation means to a buffer memory having a capacity for a plurality of error correction blocks;
The information for one error correction block among the information composed of the first and second error correction code sequences for the plurality of error correction blocks stored in the buffer memory and the first sector address is stored in the buffer memory. is stored in the working memory, an error correction processing means for performing sequentially in said one error correction block units to carry out error correction processing of the stored in the working memory one of the information of the error correction block,
Extracting means for extracting all of the plurality of second sector addresses by setting a sector address included in the second data subjected to error correction processing by the error correction processing means as a second sector address;
Error checking means for checking all errors of the plurality of second sector addresses extracted by the extracting means;
As a result of the error check, the error check code of the one error correction block output from the working memory with a descrambling initial setting value based on any second sector address obtained as no error, and First descrambling means for descrambling the first data and storing the first data in the working memory;
As a result of the error check, when it is determined that all of the plurality of second sector addresses are errors, a descrambling initial setting value based on the first sector address output from the working memory, Second descrambling processing means for descrambling and storing the error check code and first data of the one error correction block output from the working memory in the working memory;
When the first data that has been descrambled by the first or second descramble processing unit is subjected to error checking using the error check code after descrambling, and the first data has an error Is an error check and retry means for replaying the one error correction block stored in the working memory from the recording medium;
Write back means for storing at least the first data in the working memory including the error check code and the first data after descrambling processing by the first or second descrambling processing means in the buffer memory. When,
A computer program characterized by functioning as a computer program.

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