JP3768640B2 - Playback device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a playback apparatus, and more particularly to a playback apparatus for a digital signal.
[0002]
[Prior art]
Conventionally, a digital VTR that records and reproduces an image signal on a magnetic tape as a digital signal is known as this type of device.
[0003]
In a digital VTR, normally, parity data for correcting an error associated with recording / reproduction is added to a digital image signal and recorded by error correction coding. The reproduced digital image signal is stored in a memory, and an error is recorded. An error in the reproduction signal is corrected by accessing the memory by the correction circuit.
[0004]
In the digital VTR, in addition to the normal playback mode in which the tape is transported at the same speed as when recording and the digital signal is reproduced, the search mode in which the tape is transported at a speed higher or lower than that during recording and the digital signal is reproduced. Some have a slow playback mode.
[0005]
[Problems to be solved by the invention]
Now consider slow playback.
[0006]
When a digital signal is recorded on each track on the tape by azimuth recording, the envelope of the reproduction signal obtained by one tracing of each head fluctuates during slow reproduction. As a result, there are few errors or corrections for the large envelope part, but there are too many errors for the small envelope part, making correction impossible or erroneous correction.
[0007]
Further, as described above, at the time of slow reproduction, the tape is transported at a lower speed than that at the time of recording to reproduce the digital signal, so that each track on the tape is traced a plurality of times by the head.
[0008]
In a digital VTR, an image signal reproduced according to ID data added to a digital signal is usually written in a memory.
[0009]
In other words, during slow playback, an image signal having the same ID data is played multiple times, so even if the signal is played back from the same track, a signal with few errors (high reliability) is written to the memory. After that, a signal with many errors (low reliability) reproduced from the same track may be overwritten again.
[0010]
An object of the present invention is to solve the above-described problems.
[0011]
Another object of the present invention is to enable a highly reliable signal to be written in a memory among reproduced signals.
[0012]
[Means for Solving the Problems]
In order to solve the above problems and achieve the object, the present invention comprises a plurality of synchronization blocks each including synchronization data, a predetermined amount of digital image data, ID data indicating the number of the synchronization block, and parity data, Reproducing means for reproducing digital data encoded with error correction coding using parity data from a recording medium, storage means for storing parity data and digital image data reproduced by the reproducing means, and for the storage means An error correction unit that accesses and corrects an error in the digital image data using the parity data; and determines a write address in the storage unit of the digital image data and parity data according to the ID data; and the parity data The digital image in units of the synchronization block using To detect errors in the data, and a control means for controlling the operation of storing the parity data and the digital image data outputted from said reproducing means to said memory means in accordance with a detection result of the error.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0014]
FIG. 1 is a diagram showing the configuration of a digital VTR to which the present invention is applied.
[0015]
In FIG. 1, a digital image signal is reproduced by a head unit 101 from a tape T on which a number of helical tracks having different azimuth angles are formed between adjacent tracks, and a binarization circuit 107 is connected via an amplifier 103 and an equalizer 105. And output to the clock generation circuit 139. In this embodiment, the head unit 101 has two rotary heads having different azimuths, and the digital signal is reproduced by alternately tracing the tape T with these rotary heads.
[0016]
The digital VTR according to the present embodiment transports the tape T at a speed slower than that in the normal playback mode, as well as the normal playback mode in which the tape T is transported at the same speed as the recording and reproduces the digital signal. There are a slow reproduction mode for reproduction and a search reproduction mode for reproducing the digital signal by transporting the tape T at a higher speed than in the normal reproduction mode, and these modes are switched by a system controller (not shown).
[0017]
The clock generation circuit 139 includes a PLL circuit and a counter, generates a symbol clock that is phase-synchronized with the reproduction data, outputs the symbol clock to the counter 111, divides the symbol clock using the counter, and generates a byte clock, one sync block Output the clock of each unit.
[0018]
The binarization circuit 107 restores the input digital signal to a 1-sample 1-bit digital signal and outputs it to the synchronization detection circuit 109, the ID detection circuit 113, and the FIFO 115.
[0019]
In the digital VTR of this embodiment, sync data SYNC, ID data, and ID parity for error detection of ID data are added to each predetermined amount of digital image signal to form a sync block, and further, for each recording data for one track The outer code parity C2 and the inner code parity C1 are added to the error code and recorded.
[0020]
FIG. 2A shows the data structure of one sync block.
[0021]
In this embodiment, each sync block is composed of 90 bytes of data, the sync data at the head, ID data including the sync block number, etc., ID parity data for detecting an ID data error, and image / audio data Etc., and finally C1 parity data for error correction.
[0022]
Returning to FIG. 1, the synchronization detection circuit 109 detects the sync data of each sync block described above from the reproduced digital signal sequence, and outputs a sync detection signal to the counter 111 at the timing when the sync data is detected. The counter 111 is cleared in response to the synchronization detection signal from the synchronization detection circuit 109, and counts the symbol clock corresponding to the frequency of the sample of the reproduced digital signal generated by the clock generation circuit 139. Therefore, the count value of the counter 111 indicates the position from the beginning of the data in each sync block. The count result of the counter 111 is output to the ID detection circuit 113 and the data parity detection circuit 123.
[0023]
The ID detection circuit 113 extracts the ID data and ID parity of each sync block from the reproduction data supplied from the binarization circuit 107 according to the count value from the counter 111, and determines whether or not the obtained ID data is correct. Detection is performed using ID parity. As a result, when the reproduction ID data is correct, the data (sync block number) is held, and when the reproduction ID data is incorrect, a value obtained by adding 1 to the previous sync block number is set as the sync block number. Hold as. The sync block number data detected by the ID detection circuit 113 is used for a reproduction signal writing operation to the memory 127 as will be described later.
[0024]
Further, the data parity detection circuit 123 extracts information data and C1 parity of each sync block from the reproduction data supplied from the binarization circuit 107 according to the count value from the counter 111. Then, the extracted information data and C1 parity are input to a determined Galois field polynomial to perform calculation, and it is detected whether or not there is an error in the information data. If there is no error, a logic H is output to the monomulti 125, and if there is an error, 1-bit error flag data indicating the logic L is output.
[0025]
The data parity detection circuit 123 will be described with reference to FIG.
[0026]
FIG. 3 is a diagram showing a configuration of a main part of the data parity detection circuit 123. In the figure, reproduction data extracted from an extraction unit (not shown) and output in parallel in units of 8 bits is supplied from a terminal 201 to EXOR circuits 202 and 203. The EXOR circuit 202 performs an exclusive OR operation on the 8-bit data fed back via the switch 204 and the latch 207 and the input data, and outputs the result to the switch 204. When the count value of the counter 111 becomes a value indicating the start position of the data area of each sync block, the switch 204 is set to “00000000” data at a timing when a signal output from a timing signal generator (not shown) is supplied. In other cases, the output of the EXOR circuit 202 is selected. Thereafter, the EXOR circuit 202 performs an exclusive OR operation on the input data in units of 8 bits.
[0027]
The EXOR circuit 203 performs an exclusive OR operation on the 8-bit data fed back via the switch 205, the latch 208 and the conversion circuit 206 and the input data, and outputs the result to the switch 205. The switch 205 selects “00000000” data at the head of the data area of each sync block, and selects the output of the EXOR circuit 203 otherwise.
[0028]
Here, the conversion circuit 206 is configured as shown in FIG. 4, converts the logic of each hit of 8-bit data supplied from the latch 208 as shown in the figure, and outputs it to the EXOR circuit 203.
[0029]
The 8-bit output data from the latches 207 and 208 are output to the NAND circuits 209 and 210, respectively, and the output of each NAND circuit is further output to the AND circuit 211. The output of the AND circuit 211 is output to the latch 213 via the switch 212 and latched for each sync block.
[0030]
Here, the operation timing of the switch will be described.
[0031]
The switch 212 has a timing (not shown) at the next timing when the count value of the counter 111 reaches the end of the data parity of each sync block, that is, the value indicating the position of the 85th byte from the top of the data area of each sync block. The output of the AND circuit 211 is output to the latch 213 in accordance with the signal supplied from the signal generator.
[0032]
In this embodiment, from the beginning of the data area of each sync block, calculation is performed every 8 bits by EXOR 202 and 203, and when calculation of the last 1 byte of data parity is completed, if there is no error, NAND 209 and 210 Logic H is output.
[0033]
The switch 212 is for outputting only the calculation result up to the last one byte of data to the latch 213, and the calculation result latched by the latch 213 is held for one sync block period.
[0034]
The operation timings of the switches 204 and 205 and the switch 212 are shown in FIGS. The switches 204 and 205 select “00000000” in accordance with the timing signal shown in FIG. Further, the switch 212 selects the output of the timing AND 211 shown in FIG.
[0035]
As described above, the data latched by the latch 213 indicates the logical product of the results of the operations performed on the data of one sync block by the EXOR circuits 202 and 203, respectively. When logic L, that is, when each NAND circuit 209, 210 outputs logic H, there is no error.
[0036]
Normally, when 8-bit data is processed in parallel, there are eight Galois field generator polynomials, and when performing error correction, all polynomials must be calculated. When it is only necessary to do this, it is sufficient to perform two or three polynomial operations as shown in FIG.
[0037]
In FIG. 1, the output from the data parity detection circuit 123 is supplied to the monomulti 125. When a signal of logic H is input from the data parity detection circuit 123, the mono multi 125 outputs a signal of logic H for (2n + 1) sync block periods and returns to logic L. Further, when the logic H is further supplied when the logic H is being output, the so-called retriggerable is configured so that the logic H is further output from that point in time by (2n + 1) sync block periods.
[0038]
In this embodiment, n = 2 and the mono-multi 125 is constituted by four D-FFs and an OR circuit.
[0039]
The output of the mono multi 125 is used to control the switches 119 and 121, and each switch is closed when the output of the mono multi 125 is logic H.
[0040]
On the other hand, the output of the binarization circuit 107 is delayed by (n + 1) sync block periods by the FIFO 115 and is output to the track memory 127 via the switch 119 when the output from the mono multi 125 is logic H.
[0041]
Similarly, the ID data detected by the ID detection circuit 113 is delayed by (n + 1) sync block periods by the FIFO 117 and is output to the memory control circuit 141 via the switch 121 when the output from the monomulti 125 is logic H.
[0042]
The memory control circuit 141 determines the reproduction data write address according to the ID data supplied via the switch 121 and writes the reproduction data supplied via the switch 119 to the corresponding address in the track memory 127.
[0043]
When the memory control circuit 141 writes the reproduction data for one track in the track memory 127, the memory control circuit 141 notifies the error correction circuit 129 to that effect and activates the error correction circuit 129.
[0044]
Here, FIG. 5 shows the structure of image data for one track.
[0045]
In this embodiment, image data for one track is composed of 151 sync blocks, sync block numbers 0 to 140 are sync blocks including image data, and 141 to 151 are outer code C2 parity data for image data. It is a sync block that includes.
[0046]
The error correction circuit 129 performs error correction processing on the product code configuration data stored in the memory 127 several times in the order of the C1 direction and the C2 direction.
[0047]
The image data corrected by the error correction circuit 129 is output to the decompression circuit 131. The amount of information of the image data recorded in this embodiment is compressed by DCT, variable length coding, etc., and the decompression circuit 131 decompresses the amount of information of the image data reproduced by variable length code decoding, inverse CDT, etc. Then, the data is written into the video memory 133.
[0048]
The image data written in the video memory 133 is read in the order of raster scan, the luminance signal is output from the terminal 139 via the D / A converter 135, and the color difference signal is output via the D / A converter 137. Is output.
[0049]
Here, the relationship between the output data of the FIFO 115 and the output of the data parity detection circuit 123 output to the memory control circuit 141 via the mono-multi 125 will be described with reference to FIG.
[0050]
In the figure, the data for one sync block output from the binarization circuit 107 is A. B shows the detection result of the data parity detection circuit 123 of the data for one sync block. That is, whether or not there is an error in the information data is not known unless all the C1 parity is input, so that the detection result is output from the data parity detection circuit 123 at the timing indicated by B.
[0051]
The output of the data parity detection circuit 123 is supplied to the mono multi 125, and the result output from the mono multi 125 is C.
[0052]
In this embodiment, when there is no error in a certain sync block, there is little possibility that the previous and next sync blocks have an error. Therefore, there is no error in the sync block shown in A, and a signal of logic H is output from the data parity 123. When output, a signal of logic H is output from the monomulti 125 during the two sync block periods including the one sync block period shown in B, for a total of five sync block periods, and the reproduction data from the FIFO 115 to the memory 127 Is allowed to write. This situation is shown in D.
[0053]
As described above, in this embodiment, when the reproduction data is written to the memory and the error correction processing is performed on the data written to the memory, the presence or absence of an error in the reproduction data is detected before the data is written to the memory, and the detection result To control writing to the memory.
[0054]
Therefore, even when data is played multiple times from the same track, such as during slow playback, there are many errors and low-reliability data can be detected before it is written to the error correction memory. It is possible to prevent data with many errors from being overwritten after data is written to the memory.
[0055]
In this embodiment, the mono-multi 125 outputs a signal having a logic high level of 5 sync blocks. However, the value of n may be appropriately set to be 3 sync blocks or 7 sync blocks.
[0056]
In this embodiment, the presence or absence of reproduction data and address data is delayed by the FIFOs 115 and 117. However, the FIFO and the memory control circuit may be supplied as they are without providing the FIFO.
[0057]
【The invention's effect】
As described above, according to the present invention, it is possible to detect the presence or absence of an error in the reproduction data before storing the reproduction data in the error correction storage means, and write data with low reliability. Can be prevented.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of a digital VTR according to an embodiment of the present invention.
FIG. 2 is a diagram showing a format of data by the apparatus of FIG. 1;
FIG. 3 is a diagram showing a configuration of a data parity detection circuit in FIG. 1;
4 is a diagram showing a configuration of a conversion circuit in FIG. 3. FIG.
FIG. 5 is a diagram showing a data format by the apparatus of FIG. 1;
FIG. 6 is a timing chart for explaining the operation of the apparatus of FIG. 1;
[Explanation of symbols]
113 ID detection circuit 123 Data parity detection circuit 127 Track memory

Claims (6)

Each of the recording data includes a plurality of synchronization blocks each including synchronization data, a predetermined amount of digital image data, ID data indicating the number of the synchronization block, and parity data, and error correction encoded using the parity data Playback means for playing from,
Storage means for storing parity data and digital image data reproduced by the reproducing means;
Error correction means for accessing the storage means and correcting errors in the digital image data using the parity data;
A write address in the storage means for the digital image data and parity data is determined according to the ID data, and an error in the digital image data is detected in the synchronization block unit using the parity data, and the error detection result And a control means for controlling the storage operation of the parity data and digital image data output from the reproduction means for the storage means.   2. The reproducing apparatus according to claim 1, wherein the control means writes digital image data and parity data for n blocks (n is an integer) before and after the synchronous block not including an error into the storage means.   3. The reproducing apparatus according to claim 2, further comprising delay means for delaying the reproduced digital data and the parity data by (2n + 1) synchronization block periods and outputting the delayed data to the storage means.   The recording medium includes a tape-shaped recording medium on which a number of helical tracks are formed, and the reproducing means includes rotating head means for reproducing the digital image data by tracing the tape-shaped recording medium. Item 4. The playback device according to Item 1.   2. The reproducing apparatus according to claim 1, wherein the control means includes calculation means for calculating a generator polynomial smaller than a generator polynomial necessary for the error correction means to correct the error.   2. The reproducing apparatus according to claim 1, wherein the control means detects the error without correcting an error in the digital image data using the parity data.

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