JPH1186465A - Signal processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the ratio of the redundant data and to improve vibration- proof, impact resistance by writing the main data on an error correction block in a first area of a memory area, writing all or its parts of the redundant data in a second area and performing the error correction of the main data stored in the first area based on the redundant data recorded on the second area. SOLUTION: A control part 20 secures a data amount much of a PO parity of a 2 ECC block on a DRAM 21 as a redundant data area, and toggles at every ECC block, and superscribes the PO parity of respective 13 rows to write in. Further, when the control part 20 receives a write-in request signal, the part 20 sends successively a data area write-in address INC, request signal and a redundant area write-in address INC, request signal respectively to a disk data area write-in address counter 106a, and a redundant area write-in address counter 106b for an address generation part 22 to count respective addresses.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing apparatus for processing a signal reproduced from a medium such as a DVD (Digital Video Disk), and more particularly to a signal processing apparatus for processing main data.
The present invention relates to a signal processing device that processes data to which redundant data (parity) for CC (error correction code) correction processing is added.

[0002]

2. Description of the Related Art In general, on a DVD disk, a transfer rate is high (a large amount of data per unit time) for a complicated and fast-moving image, while a transfer rate is low (a unit for a simple and little-moving image). (The amount of data per hour is reduced). Therefore, in a normal DVD drive device, the work R for ECC processing is performed.
Two RAMs, the AM and the buffer RAM for the variable transfer rate, are used.
Sharing by one buffer is also performed. Generally, a buffer RAM requires a large capacity (4 Mbits), so a DRAM is used.

An ECC block has a P
I parity and PO parity are added and interleaved, and when this is written to the buffer RAM, the following 2 is used.
There is a street. The first is a method of writing after deinterleaving (after deinterleaving), and the second is a method of writing without deinterleaving and deinterleaving at the time of reading for ECC processing or the like. In each case, the main data and the parity data in the ECC block are written in the memory at the same ratio as in the format, and the main data is read from the memory while skipping the parity when the data is transferred to the image / audio decoder after the ECC correction is completed.

[0004]

However, in the above-mentioned conventional method, the main data and the parity data in the ECC block are written into the memory at the same ratio in the format. For example, in the case of a DVD, the parity occupies in the memory. The ratio is about 13%, so that there is a problem that the memory cannot be used effectively.

[0005] When vibration or shock is applied to the drive device during a seek operation, the process of writing the reproduced data from the medium to the memory is stopped, but the output to the image / audio decoder (memory) is stopped. ) Is not stopped, so it is better to accumulate a lot of valid data in the memory. Also, if the seek distance is long and the seek time is long, or if a large vibration or impact is applied, the memory may be emptied and the reproduction of images and sounds may be interrupted. Is easy to join. Note that the memory is 4 Mbytes and the average transfer rate is 4 M
In the case of bps, since 1.04 seconds of data for 8 seconds is a redundant area, substantial reproduction is about 7 seconds, and about 1 second is wasted.

The present invention has been made in view of the above-mentioned conventional problems, and has as its object to provide a signal processing device which is excellent in vibration resistance and shock resistance by reducing the ratio of redundant data in a memory.

[0007]

According to the present invention, in order to attain the above object, a memory area is written in at least main data on an error correction block (only main data or main data + PI data is written). Area and a second area for writing all or a part of redundant data (for writing PI, PO data or only PO data) and writing main data and redundant data to the first and second areas, respectively. It is like that. That is, according to the present invention, in a signal processing apparatus for processing a signal reproduced from a medium on which an error correction block in which main data and redundant data for error correction are configured at a predetermined ratio is recorded, the signal is reproduced from the medium. A memory for temporarily storing the redundant data, an area of the memory for storing at least a first area for main data on the error correction block, and a second area for writing all or a part of redundant data.
Memory control means for writing main data and redundant data reproduced from the medium into the first and second areas, respectively, based on the redundant data stored in the second area of the memory. An error correction unit that corrects an error of the main data in the error correction block stored in the first area.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the signal processing device according to the present invention, FIG. 2 is an explanatory diagram showing ECC blocks and interleaving of the DVD of FIG. 1, and FIG. 3 is an explanatory diagram showing physical sectors of the DVD of FIG. FIG. 4 is an explanatory view showing the area of the DRAM of FIG. 1 and the write and ECC correction processing.

In FIG. 1, a signal read from a disk 11 by a pickup 12 is applied to an RF amplifier / slicer / equalizer (EQ) / bit PLL circuit 13 to extract a bit clock. Following NRZ conversion /
The sync detection / protection circuit 14 performs NRZ conversion of the reproduced data based on the bit clock, detects a frame sync (synchronization) signal and a sector sync signal, and when a sync signal is missing due to a defect or the like, a pseudo sync signal. Is inserted and protected. This data is sent to the data input / output control unit 16 and the ID detection / correction unit 17 via the 8/16 demodulation unit 15. ID detection / correction unit 1
7, an ECC block sync generation unit 18 detects an ID including a sector address and the like, and detects an ECC block sync signal at the head of the ECC block.

Here, in the DVD, as shown in FIGS. 2 and 3, one sector is composed of 13 rows, and each of the first to twelfth rows has a frame sync signal for 172 (91 + 81) bytes of main data. (Frame Sync), a sector sync signal (Sector Sync) and a 10-byte PI parity are added (interleaved).
The third row contains the frame sync signal and the sector sync signal and 17
It is composed of 2-byte PO parity and 10-byte PI parity. And these 16 sectors are 1EC
A C block is configured, and an EC
C correction processing is performed. The main data refers to 2048 bytes in the DVD format, but in this specification, data including data sector ID, IEC, RSV, and EDC, that is, data excluding PI and PO parities.
Then, the ratio of the PI and PO parities in this format (excluding the sync signal) is (182 + 10 × 12) /
(182 × 13) ≒ 12.8%.

Therefore, the control unit 20, as shown in FIG.
A data amount of PO parity of 2 ECC blocks (182 x 16 x 2 bytes in each of 13 sectors of 16 sectors x 2 ECC blocks) of 2 ECC blocks is secured in the DRAM 21 as a redundant data area, and the 13 th rows of each of the 16 sectors are secured. ECC area
Toggle for each block, PO for 13th row of 16 sectors
Overwrite parity (and PI parity).
Another area is reserved for main data and PI parity data in the sectors in the first to twelfth rows. Similarly, if the PI parities in the first to twelfth rows are similarly written in the redundant data area, the ratio of the parity is reduced. However, only the PO parity data (and the PI parity data) in the thirteenth row is easier to manage the address. Become.

The frame sync signal and the sector sync signal detected by the NRZ conversion / sync detection / protection circuit 14, the write request signal from the 8/16 demodulation unit 15, and the ECC block detected by the ECC block sync generation unit 18 The sync signal is sent to the control unit 20.
The control unit 20 controls the EC shown in FIG. 3 based on these signals.
Data for 24 frame sync signals from the beginning of the C block, that is, main data for the first to twelfth rows, PI
Parity data is written to the main data and PI parity data area of a DRAM (hereinafter, memory) 21 and data input / output is performed so that the remaining two frame sync signals, that is, PO data of the thirteenth row are written to the redundant data area of the memory 21 It controls the control unit 16, the address generation unit 22, and the like. Further, the control unit 20 monitors addresses so that data accesses to the memory 21 do not overlap based on a request signal from each block, and controls, for example, that reading by the ECC unit 23 does not precede writing to the medium.

Referring to FIG. 4, writing of reproduction data to the DRAM 21 and access by the ECC unit 23 will be described. First, the main data, PI parity data, and PO parity data of the first ECC block from the disk 11 are written into the DRAM 21, and then the main data, PI parity data, and PO parity data of the next ECC block are written into the DRAM 21, and the ECC unit 2
3 reads the data of the first ECC block from the DRAM 21, detects an error, and performs correction (ECC correction processing). Next, the main data of the third ECC block,
PI parity data and PO parity data in DRAM
21, the PO parity is set to the first EC
Overwrite the area of the 13th row of 16 sectors where the PO parity of the C block is stored, and at this time, perform the ECC correction processing of the second ECC block.

Similarly, the PO parity of the fourth ECC block is overwritten on the area where the PO parity of the second ECC block is stored, and the ECC correction processing of the third ECC block is performed at the same time. That is, since the PO parity of the ECC block is unnecessary after performing the ECC correction processing, the PO parity of the k-th ECC block is overwritten on the area storing the PO parity of the (k-2) -th ECC block. , And at the same time the k-1st ECC
ECC correction processing of the block is performed.

Next, a specific operation will be described. First, when the control unit 20 receives a write request signal from the 8/16 demodulation unit 15, it sends a data area write address INC. To the address generation unit 22. Request signal and redundant area write address INC. The request signals are sequentially sent to the data area write address counter 106a and the redundant area write address counter 106b in the disk data write address generator 106, whereby the counters 106a and 106b are enabled, and the data write area address and the redundant area Count write addresses.

At the same time, the control unit 20 controls the multiplexer (M
By sending an address selection signal for selecting the counters 106 a and 106 b to the PX) 108, the data write area address and the redundant area write address of the counters 106 a and 106 b are selected by the multiplexer 108 and sent to the DRAM 21.

Further, the control unit 20 is a data input / output control unit 1
6 by sending a data selection signal to 8/16
Output data of the demodulation unit 15 is sent to the DRAM 21 via the data input / output control unit 16. Further, from the control unit 20 to the DR
The write enable signal WE and the strobe signal are sent to the AM 21, whereby the output data of the 8/16 demodulation unit 15 is written to the main data, the PI data area, and the redundant data area in the DRAM 21. Although not shown, in the DRAM 21, a strobe signal is usually a RAS (row address strobe) signal and a CAS (column a).
ddress strobe) signal and the upper address is RAS
Since the signal is strobed and the lower address is strobed by the CAS signal, each counter in the address generator 22 outputs the upper address and the lower address separately.

Next, the ECC unit 23 reads data of the first to thirteenth rows × 16 sectors from the DRAM 21 and performs an error correction process on the main data based on the PI parity data and the PO parity data. In this case, the control unit 20
After receiving an ECC read request from the ECC unit 23, if data for one ECC block has been written to the DRAM 21, a PI read address counter 101 for generating a PI code word address and a PO code word address are generated. PO read address counter 102 with ECC read address INC. A request signal and a PI / PO signal indicating PI correction or PO correction are transmitted, and counters 101 and 102 are enabled to generate an ECC read address. At this time, similarly, the control unit 20 sends an address selection signal to the multiplexer 108 so that the ECC read address is selected by the multiplexer 108 and sent to the DRAM 21.

At the same time, the control unit 20 sends a PI / PO signal to the ECC unit 23 to instruct whether to perform PI correction or PO correction. The control unit 20 is a DRAM
21 and a read enable signal OE is sent. Further, the control unit 20 sends a data selection signal to the data input / output control unit 16 so that the data read from the DRAM 21 is transmitted to the data input / output control unit 16 via the ECC.
Sent to the unit 23.

Although not shown, in the case of PO code word reading, the main data in which the data of the first to twelfth rows of the sector are recorded and the data in the PI data area for 16 sectors are arranged in the column direction. After the read, the data area read counter reads the main data, the PI data and the PI data so that the PO data of the redundant data area in which the data of the thirteenth row of the sector is recorded is read for 16 sectors in the column direction.
The data read address is counted, and the redundant area read counter counts the PO data read address.

When writing data to the DRAM 1 in the order of data input (in the order of PI direction), the data area read counter and the redundant area read counter count up by +1 each time a PI word code is read, and +182 when reading a PO word code. Count up by one. The data area read counter skips the redundant area and counts up, and the redundant area read counter skips the data area and counts up. For example, the redundant area read counter decodes the output of the redundant area read counter after the completion of the writing of the two ECC blocks, and loads the redundant area and the initial address.

Next, the ECC unit 23 responds to the ECC read data from the
PI correction or PO correction is performed based on the PO signal. In this case, the error detection unit 23a detects an error from the input data sequence and, if an error exists, an error location (PI: 0 to 181; PO: 0 to 287) indicating in which data the error exists. ) And an error value (difference between a normal value and an incorrect value).
The error correction unit 23b outputs the data having an error to the DRAM 1
After reading and correcting the error data, the error location is sent to the correction address generation unit 103 and a correction read request signal is sent to the control unit 20 in order to write the correction data to the DRAM 1.

When the control unit 20 receives the corrected read request signal, the control unit 20 sends the corrected address request signal to the address generation unit 2.
2 and an address selection signal for selecting the correction address generator 103 to the multiplexer 108. The correction address generation unit 103 determines the error location and the ECC
Start address of PI code word or PO code word at the time of data reading (top address of each row in case of PI correction, top address of each column in case of PO correction)
To generate a correction address and output it.

Here, in PI correction, an error location and a start address may be simply added.
In the correction, an error location is determined using the error location to determine whether an error is present in the main data, the data in the PI data area, or the data in the redundant data area to generate a correction address. Briefly, the start address of the data area read counter at the time of ECC read and the start address of the redundant area are used as the start address, and N × 182 is added to the start address of the data area read counter until the error location N is 0 to 191. When the error location N is 192 to 207, the start address of the redundant area read counter is (N-192) × 18.
What is necessary is just to add 2.

The control section 20 sends a data selection signal to the data input / output control section 16 to send the data with error (data before correction) read from the DRAM 1 to the error correction section 23b. An enable signal OE and a strobe signal are sent to the DRAM 1. The error correction unit 23b adds an error value to the input data to calculate normal data, and then sends a correction write request signal to the control unit 20. In response to this, the control unit 20 sends an address selection signal for selecting the correction address generation unit 103 to the multiplexer 108, and sends a write enable signal WE and a strobe signal to the DRAM 1. At this time, the write address generated by the correction address generation unit 103 is the same as that at the time of reading, so that the error correction unit 23b can write correction data to the DRAM 1.

In the ECC correction process, one set of PI correction and P
When ending with O correction, PI correction is performed 208 times per ECC block (208 rows = 13 rows × 16 sectors).
After performing, the process proceeds to the PO correction process. PI parity (1
Since the PO correction for the 73rd to 182nd columns) does not need to be performed, it is performed 172 times per ECC block. PO
When the correction is completed, the data is read out to the EDC (error detection code) unit 25 while descrambling the data from the DRAM 1 (shown in FIG. 24), and the erroneous correction of the data by the ECC correction is determined. Here, the control unit 20 sends the EDC read address INC. The request signal is output to the EDC address counter 104, the address selection signal is sent to the multiplexer 108, and the read enable signal OE and the strobe signal are sent to the DRAM 1. Although not described in detail, EDC is performed only on main data excluding ID and parity.

After the EDC correction is completed, the control unit 20
When a decoder read request signal is received from the PEG decoder, a signal for selecting the decoder data read address counter 107 is sent to the multiplexer 108 in order to read the data from the DRAM 1 while descrambling the data (FIG. 26) to the MPEG decoder. Enable signal OE and strobe signal to DRAM
Send to 1. In this example, in order to reduce the number of accesses to the DRAM 1, data is stored in a scrambled state on the DRAM 1, and the data is stored in the EDC unit 25 or the MPEG.
Although descrambling is performed at the time of reading to the decoder, the present invention is not limited to this.

Further, according to the above embodiment, only 32 rows of PO parity are written in the DRAM 1 and the
By overwriting this for each ECC block after the C correction processing, the ratio of redundant data in the DRAM 1 is reduced to about 7.7.
%, And about 13% can be reduced by performing PI parity, so that vibration resistance and shock resistance can be improved. Further, the present invention is not limited to the above embodiment, and can be applied to all cases where data to which parity for error correction is added is processed.

[0029]

As described above, according to the present invention, the memory area is divided into at least the first area for writing the main data on the error correction block and the second area for writing all or a part of the redundant data. The main data and the redundant data are written in the first and second areas, respectively, so that the ratio of the redundant data in the memory can be reduced, and the vibration resistance and shock resistance can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an embodiment of a signal processing device according to the present invention.

FIG. 2 is an explanatory diagram showing ECC blocks and interleaving of the DVD of FIG. 1;

FIG. 3 is an explanatory diagram showing physical sectors of the DVD of FIG. 1;

FIG. 4 is an explanatory diagram showing a DRAM area of FIG. 1 and write and ECC correction processing;

[Explanation of symbols]

Reference Signs List 16 DRAM (memory) 20 Control unit (constitutes memory control unit with address generation unit) 22 Address generation unit 23 ECC unit (error correction unit)

Claims (3)

[Claims] 1. A signal processing apparatus for processing a signal reproduced from a medium in which information is recorded by an error correction block in which main data and redundant data for error correction are configured at a predetermined ratio, wherein the signal is reproduced from the medium. A memory for temporarily storing the data, and an area of the memory, the main data on the error correction block is divided into at least a first area and a second area for writing all or a part of the redundant data, Memory control means for writing main data and redundant data reproduced from the medium to the first and second areas, respectively; and storing the main data and redundant data in the first area based on the redundant data stored in the second area of the memory. And an error correcting means for correcting an error of the main data in the error correction block. 2. The method according to claim 2, wherein the memory control unit is configured to perform the following steps each time the error correction block is corrected by the error correction unit.
2. The signal processing apparatus according to claim 1, wherein the second area is overwritten with redundant data of a next error correction block. 3. The signal processing device according to claim 1, wherein the second area of the memory is within twice the amount of redundant data required for performing error correction.