JPH11102576A - Data-reproducing apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To fix the data length and facilitate the processing of data strings by generating an address to be fed to a recording medium from a synchronous code and a frame number in a reproduced data packet, and recording data of the reproduced data packet on the basis of the address on the recording medium. SOLUTION: A BCA detection circuit 19 deletes a line sending a recording length to a BCA data-processing circuit 22 therefrom without detecting the recording length of BCA data. In detecting the BCA data, a control MPU generates a memory initialization instruction to a memory initialization control circuit of the BCA detection circuit 19 via an input terminal. The BCA data having a not specified data length are fixed in data length by initializing contents in a BCA data-storing memory 21. Accordingly, an ECC operation process and an EDC operation process can be carried out uniformly with a process of a maximum data length irrespective of the data length of the BCA data, thereby eliminating detection of the recording length of the BCA data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a data reproducing apparatus for reproducing data having an unspecified data length.

[0002]

2. Description of the Related Art As is well known, recently, one side has about 5G.
D as an optical disk that records a huge amount of data
VD (Digital Video Disk) has been developed.
DVD playback devices for playing VD have also become widespread in the market.

By the way, as shown in FIG. 4, after the manufacturing process is completed in a factory or the like, as shown in FIG.
In a specific area further inside than the lead-in area,
A YAG laser may record a BCA (Burst Cutting Area) code.

FIG. 5 shows the structure of one packet of such BCA data. First, the number of BCA user data has a variable information area of 16n-4 (1 ≦ n ≦ 12) bytes, and a 4-byte EDC (Error Detection
Code) parity and 16-byte ECC (Error Correc)
Option and parity are added.

[0005] Then, 1 byte of sync data RSBCAn is added to the variable information area and the EDC parity every 4 bytes, and 1 byte is added to the ECC parity every 4 bytes.
Byte sync data RSBCA13 is added.

The BCA data has a 1-byte sync data SBBCA at the head thereof, each of which is "0".
0h (Hexa-decimal) "4 byte BCA-Prea
mble data is added.

Further, the BCA data is obtained by
After parity, 1-byte sync data RSBCA14
And 4 bytes of BCA-Po, each of which is "55h"
Then, 1-byte sync data RSBCA15 is added.

Then, each of the sync data SBBCA, RSBC
An, RSBCA13, RSBCA14, and RSBCA15 are each composed of eight channel bits representing a specific sync pattern and eight channel bits representing a frame number n. It is to be noted that the modulation rule is such that one bit becomes two channel bits.

Here, the number of user data in one frame is formed of 16 bytes, but only in the n-th frame, the number of user data is 12 bytes, and 4 bytes of EDC parity are added. For example, if n = 5,
The number of user data is 16 × 5-4 = 76 bytes,
After the sync data RSBCA5 in the fourth row of the fifth frame, 4
Byte EDC parity will be added.

The 16-byte Reed-Solomon ECC parity added by being interleaved in the vertical direction of the BCA data structure belongs to 13 frames regardless of the user data length. For example, if n = 5,
Sync data RSBC after EDC parity of 5 frames
A13 appears and ECC parity follows.

The BCA data is, as described above,
It is recorded with a sufficient width on the concentric circle on the inner periphery of the VD lead-in area. The shorter the data length is, the larger the data non-recording area in the BCA data recording area on the DVD becomes. ing.

The modulation rule of the BCA data is as follows:
1-bit data representing “0” and “1” includes “1”
Two channel bits of “0” and “01” are respectively assigned.The specific sync pattern is “01000110” from the top, and the following frame numbers are:
According to the above-described modulation rule, 4-bit data representing "0" to "13" is modulated into 8 channel bits.

According to this modulation rule, the minimum polarity inversion interval Tmin of data is 1T, and the maximum polarity inversion interval Tmin is 1T.
max becomes 4T, and this 4T pattern appears only in the sync data.

FIG. 6 shows a disk reproducing apparatus capable of reproducing an optical disk on which such BCA data is recorded. In FIG. 6, reference numeral 11 denotes an optical disk on which BCA data is recorded, which is rotated by a disk motor 12. Further, an optical pickup 13 is provided so as to face the signal recording surface of the optical disk 11.

The disk motor 12 includes a servo circuit 1
4 controls the rotation speed. The optical pickup 13 performs a tracking servo and a focus servo for an objective lens (not shown) by a servo circuit 14,
Is controlled in the radial direction.

Here, when reproducing the BCA data of the optical disk 11, a control MPU (Micro-Processing Unit) 15 which controls the operation of the disk reproducing apparatus in a comprehensive manner is controlled by the servo circuit 14 to reproduce the BCA data from the optical disk 11. 24Hz (1440rpm) which is the most suitable rotation speed
(Constant Angular Velocity) servo to keep the optical pickup 13
Move to the data recording area.

An electric signal corresponding to the BCA data output from the optical pickup 13 is supplied to the amplifying circuit 1.
After passing through 6 and the equalizer circuit 17, the data is supplied to the data slice circuit 18 and binarized. The binarized signal is supplied to a BCA detection circuit 19 and a PLL (Phase Locked Loo
p) is supplied to the circuit 20.

The PLL circuit 20 generates a channel bit clock from the input binary signal,
The signal is output to the A detection circuit 19. The BCA detection circuit 19 extracts data from the input binary signal based on a channel bit clock, and generates a BCA detection channel bit.

The BCA detection circuit 19 detects a sync pattern from the BCA data stream based on the channel bit clock and the BCA detection channel bits, and demodulates the subsequent 8 channel bits of data. Get the frame number.

Thereafter, the BCA detection circuit 19 generates a line number within the frame from 0 to 3 for the obtained frame number, determines an address for the BCA data storage memory 21, and outputs the demodulated BCA data. Store them sequentially. When the BCA data is the longest, that is, when n = 12, 208 bytes are recorded in the BCA data storage memory 21.

The BCA data recorded in the BCA data storage memory 21 is stored in a BCA data processing circuit 22.
Error correction processing based on ECC parity,
Further, error detection based on the EDC parity is performed.

FIG. 7 shows details of the BCA detection circuit 19. That is, the BCA binarized signal output from the data slice circuit 18 is output to the data bus via the demodulation circuit 19b and the output terminal 19c after passing through the input terminal 19a, and the sync detection circuit 19e
Is supplied to The channel bit clock output from the PLL circuit 20 is supplied to the demodulation circuit 19b and the sync detection circuit 19e via an input terminal 19d.

The output of the demodulation circuit 19b and the output of the sync detection circuit 19e are output to an address bus via a memory address generation circuit 19f and an output terminal 19g, and are also output to a BCA recording length detection circuit 19h and an output terminal 19i. Via the BCA data processing circuit 22.

Here, when the optical pickup 13 reaches the BCA data recording area from the data non-recording area of the optical disk 11, a channel bit starting from the sync data SBBCA is detected. Then, when the sync data SBBCA and the BCA-Preamble data are reproduced, the PLL circuit 20 is locked, and a normal channel bit clock can be obtained.

At this time, in the BCA detection circuit 19,
First, the sync pattern of the sync data RSBCA1 is detected, and an address 0 is generated in the BCA data storage memory 21. After that, the BCA detection circuit 19 performs data demodulation processing to make one byte every 16 channel bits detected, and increments the address each time.

In this way, the 4-byte data is stored in B
At the time when the data is recorded in the CA data storage memory 21, next, the sync data RSBCA1 should be detected again. However, even if the sync data RSBCA1 cannot be detected, the BCA detecting circuit 19 detects the sync data pseudo. The so-called synchronization protection is continuously performed without changing the data demodulation interval and the address increment.

The BCA detection circuit 19 sets a sync detection window of about ± 2 channel bit widths with respect to the predicted position for detecting the sync data, and if the sync data can be detected in this window, the position correction is performed. To correct the subsequent data demodulation synchronization.

If the sync data detected at this time is a value other than RSBCA1, such as RSBCA2 or RSBCA10, the BCA detection circuit 19 regards this as a detection error and changes the address. I try not to do it.

Then, the demodulated data of 16 bytes is BC
At the time when the data is recorded in the A data storage memory 21, the next generated sync data should be RSBCA2 or RSBCA13. However, the BCA detection circuit 19 continues incrementing the address regardless of the frame number and performs data demodulation. Synchronization is continued without change.

That is, although the data demodulation synchronization is changed by the position correction of ± 2 channel bits by the sync data, the increment of the address is continued. When the address is generated in this way, the address for each byte of the user data and its EDC parity and ECC parity is generated as shown in FIG.

Data demodulation and recording are performed according to the above procedure, and when 16 bytes of data to which the sync data RSBCA13 is added are recorded, the recording operation is completed.
Next, the data recorded in the BCA data storage memory 21 is subjected to processing such as error correction and EDC error detection by the BCA data processing circuit 22. That is, in the BCA detection circuit 19, when recording the BCA data in the BCA data storage memory 21, the final data (RSBC
The recording address of A13) is held, and this address is sent to the BCA data processing circuit 22.

The BCA data processing circuit 22 first performs error correction processing using ECC parity.
Here, the ECC parity is generated by a syndrome calculation based on a vertical data permutation. Therefore, in this error correction processing, the address is advanced in the vertical direction by four columns.

That is, for example, when n = 3,
The 16-byte data with the sync data RSBCA3 attached in 4-byte units is followed by the ECC parity with the sync data RSBCA13.
Up to RSBCA1 data, and 16 to 31 are R
The data of SBCA2 is the data of RSBCA3 from 32 to 47, and the ECC of RSBCA13 is 48 to 63.
Parity.

Therefore, the addresses generated for error correction in the first column are 0 → 4 → 8 → 12 →... → 56 →
60, which means that the ECC parity exists at the addresses 48, 52, 56, and 60. When correcting errors in the second column, the addresses are changed from 1 → 5 → 9 → 13 →.
→ 57 → 61. In this case, addresses 49, 5
3, 57 and 61 are the positions of the ECC parity.

Similarly, at the time of error correction in the third column, addresses are generated in the order of 2 → 6 → 10 → 14 →... → 58 → 62. In this case, the addresses 50, 54, 58 and 62 are set to EC.
It becomes the position of C parity, and at the time of error correction of the fourth column,
Addresses are generated in the order of 3 → 7 → 11 → 15 →... → 59 → 63. In this case, addresses 51, 55, 59 and 63 are the positions of the ECC parity.

By the way, in the format of the BCA code, the ECC parity is created corresponding to the maximum recording length of the BCA user data, that is, n = 12. Therefore, if n ≠ 12, the EDC parity
The syndrome calculation must be performed by inserting 0 data “00h” into the gap up to the C parity.

For this reason, even in the error correction processing of the BCA data, it is necessary to virtually insert 0 data “00h” into the gap to perform the syndrome calculation. In the above example (n = 3), when correcting the error in the first column, E
Between the address 44 where the DC parity is located and the address 48 where the first byte of the ECC parity is located, 0 data “00h” is set to (12
-3) × 4 = 36 bytes need to be inserted.

In the BCA data processing circuit 22, the BCA recording length detecting circuit 19h of the BCA detecting circuit 19
The gap is calculated based on the recording length detected in step (1), that is, the recording address of the data of the sync data RSBCA13 obtained by the above recording method, and dummy 0 data “00h” is inserted.

That is, if n = 6, the address of the first column is generated as 0 → 4 → 8 → 12 →... → 104 → 108. In this case, the addresses 96, 100, 104, 10
Since 8 is the ECC parity, 0 data “00h” is (12−6) × 4 = 24 between addresses 92 and 96.
Bytes will be inserted.

Next, the operation of the BCA data processing circuit 22 for detecting an EDC error will be described. That is, in the EDC calculation process, the process is adjusted to the recording length by using the recording address of the last data held at the time of data recording, similarly to the ECC process.

For example, if n = 3, the generated addresses are 0 to 63, and the addresses of the EDC parity are 44, 45, 46, and 47. For this reason, ED
The address generated during the C operation processing starts from 0 and is 4
The process ends at 7. If n = 6, the generated addresses are from 0 to 111, and the addresses of the EDC parity are 92, 93, 94, and 95 among them. For this reason,
The address generated during the EDC operation processing starts from 0 and ends at 95.

As described above, in the disk reproducing apparatus capable of reproducing BCA data, the BCA detection circuit 19 performs error correction by ECC parity and EDC check processing.
Supplies the detected recording length to the BCA data processing circuit 22. The BCA data processing circuit 22 selects ECC error correction processing or EDC calculation processing according to the input detected recording length, and changes the processing. I have to.

[0043]

However, in the above-described conventional disk reproducing apparatus, the recording length of the BCA data is detected, and the ECC and EDC processes are changed according to the detected recording length. Because it is, B
The process required for CA data reproduction is complicated, and the circuit configuration is accordingly complicated and large in size.

Therefore, the present invention has been made in view of the above circumstances, and does not require complicated processing for detecting the recording length of BCA data, and facilitates processing of BCA data with a simple configuration. It is an object of the present invention to provide a very good data reproducing device which enables the above.

[0045]

According to the data reproducing apparatus of the present invention, one data packet is composed of an unspecified number of frames, and one frame is a predetermined number of data to which a synchronization code and a frame number are added. It is intended for reproducing a data string composed.

Then, a recording medium having a recording capacity capable of recording one data packet including the maximum number of frames, and initial data for recording and initializing specific data in a recording area for one data packet of the recording medium. Generating an address to be given to a recording medium from a synchronization code and a frame number included in the reproduced data packet, and recording the data of the reproduced data packet on the recording medium based on the generated address. Means.

According to the above arrangement, when recording a data string having an unspecified number of frames on a recording medium, the specific data is recorded on the recording medium, the contents thereof are initialized, and the data is reproduced on the recording medium. An address to be given to the recording medium is generated from the synchronization code and the frame number included in the data packet, and the data length of the data packet reproduced based on the generated address is recorded in the recording medium, so that the data length is fixed. It is trying to become.

Therefore, regardless of the data length, it is possible to perform, for example, ECC calculation processing, EDC calculation processing, and the like on the data of the data packet recorded on the recording medium in a manner consistent with the processing at the maximum data length. Will be able to
Unlike the related art, it is possible to easily process a data string with a simple configuration without requiring complicated processing for detecting the recording length of BCA data.

[0049]

Embodiments of the present invention will be described below in detail with reference to the drawings. In FIG. 1, the same parts as those in FIG. 6 are denoted by the same reference numerals. That is, the line for transmitting the recording length from the BCA detection circuit 19 to the BCA data processing circuit 22 is deleted without the BCA detection circuit 19 detecting the recording length of the BCA data. The BCA detection circuit 19 is configured as shown in FIG. In FIG. 2, the same parts as those in FIG. 7 are denoted by the same reference numerals.

Here, the BCA data storage memory 21
Has a capacity capable of storing 208 bytes which is the longest, that is, the number of data when n = 12. Then, in detecting the BCA data,
The control MPU 15 receives the BCA via the input terminal 19j.
A memory initialization command is issued to the memory initialization control circuit 19k of the detection circuit 19.

In response to the memory initialization command, the BCA detection circuit 19 sends the BCA data storage memory 21
As shown in FIG. 3, for example, "FFh" is written as non-zero data in addresses 0 to 15 and addresses 16 to 191 are written.
0 data "00h" is written to the address 192-2.
A memory initialization process of writing, for example, “FFh” as non-zero data in 07 is performed.

In this memory initialization process, the address decoder 19l decodes the address generated by the memory address generation circuit 19f, so that non-zero data "F" is stored in the addresses 0 to 15 and 192 to 207.
The control signal A (“H” active) is output to the OR circuit 19m so that “Fh” is generated from the output terminal 19c. At other addresses (including 16 to 191), 0 data “00h” is output from the output terminal. The control signal B (“L” active) is output to the AND circuit 19n as generated from the signal 19c.

When the memory initialization process is completed, the BCA detection circuit 19 starts the operation of detecting BCA data. That is, the control MPU 15 causes the servo circuit 14 to perform CAV servo so as to keep the optical disc 11 at an optimum rotation speed for reproducing the BCA data, and to move the optical pickup 13 to the recording area of the BCA data. Generate a command.

Here, when the optical pickup 13 reaches the BCA data recording area from the data non-recording area of the optical disk 11, a channel bit starting from the sync data SBBCA is detected. Then, when the sync data SBBCA and the BCA-Preamble data are reproduced, the PLL circuit 20 is locked, and a normal channel bit clock can be obtained.

At this time, in the BCA detection circuit 19,
First, the sync pattern of the sync data RSBCA1 is detected, and an address 0 is generated in the BCA data storage memory 21. After that, the BCA detection circuit 19 performs data demodulation processing to make one byte every 16 channel bits detected, and increments the address each time.

In this way, the 4-byte data is stored in B
At the time when the data is recorded in the CA data storage memory 21, next, the sync data RSBCA1 should be detected again. However, even if the sync data RSBCA1 cannot be detected, the BCA detecting circuit 19 detects the sync data pseudo. The so-called synchronization protection is continuously performed without changing the data demodulation interval and the address increment.

Further, the BCA detection circuit 19 sets a sync detection window of about ± 2 channel bit widths with respect to the predicted position for detecting the sync data, and if the sync data can be detected within this window, the position correction is performed. To correct the subsequent data demodulation synchronization.

If the sync data detected at this time is a value other than RSBCA1, such as RSBCA2 or RSBCA10, the BCA detection circuit 19 regards it as a detection error and changes the address. I try not to do it.

The demodulated data of 16 bytes is BC
When the sync data is recorded in the A data storage memory 21, the next sync data should be RSBCA2 or RSBCA13, but if the detected frame number is other than 13, the address is not changed and the increment is continued.

When the sync pattern of the sync data RSBCA13 is detected within a window of ± 2 channel bit widths with respect to the predicted position, the memory address generation circuit 19f outputs the address 192 (address jump). This address 192 is the RSBCA1 at the maximum recording length.
Since it corresponds to the address where the first byte of No. 3 is to be written, the 0 data “00h” written at the time of memory initialization remains in the jumped addresses 16 to 191 after all. Then, the recording operation is completed at the time when 16 bytes of data to which the sync data RSBCA13 is added are recorded.

Next, the data recorded in the BCA data storage memory 21 as described above is subjected to processing such as error correction and EDC error detection by the BCA data processing circuit 22. First, address generation for error correction processing using ECC parity is performed as follows.

That is, the addresses generated for the error correction processing in the first column are 0 → 4 → 8 → 12 →... → 2
00 → 204, and the addresses 192, 196, 20
The ECC parity exists at the position of 0,204. The addresses generated for the error correction processing in the second column are 1 → 5 → 9 → 13 →... → 201 → 205
Thus, the ECC parity exists at the addresses 193, 197, 201, and 205.

Similarly, the address generated for the third column error correction processing is 2 → 6 → 10 → 14 →... → 2
02 → 206, and the addresses 194, 198, 20
ECC parity exists at the position of 2,206. The addresses generated for the error correction processing in the fourth column are 3 → 7 → 11 → 15 →... → 203 → 20
7 and the ECC parity exists at the addresses 195, 199, 203 and 207.

When the BCA data is recorded in the BCA data storage memory 21, the ECC parity following the sync data RSBCA13 is a fixed position of the memory 21, that is,
Recorded at addresses 192 to 207. Therefore, for example, even when n = 3, the recording position of the ECC parity is n
= 12.

Even when n = 3, the addresses 48 to
The address generation of the data non-recording position at the time of the BCA reproduction up to 191 is executed without skipping. That is, ECC
The address generation at the time of the error correction process using the parity is performed in the same manner as when the maximum data length is n = 12, regardless of the value of n.

As described above, the reason why the same processing as when n = 12 can be performed even though n = 12 is n ≠
At the time of 12, during the period from the EDC parity to the ECC parity, 0 data “00h” at the time of the above-mentioned memory initialization is used.
, The pseudo 0 data “00h” as in the prior art
This is because there is no need to insert

Therefore, the calculation result of the syndrome calculated at the time of the ECC calculation is exactly the same as the syndrome calculation generated at the time of creating the BCA data. Thereby, BC
Regardless of the A record data length, the ECC processing may be unified when the maximum data length is n = 12.

Next, the address generation for the EDC operation processing is the same as the processing at the time of the maximum recording length of n = 12. That is, the address generation is sequentially incremented from 0 and completed at 191. The EDC parity position is not recorded at the time of reproduction (that is, the address 188, 189, 190, 191 where 0 data “00h” remains).
Becomes

As described above, the reason why the same processing as when n = 12 can be performed even when n = 12 is not satisfied is that, for example, when n = 3, the EDC operation result is obtained from the address 0 based on the actual EDC parity. If the operation result is 0, that is, if the EDC check result is OK at that time, it is determined at the time when the address 47 which is the recording position of the fourth byte is generated. , The result of the EDC calculation for performing the exclusive OR operation should also be 0.
This is because the DC operation result is held as it is. Thus, regardless of the BCA recording data length, n
EDC processing may be unified when the maximum data length is = 12.

According to the above-described embodiment, BCA data having an unspecified data length is stored in the BCA data storage memory 21.
When recording in the BCA data storage memory 21, the contents of the BCA data storage memory 21 are initialized in advance, and the data length is fixed, so that the ECC calculation processing and the EDC calculation processing can be performed at the maximum data length regardless of the data length. BCA data can be easily processed with a simple configuration without the need for complicated processing such as detecting the recording length of BCA data as in the past. Becomes

The BCA detection circuit 19 may generate identification information indicating whether or not the reproduced BCA data has been recorded in the BCA data storage memory 21, and may record the identification information in the BCA data storage memory 21. . It should be noted that the present invention is not limited to the above-described embodiment, and can be variously modified and implemented without departing from the scope of the invention.

[0072]

As described in detail above, according to the present invention,
It is possible to provide an extremely good data reproducing apparatus which does not require complicated processing for detecting the recording length of BCA data and can easily process BCA data with a simple configuration.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a data reproducing apparatus according to the present invention.

FIG. 2 is a block diagram showing details of a main part in the embodiment.

FIG. 3 is an exemplary view for explaining a memory initialization process in the embodiment;

FIG. 4 is a plan view illustrating a recording area of BCA data on an optical disc;

FIG. 5 is a view for explaining a format of the BCA data.

FIG. 6 is a block diagram showing a conventional disc reproducing apparatus for reproducing the BCA data.

FIG. 7 is a block diagram showing details of a main part in the disc reproducing apparatus.

FIG. 8 is a view showing an example of generating an address in the disc reproducing apparatus.

[Explanation of symbols]

 Reference Signs List 11 optical disk, 12 disk motor, 13 optical pickup, 14 servo circuit, 15 control MPU, 16 amplifier circuit, 17 equalizer circuit, 18 data slice circuit, 19 BCA detection circuit, 20 PLL Circuit 21 BCA data storage memory 22 BCA data processing circuit

Claims (6)

[Claims] 1. A data reproducing apparatus for reproducing a data string in which one data packet is composed of an unspecified number of frames, and one frame is composed of a predetermined number of data each having a synchronization code and a frame number. A recording medium having a recording capacity capable of recording the one data packet including the maximum number of frames, and initialization means for recording and initializing specific data in a recording area for the one data packet of the recording medium; Generating an address to be given to the recording medium from the synchronization code and the frame number included in the reproduced data packet, and recording the data of the reproduced data packet on the recording medium based on the generated address. A data reproducing device comprising a recording unit. 2. The data reproducing apparatus according to claim 1, wherein the specific data is 0 data. 3. The specific data recorded in an area corresponding to a first frame and a last frame of the one data packet in the recording medium is non-zero data. Data playback device. 4. The data reproducing apparatus according to claim 1, wherein said data sequence is BCA data. 5. The data reproducing apparatus according to claim 1, wherein the recording means generates identification information indicating whether or not the data of the reproduced data packet has been recorded on the recording medium. 6. A data reproducing apparatus according to claim 5, further comprising means for processing a data packet recorded on said recording medium based on said identification information.