JP2006058413A - Method for forming mask - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology by which the alternation of a layout pattern from the production side is made unnecessary, the design time can be shortened and the yield can be improved in the method for forming a mask. <P>SOLUTION: A layout pattern showing a circuit pattern is prepared in the design side (S101). Then, an automatic layout pattern is altered in consideration of manufacturability (S102). Thereafter, the design verification is carried out (S103). The layout pattern is approved with sign off (S104), and the altered layout pattern is stored in a data base (S105). The steps mentioned hitherto are carried out in the design side. In the next place, in the manufacturing side, the layout pattern stored in the data base is subjected to OPC treatment (S106), and the manufacturability verification is carried out (S107). Further, a mask is formed based on the pattern subjected to OPC correction (S110), and a wafer process is carried out by using the formed mask (S111). <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a mask manufacturing technique, and more particularly to a technique effective when applied to a process of changing a layout pattern.

  Japanese Patent Application Laid-Open Publication No. 2004-004941 (Patent Document 1) mainly describes OPC (Optical Proximity) at the time of generation change of LSI (Large Scale Integration) (70% reduction of design rule or discontinuous dimensional change). A technique is disclosed in which even if a correction (optical proximity effect correction) process is performed, a manufacturing margin is insufficient, and a layout pattern must be improved. In this technique, (1) layout pattern design step, (2) layout pattern initial placement step, (3) proximity effect correction step, (4) proximity effect correction validity determination step, and (5) proximity effect correction become effective. And (6) a step of rearranging the initial layout pattern based on the changed design rule, (7) a proximity effect recorrection step, and (8) a mask manufacturing step. Yes.

  In Japanese Unexamined Patent Publication No. 2003-142854 (Patent Document 2), when a manufacturing margin cannot be ensured, a plurality of design rules are provided in one mask layer, and a layout pattern is arranged according to the plurality of design rules. A technique for securing a manufacturing margin is disclosed.

  Japanese Unexamined Patent Application Publication No. 2002-131882 (Patent Document 3) discloses a technique for ensuring a manufacturing margin without providing new restrictions on design rules. In this technology, a method of directly extracting a manufacturing margin shortage portion from design layout data is taken.

  Japanese Patent Application Laid-Open No. 2003-162041 (Patent Document 4) discloses a technique for automatically creating an improved layout pattern without providing a new restriction on the design rule. In this technology, an insufficient manufacturing margin pattern (OPC nonconforming pattern) and countermeasures are stored in a library storage device, and an improved layout pattern of an underproduction pattern is created by pattern matching for a new layout pattern. is there.

Japanese Unexamined Patent Publication No. 2001-350250 (Patent Document 5) describes not only the faithfulness of the pattern dimensions between the design layout pattern and the prediction (simulation) result when the pattern after the OPC process is transferred onto the wafer. In addition, an OPC processing method in consideration of a manufacturing margin is disclosed.
JP 2004-004941 A JP 2003-142484 A JP 2002-131882 A JP 2003-162041 A JP 2001-350250 A

  Currently, in the mask formation process, the flow after the design of the layout pattern is as shown in FIG. As shown in FIG. 29, after designing a layout pattern which is a circuit pattern (S1001), design verification of this layout pattern is performed (S1002). After sign-off (S1003), the layout pattern is stored in the database (S1004). The work so far is performed on the design side.

  Subsequently, the manufacturing side extracts the layout pattern stored in the database and performs optical proximity effect correction (OPC) (S1005). Then, manufacturing verification of the pattern subjected to the optical proximity effect correction is performed (S1006). If the result of the manufacturing verification is satisfactory (S1007), a mask is formed based on the pattern subjected to the optical proximity effect correction (S1008). . Thereafter, the formed mask is used in a wafer process (S1009).

  In manufacturing verification, (1) process margin verification, (2) CD verification, (3) mask verification, (4) tool verification, and the like are performed. In the process margin verification, it is verified whether the process margin (yield) is secured, and in the CD verification, it is verified whether the pattern is finished as designed. In mask verification, it is verified whether a mask can be manufactured, and in tool verification, it is verified whether there is a defect in the CAD tool.

  If an error occurs in this manufacturing verification, a return occurs as can be seen from FIG. The first return is a change in the OPC specification, which can be dealt with by a change in the OPC specification. If it is not possible to cope with the change in the OPC specification, a second return occurs. This second return is handled by changing the layout pattern. If the layout pattern cannot be changed, a third return occurs. The third return is a change in the design rule (DR), and the design is redone. As can be seen from FIG. 29, it can be seen that the loss in the design period increases as the first, second, and third returns.

  In the manufacturing verification (1), (2), (3), and (4), the method for dealing with errors in each item of the manufacturing verification is that the mask verification in (3) is almost always due to a change in the OPC specification. Yes. Regarding tool verification in (4), the reliability of tools has been improved in recent years, and almost no problems occur. Even if a problem occurs, it can be handled by combining commands that do not cause a problem. it can. The process margin verification (1) and the CD verification (2) often cannot be handled by changing the OPC specification, and are handled by changing the layout.

  The resolution performance has an evaluation quantity called the Rayleigh equation, and the resolution line width (RP) is expressed as the following equation.

RP = k1 × λ / NA
Here, k1 is a proportionality constant, λ is an exposure wavelength, and NA is a numerical aperture.

  In recent years, in order to meet the demand for miniaturization of layout patterns, efforts have been made to reduce the k1 factor by super-resolution technology or the like. When the k1 factor is reduced, the resolution performance is improved, but there are also disadvantages such as a two-dimensional distortion of the pattern being increased and a process margin being reduced. Therefore, as the pattern becomes finer, layout changes due to errors in the second return, that is, the process margin verification of the manufacturing verification (1) and the CD verification of the manufacturing verification (2) are greatly increased. In addition, when the two-dimensional distortion of the pattern increases, it becomes difficult to create a complete design rule.

  Thus, with the miniaturization of the layout pattern, many second returns shown in FIG. 29 occurred, resulting in a great loss of design work period. Further, the layout pattern changing method cannot be determined by the designer himself, and there is a problem that an instruction from an engineer on the manufacturing side is necessary for the changing method. In other words, since the manufacturing verification is performed on the manufacturing side, the change in the layout pattern necessary for the manufacturing verification is notified to the designer on the design side only by an instruction from the engineer on the manufacturing side. For this reason, there is a problem that it is impossible for the designer on the design side to determine how to change the layout pattern.

  An object of the present invention disclosed in the present application is to provide a technique capable of eliminating a change in a layout pattern from the manufacturing side, shortening a design period, and improving a yield in a mask forming method. .

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A mask forming method comprising the following steps: (a) a step of creating a layout pattern showing a circuit pattern; (b) a search is made for a dangerous location leading to a defect in the layout pattern, and the dangerous location exists. A step of automatically changing the layout pattern to form a changed layout pattern, (c) a step of verifying design based on the changed layout pattern, and (d) a step of storing the changed layout pattern in a data storage unit. e) a step of forming an optical proximity effect correction pattern by correcting the optical layout effect stored in the data storage unit, and (f) a step of performing manufacturing verification based on the optical proximity effect correction pattern, (g) Forming a mask based on the optical proximity correction pattern when the manufacturing verification result is satisfactory;

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  Since the layout pattern can be automatically changed in consideration of manufacturability at the design stage, it is possible to eliminate the change of the layout pattern from the manufacturing side in the mask formation method, to shorten the design period and to improve the yield. Can do.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say.

  Similarly, in the following embodiments, when referring to the shape, positional relationship, etc., of components, etc., unless otherwise specified, and in principle, it is considered that this is not clearly the case, it is substantially the same. Including those that are approximate or similar to the shape. The same applies to the above numerical values and ranges.

  In all the drawings for explaining the embodiments, the same members are denoted by the same reference symbols in principle, and the repeated explanation thereof is omitted.

  Hereinafter, embodiments will be described in detail with reference to the drawings.

(Embodiment 1)
Before describing the mask formation method in the first embodiment, the background thereof will be specifically described with reference to an example.

  FIG. 1 shows an example of a wiring layout pattern. The layout pattern shown in FIG. 1 extends in the first direction (X direction), changes direction 90 degrees in the middle and extends in the second direction (Y direction), and extends in the first direction. Wiring patterns 2 to 9 having edges formed so as not to be connected to the wiring pattern 1 are provided. This layout pattern is formed by the layout pattern design of FIG. 29 (S1001). The second direction described above is a direction perpendicular to the first direction, and broadly, a direction intersecting the first direction.

  Next, in the OPC (S1005) of FIG. 29, OPC is performed on the designed layout pattern. FIG. 2 shows a result of executing model-based OPC (Optical Proximity Correction) on this wiring layout pattern. That is, the OPC patterns 1a to 9a shown in FIG. 2 are formed by performing OPC processing on the wiring patterns 1 to 9 shown in FIG. Model-based OPC is obtained by performing optical proximity effect correction on a layout pattern using a simulation model. Here, in an exposure process using an electron beam or light, when an IC pattern is drawn or transferred onto a wafer, a proximity effect occurs in which a certain pattern changes in size due to the influence of an adjacent pattern. Therefore, in the mask formation process, correction is performed for the purpose of suppressing the proximity effect and reproducing the designed layout pattern as faithfully as possible, and this correction is called optical proximity effect correction.

  Next, FIG. 3 shows a result of executing a finished prediction simulation (process simulation) on the result after the model-based OPC. FIG. 3 shows a case where there is no process variation. As can be seen from FIG. 3, it is understood that a pattern close to the designed shape can be obtained by OPC.

  Next, FIG. 4 shows a case where process variation is taken into consideration. That is, FIG. 4 shows a case where the process margin is taken into consideration. The process margin verification checks the contrast of light intensity in order to verify the resolution of the resist, and also changes the process intensity, for example, the fluctuation amount of the light intensity and the dimensional fluctuation when the exposure amount and focus change. It is done in various ways, such as checking the amount. This process margin verification is performed by the manufacturing verification of FIG. 29 (S1006).

  FIG. 4 shows the result of executing contrast verification of light intensity as an example of process margin verification. From FIG. 4, it can be seen that, for example, dangerous places 20 to 23 having a risk of the wiring pattern bridging (wiring short circuit) are generated. In order to avoid the danger spots 20 to 23, first, consider the change of the OPC specification, which is the first return shown in FIG. In order to avoid the bridge, when the correction amount in the direction 10 (X direction) in FIG. 2 is reduced and the correction amount in the direction 11 (Y direction) is increased, a bridge is generated in the direction 11. Further, when the amount of scraping at the portion having the width 12 is increased, the portion having the width 12 is pinched (disconnected). In such a case, the OPC specification cannot be changed, and the layout is the second return shown in FIG. Specifically, the edges of the wiring patterns 3, 4, 7, and 8 in FIG. However, since such a simulation is performed on the manufacturing side, the designer who performs the design himself does not know where and how much to change. That is, it is necessary for an engineer on the manufacturing side to instruct a change location and a change amount.

  In this way, the layout pattern changes after the design is completed, resulting in a significant loss of design work period, and the layout pattern changing method cannot be determined by the designer himself. Instructions from engineers are required.

  Therefore, a method for forming a mask in the first embodiment is proposed. FIG. 5 is a flowchart showing a mask forming method according to the first embodiment. In FIG. 5, first, a layout pattern indicating a circuit pattern is created on the design side (S101). Subsequently, the automatic layout pattern in consideration of manufacturability is changed to form a changed layout pattern (S102). This automatic layout pattern change is a feature of one invention disclosed in the present application. That is, after a layout pattern is created on the design side, a portion (dangerous part) that may be changed in the layout pattern is predicted in advance, and the layout pattern of the predicted portion is automatically changed. As described above, the layout pattern change required in advance on the design side immediately after the design of the layout pattern on the design side can reduce the loss in the design work period. That is, by changing the layout pattern in advance on the design side, it is possible to eliminate the layout pattern change that occurs in the manufacturing verification on the manufacturing side, thereby eliminating the second return (see FIG. 29) due to the layout pattern change. . Therefore, the loss of the design work period accompanying the 2nd return can be reduced. Further, since the layout pattern can be changed “automatically”, there is an effect that the designer does not need to manually change the layout pattern in accordance with an instruction from the engineer on the manufacturing side.

  After changing the automatic layout pattern (S102), design verification is performed (S103). In design verification, design rules are checked, connection verification and timing verification are performed as necessary, and then a layout pattern is approved by sign-off (S104) and stored in a database (data storage unit) (S105). This is the end of the design.

  Next, the manufacturing side performs an OPC process on the layout pattern stored in the database (S106), and then performs manufacturing verification (S107). Since the layout pattern has already been changed at the design stage, a change that causes a change in the layout pattern does not occur in the manufacturing verification, and even if the manufacturing verification does not result in OK (S108), the specification change by OPC can be supported. (S109). When the manufacturing verification finally results in OK, a mask is formed based on the OPC corrected pattern (S110), and a wafer process is performed using the formed mask (S111).

  In this way, the layout pattern can be automatically changed while considering manufacturability on the design side, so in the mask formation method, the layout pattern change from the manufacturing side is eliminated, the design period is shortened and the yield is improved. Can be achieved.

  Specifically, a means for realizing the automatic layout pattern change on the design side will be described. FIG. 6 is a block diagram showing a configuration for automatically changing the layout pattern. In FIG. 6, 30 is a layout pattern holding means for holding a designed layout pattern (layout data), 31 is a dangerous part extraction pattern generating means for generating a pattern for extracting a dangerous part, and 32 is a process. The dangerous point extraction means 33 for extracting the upper dangerous place, the process information holding means 33 for holding information necessary for the process simulation, the optical conditions, the simulation model, etc., and the pattern of the dangerous place 34 do not become a dangerous place. A layout pattern change amount calculation means for avoiding danger for calculating a change amount of the layout pattern to be performed, 35 is a design rule holding means for holding the design rule, and 36 is a layout pattern for changing the layout pattern by the calculated change amount. The changing means 37 is a layout pas It is changed layout pattern holding means for holding the over down.

  Next, the operation based on the above configuration will be described. FIG. 7 is a flowchart showing a method for automatically changing the layout pattern. First, the dangerous part extraction pattern generation unit 31 generates a dangerous part extraction pattern for extracting a dangerous part that causes a problem in the process (S201). For generation of the dangerous part extraction pattern, rule-based OPC, model-based OPC, uniform sizing, or a combination thereof may be used. Here, the rule-based OPC is a method for correcting based on, for example, a rule determined for a pattern interval, and the model-based OPC is a method for correcting based on a simulation model.

  Subsequently, a process simulation is performed by the dangerous point extraction means 32 (S202). In this process simulation, for example, a simulation model for extracting a dangerous part is used. Based on the result of the process simulation, it is checked whether there is a dangerous place in the process (S203). If there is no dangerous part, the process ends. If there is a dangerous part, the layout pattern change amount calculation means 34 calculates the change amount of the design layout pattern that avoids the dangerous part (S204). Next, the layout pattern changing unit 36 changes the design layout pattern by the calculated change amount (S205). Next, a dangerous part extraction pattern is generated based on the changed design layout pattern, and the above process is repeatedly executed until there is no dangerous part, and finally, a changed layout pattern is formed. If there is a dangerous part that cannot be changed, the process is repeated infinitely, so the number of repetitions is set and the process ends.

  A more specific example of the automatic change of the layout pattern shown in FIG. 7 will be described. As the designed layout pattern, the layout pattern shown in FIG. 1 is used, and the model-based OPC is used for generating the dangerous part extraction pattern. In addition, for the extraction of the dangerous place, a process simulation based on the dangerous place extraction pattern (model base OPC) is performed, and the light intensity distribution (parameter) calculated by this process simulation is used for the extraction of the dangerous place. That is, contrast verification is used.

  When model-based OPC and contrast verification are executed, dangerous spots 20 to 23 are extracted as shown in FIG. Next, the amount of layout pattern change when contrast verification is used is calculated. An example of this calculation method is shown in FIG. That is, FIG. 8 shows an example of calculating the amount of change of the layout pattern shown in FIG.

  In FIG. 8, first, the difference between the set intensity value and the intensity of the measurement point is calculated (S301). The difference between the set intensity value and the intensity of the measurement point is as shown in FIG. In FIG. 9, the vertical axis indicates the light intensity, and the horizontal axis indicates the position. The measurement points shown on the horizontal axis correspond to the positions shown in FIG. That is, the measurement point is in an area where the pattern between the OPC pattern 1a and the OPC pattern 3a, which is a dangerous part extraction pattern, is not formed, but there is a risk that a bridge may occur as shown in FIG. In position 20. As shown in FIG. 9, since this measurement point is in a region where an OPC pattern that is a dangerous point extraction pattern is not formed, the light intensity at the time of exposure needs to be equal to or less than a set intensity (set value I). However, as shown in FIG. 9, in the simulation, the light intensity is higher than the set value, and this is a dangerous place to bridge. In step S301, a difference (ΔI) between a preset strength value I to be satisfied and a simulation strength at the measurement point is calculated.

  Next, the edge of the dangerous place in the dangerous place extraction pattern is changed to obtain the light intensity at the measurement point (S302). That is, as shown in FIG. 10, for example, the light intensity at the measurement point when the edge of the OPC pattern 3a that is a dangerous place in the dangerous place extraction pattern is changed by Δx is obtained. Specifically, the light intensity (Iout) at the measurement point when the edge of the OPC pattern 3a is moved to the outside of the pattern by Δx / 2 and the measurement point at the time of moving the edge of the OPC pattern 3a by Δx / 2 to the inside. The light intensity (Iin) is obtained.

  Subsequently, the fluctuation amount (slope) (S) of the light intensity per unit movement amount is obtained. The fluctuation amount (S) of the light intensity per unit movement amount is given by the following equation.

S = (Iout−Iin) / Δx
Then, by dividing the difference obtained in S301 by the fluctuation amount (S) of the light intensity per unit movement obtained in S303, an edge where the light intensity value at the measurement point is equal to or smaller than the set value (edge of the OPC pattern 3a) ) Is obtained (S304). This movement amount (Δw) is shown in FIG. Here, the amount of movement (Δw) shown below is the amount of movement of the edge of the OPC pattern 3a that can ensure contrast.

Δw = ΔI / S
If the edge of the OPC pattern 3a is moved by this movement amount (Δw), the same movement process as described above is executed for the OPC pattern 1a shown in FIG. become. Therefore, the layout pattern change amount (Δp) is obtained by multiplying the edge movement amount of the OPC pattern 3a by an appropriate weight (d) (S305).

Δp = d × Δw (d ≦ 1.0)
Next, it is checked whether the design rule is violated when the layout pattern is changed by Δp (S306). For example, when the wiring pattern 1 is drawn with the minimum line width and Δp is negative, that is, when correction for further narrowing the wiring pattern 1 is made, the design rule is violated. In this case, while Δp of the wiring pattern 1 is set to zero, there is no problem even if the edge of the wiring pattern 3 is moved by Δp. Therefore, the change amount is moved by Δp (S307).

  Subsequently, the designed layout pattern is changed by the change amount calculated as described above. Thereafter, as shown in the flow chart of FIG. 7, the accuracy of the change amount of the layout pattern is increased by repeated calculation, and the final change amount is obtained.

  FIG. 12 shows a layout pattern (changed layout pattern) automatically changed in this way. As shown in FIG. 12, it can be seen that the interval between the wiring patterns at the dangerous locations is widened. That is, as shown in FIG. 4, it can be seen that the layout pattern is changed so that the distance between the edge of the wiring patterns 3, 4, 7, and 8 and the wiring pattern 1 at risk of bridging is increased.

  Model-based OPC is performed on the changed layout pattern, and the light intensity at a location (measurement point) that has been a dangerous location is shown in FIG. It can be seen that the light intensity is below the threshold value (set value I) at the measurement point in the hazardous location, and the contrast is secured.

  In this way, there is no change in the layout pattern after the completion of the design, so there is no loss in the design work period. In addition, since the layout pattern is automatically changed, the designer does not need to receive an instruction of the layout change location and change amount from the engineer on the manufacturing side.

  Here, Japanese Patent Application Laid-Open No. 2004-004941 describes that the design rule is changed when the optical proximity effect correction is not effective. In general, a design rule is a description of a layout pattern arrangement rule with a simple description of several pages of a sheet for one mask layer. If the method for changing a huge amount of manufacturing margin shortage in a layout pattern is to be expressed succinctly in the arrangement rule described above, a huge amount of manufacturing margin shortage needs to be accumulated, and the efficiency of the countermeasures Abstraction is necessary. In addition, there is a risk that the arrangement rule becomes too strict for the design side, resulting in an adverse effect such as an increase in the chip area. Furthermore, there is no automatic change method for changing the layout pattern of the manufacturing margin shortage portion, and it is considered that the design rule must be extracted while changing the layout pattern manually.

  On the other hand, one invention disclosed in the present application can automatically change the layout pattern for each pattern having a manufacturing margin shortage, without necessarily changing the design rule, in recognition of these problems. it can. As a result, the layout pattern can be changed with a manufacturing margin secured in a short time and without causing an increase in the final chip area.

  In addition, in one invention disclosed in the present application, in order to increase the manufacturing margin verification accuracy, the manufacturing margin verification and the dangerous part extraction are performed on the pattern after performing the OPC process on the layout pattern. Therefore, it is possible to improve efficiency by avoiding the change of the layout pattern.

  In addition, one invention disclosed in the present application does not require library storage as disclosed in Japanese Patent Application Laid-Open No. 2003-162041, and changes the layout pattern based on an arithmetic method incorporating a physical phenomenon. To do.

  In Japanese Patent Laid-Open No. 2001-350250, the main purpose is to incorporate a manufacturing margin into the OPC processing method itself and improve the layout pattern after the OPC processing, and consider changing the layout pattern on the design side. Not. In addition, although it is considered to perform device / circuit simulation on the design side using the finished prediction pattern (pattern of the simulation result) as an input, in general, the finished side prediction pattern with a significantly different data format is used as the design side simulator. Entering in is not realistic.

  In contrast, one invention disclosed in the present application can automatically generate a modified layout pattern that can secure a manufacturing margin and present it to the designer, and input this modified layout pattern to the design-side simulator. It is very easy to check.

(Embodiment 2)
According to the first embodiment, a process margin can be secured in a layer whose layout pattern has been changed, but the process margin may be lost with other layers. In the second embodiment, an example will be described in which a layout pattern can be automatically changed while taking into account process margins with other layers. As another layer, a plug pattern will be described as an example.

  FIG. 14 shows an example of a layout pattern used in the second embodiment. In FIG. 14, the layout pattern according to the second embodiment extends in the X direction (first direction) intersecting the wiring pattern (second pattern) 40 extending in the Y direction (second direction) and the Y direction. In addition, wiring patterns 41 to 43 (first pattern) having edges formed so as not to contact the wiring pattern 40 are provided. Then, plugs 44 to 46 are formed below the edge portions of the wiring patterns 41 to 43, respectively. That is, the wiring patterns 41 to 43 are connected to the plugs 44 to 46 at the edge portions, respectively.

  FIG. 15 shows the result of performing a process simulation after generating a dangerous part extraction pattern based on the layout pattern shown in FIG. In the second embodiment, a portion having a large dimensional variation due to exposure amount variation (parameter) is extracted as a dangerous location by process simulation. The contour line in the middle of FIG. 15 shows the finished prediction pattern (simulation) at the center exposure amount, and the adjacent contour line shows the finished prediction pattern when the exposure amount fluctuates. As can be seen from FIG. 15, edge portions 47 and 48 having large dimensional variations are extracted as dangerous portions to be bridged. In FIG. 15, the edge locations 49, 49a, 49b facing the edge location 48 are referred to as peripheral edge locations. Here, the edge dividing method of the peripheral edge locations 49, 49a, 49b is the same as the widely used model base OPC, and other methods may be used.

  FIG. 16 shows a flowchart for calculating the change amount of the layout pattern in consideration of the process margin with other layers in consideration of the dimensional variation due to the exposure amount variation. Here, the wiring pattern of the layout pattern shown in FIG. 14 is called a first layer, and the plug is called a second layer.

  First, the deviation of the dimension (ΔCD) is calculated at the edge parts 47 and 48 which are the dangerous parts shown in FIG. 15 (S401 in FIG. 16), and the value obtained by multiplying the dimension deviation by the weight (d) is the temporary change amount. (Δp1) is set (S402 in FIG. 16). Since the amount of change is in the opposite direction to the dimensional deviation, a minus is applied.

Δp1 = −d × ΔCD (d ≦ 1.0)
Then, the margin between the first layer changed by the temporary change amount (Δp1) and the second layer (plug) is checked (S403 in FIG. 16). FIG. 17 shows the result of the process simulation between the first layer and the second layer (plug) changed by the provisional change amount. As an example of checking the margin between the second layer, the area of overlap between the first layer and the second layer is checked. That is, as shown in FIG. 17, the overlapping area of the pattern 42a simulating the wiring pattern 42 and the pattern 45a simulating the plug 45 is checked. If the overlapping area is sufficient (S404 in FIG. 16), the process proceeds to S406 because there is a margin in relation to the second layer (plug).

  On the other hand, as can be seen from FIG. 17, when the first layer is moved by the temporary change amount (Δp1), there is no margin between the second layer (plug) (S404 in FIG. 16). As described above, when the area of the overlap between the first layer and the second layer (plug) cannot satisfy the allowable value, the layout change amount is adjusted so as to reach the position where it can be satisfied (Δp2) (S405 in FIG. 16). ). As a result, the amount of layout change is as follows.

Δp = Δp1 + Δp2
Thus, when the first layer is moved, the layout change amount is determined so that the overlapping area with the second layer (plug) connected to the first layer is within the allowable range. In the above description, the overlapping area between the pattern 42a simulating the wiring pattern 42 and the pattern 45a simulating the plug 45 is checked. However, the present invention is not limited to this. The overlapping area between the first layer and the second layer (plug) may be checked, or only one of them may be simulated. Finally, it is only necessary that the overlapping area of the moving first layer and the second layer (plug) connected thereto is within an allowable range.

  Next, it is checked whether the first layer changed by the temporary change amount (Δp) satisfies the design rule of the first layer. If necessary, it is also checked whether the design rule between the first layer and the second layer is satisfied (S406 in FIG. 16). After checking, if the design rule is not violated (S407 in FIG. 16), the process is terminated. On the other hand, if the design rule is violated (S407 in FIG. 16), a search is made for a peripheral edge that can satisfy the design rule (S408 in FIG. 16). When the wiring pattern 40 in FIG. 14 has the minimum line width, if only the edge portion 48 in FIG. 15 is moved by the temporary variation (Δp1), the minimum line width is divided, which violates the design rule. However, the peripheral line locations 49, 49a, and 49b facing the edge location 48 can move in the same manner to ensure the minimum line width. As described above, when the design rule violation can be avoided by moving the peripheral edge portion (S409 in FIG. 16), the change amount is also set in the peripheral edge portion (S410 in FIG. 16). If there is no peripheral edge (S409 in FIG. 16), a layout pattern change amount that does not violate the design rule is set (S411 in FIG. 16).

  The layout pattern is moved by the layout pattern change amount set in this way, and the process is repeated until there is no danger portion according to the flowchart shown in FIG.

  FIG. 18 shows the result of changing the layout pattern as described above (changed layout pattern). As can be seen, the edge of the wiring pattern 42 has no margin with the plug 45, so the amount of change is small, and it can be seen that the facing wiring pattern 40 is moved by a large amount of variation.

  According to the second embodiment, a margin between other layers can be taken into consideration, and the loss of the design work period due to the layout change after the completion of the design can be further reduced.

(Embodiment 3)
In the second embodiment, the layout pattern is changed in consideration of the process margin with other layers. However, the layout pattern may need to be changed for other layers as well.

  FIG. 19 shows a layout pattern according to the third embodiment. This layout pattern is a layout pattern obtained by adding a wiring pattern 50 and a plug 51 to the layout pattern of FIG. 14 described in the second embodiment. When a process simulation is performed in the same manner as in the second embodiment, there is a possibility that a bridge may be generated at the locations 52 and 53 in FIG.

  Here, in the second embodiment, the layout pattern is changed so that the wiring pattern 40 is kept away from the edge portion of the wiring pattern 42 as shown in FIG. However, in the third embodiment, the wiring pattern (first pattern) 50 exists on the opposite side of the wiring pattern (second pattern) 40 of the wiring pattern (first pattern) 42. Therefore, when the wiring pattern 40 is moved away from the wiring pattern 42, the wiring pattern 40 approaches the wiring pattern 50, and a bridge is generated. As described above, in the third embodiment, the wiring pattern 40 cannot be separated as in the second embodiment. Further, when the width of the wiring pattern 40 is the minimum line width, it cannot be cut off.

  In such a case, an example of changing the layout pattern is shown. FIG. 20 is a flowchart for changing the layout pattern. First, it is checked whether the second layer (first plug) can be changed (S501). If it can be changed (S502), the change amount is set in the second layer (first plug) (S503). At this time, assuming that the first layer (wiring pattern) connected to the second layer (first plug) can be changed, the second layer (first plug) is also moved by the same amount as the wiring pattern. This is shown in FIG. As shown in FIG. 21, in order to avoid a bridge between the wiring pattern 40 and the wiring pattern 42, the edge of the wiring pattern 42 is moved away from the wiring pattern 40 and the position of the plug (first plug) 45 is also moved away from the wiring pattern 40. Move to. Similarly, the edge of the wiring pattern 50 is moved away from the wiring pattern 40 and the position of the plug (first plug) 51 is moved in the same manner. In this way, the layout pattern can be changed so as to avoid dangerous places. That is, a modified layout pattern that avoids a dangerous place can be formed.

  On the other hand, it is examined whether the first layer can be changed to another layer (S504). When the first layer can be changed to another layer (S505), a changed layout pattern in which the first layer is changed to another layer is formed (S506). FIG. 22 shows an example in which the first layer is changed to another layer. As shown in FIG. 22, the layout pattern is changed so that the wiring pattern 40 is connected to an upper wiring pattern 55 via a plug (second plug) 54. That is, since the wiring pattern 40 is bypassed using the plug (second plug) 54 and the wiring pattern 55, bridging with the wiring patterns 42 and 50 is avoided. In FIG. 22, the layout pattern is changed to make a detour to the upper layer. However, the layout pattern is not limited to this, and the layout pattern may be changed to make a detour to the lower layer, for example.

  If the second layer (first plug) can be moved, but the first layer cannot be changed to another layer, the layout pattern shown in FIG. 21 is changed. On the other hand, if the first layer can be changed to another layer, but the second layer (first plug) cannot be moved, the layout pattern shown in FIG. 22 is changed. That is, as shown in FIG. 19, when the layout change amount in the same layer cannot be determined between the wiring pattern 42 (first pattern) and the wiring pattern 40 (second pattern) in the same layer, as shown in FIG. As described above, the layout change amount is determined so that a portion of the wiring pattern 40 that may be connected to the wiring pattern 42 is detoured to the upper layer or the lower layer via the plug 54.

  If both layout patterns cannot be changed (S507), an error is output (S508).

  When both layout patterns can be changed, there are two types of possible changes shown in FIGS. 21 and 22. Example 1 is an example in which the wiring patterns 42 and 50 of the first layer are retracted and the plugs (first plugs) 45 and 51 are moved together. Example 2 is an example in which the wiring pattern 40 of the first layer is changed to the wiring pattern 55 of the upper layer and connected by a plug (second plug) 54. As described above, when there are a plurality of modification examples, the designer may make a determination, or one of them may be automatically selected.

(Embodiment 4)
In the fourth embodiment, the designed layout pattern is changed. However, if there is no result of the process simulation and the result of the actual process, the layout pattern is changed too much. Therefore, in the fourth embodiment, a simulation model verification unit for extracting a dangerous part is provided, the difference from the actual process is fitted again, and a new model with a higher risk point extraction accuracy is created. It is something that can be done. In addition, it is possible to create a new design rule by comparing and analyzing the layout information in which the layout pattern could not be changed and the layout information in which the layout pattern was changed and the design rule.

  FIG. 23 is a block diagram showing a configuration provided in the fourth embodiment in addition to the configuration shown in FIG. Reference numeral 60 denotes a layout pattern that cannot be changed, a layout pattern that can be changed, and layout classification information (line edge, corner, edge, etc.) and layout peripheral status (pattern width, interval, pitch, density, interval between other layers) Layout information storage means 61 for storing layout information, etc., 61 is a layout information holding means for holding layout information, 62 is a layout information classification means for classifying necessary layout information, and 63 is a design for holding design rules. Rule holding means 64 is process information used in the process such as a process model used in process simulation, length measurement data of a scanning electron microscope (SEM), difference data between actual process and simulation, wavelength of exposure machine, etc. Process information holding means for holding 5 is a simulation model verification means for verifying whether the prediction result by the simulation model matches the result of the actual process, and a new model is generated, and 66 is for analyzing the current design rule and the pattern with the layout change. Design rule analyzing means for generating a new design rule, 67 is a new model holding means for holding a newly generated model, and 68 is a new design rule holding means for holding a newly generated design rule.

  Thus, in the fourth embodiment, since the simulation model verification means 65 is provided, the prediction result of the simulation model used for extraction of the dangerous part is based on the above layout information and the above process information. A new model can be generated by verifying that it matches the results of the process. Then, by using the newly generated model to extract dangerous spots, it is possible to accurately extract dangerous spots that are problematic in the actual process, and change the layout pattern according to the actual situation. can do. In addition, by providing the design rule analysis means 66, it is possible to analyze the current design rule and the pattern that has undergone the layout change and generate a new design rule, and therefore to create a design rule that reflects the changed layout pattern. Can do.

  As described above, according to the fourth embodiment, the accuracy of the simulation model can be increased, and a layout pattern with a high yield can be obtained.

(Embodiment 5)
FIG. 24 is a block diagram showing a configuration for realizing automatic layout pattern change in the fifth embodiment. In FIG. 24, the configuration of a portion different from the first embodiment will be described, and the description of the configuration of the same portion will be omitted.

  In FIG. 24, different configurations have only one dangerous spot extracting means 32 and one layout pattern change amount calculating means 34 in the first and second embodiments. It is the point which has the location extraction means 32A-32N and the some change amount calculation means 34A-34N. And as shown in FIG. 24, each of the dangerous part extraction means 32A-32N respond | corresponds to each of change amount calculation means 34A-34N.

  In the first embodiment, the dangerous part is extracted in consideration of the contrast (first parameter), and the layout pattern change amount for avoiding the extracted dangerous part is calculated. In the second embodiment, taking into account the exposure amount variation (second parameter), the dangerous part is extracted, and the layout pattern change amount for avoiding the extracted dangerous part is calculated. In this case, the number of parameters used when extracting the dangerous part is one, but in the fifth embodiment, a plurality of process margin verifications are combined. For example, the dangerous part extraction unit 32A extracts a dangerous part in consideration of contrast, the dangerous part extraction unit 32B extracts a dangerous part in consideration of exposure amount fluctuation, and the dangerous part extraction unit 32N takes defocus into consideration. To extract dangerous spots. Then, the change amount of the layout pattern is calculated by the change amount calculation means 34A to 34N corresponding to the respective dangerous spot extraction means 32A to 32N. For example, the first risk location is extracted by the risk location extraction means 32A, and the change amount of the layout pattern (first layout change amount) that avoids the first risk location is calculated by the change amount calculation means 34A. Further, the second dangerous place (which may be the same place as the first dangerous place) is extracted by the dangerous place extracting means 32B, and the layout pattern change amount (second layout change amount) that avoids the second dangerous place. Is calculated by the change amount calculation means 34B.

  Thereafter, the layout change amount optimizing unit 38 determines the optimized change amount based on the change amount of the layout pattern calculated by each of the change amount calculating units 34A to 34N.

  As described above, in the fifth embodiment, it is possible to determine an optimal layout pattern change amount by combining a plurality of process margin verifications.

(Embodiment 6)
In the first to fifth embodiments, after generating a dangerous part extraction pattern, a dangerous part is extracted by performing a process simulation based on the dangerous part extraction pattern. And although the pattern which can avoid a dangerous place was produced | generated and the layout pattern was changed based on this, in this Embodiment 6, after producing | generating the pattern which can extract a dangerous place and avoid a dangerous place, this Process simulation is performed on the pattern to generate a finished pattern. An example of changing the layout pattern based on the finished pattern will be described.

  FIG. 25 is a flowchart showing a method for automatically changing the layout pattern according to the sixth embodiment. In FIG. 25, after first creating a dangerous part extraction pattern (S601), a process simulation is performed (S602) to extract a dangerous part. If there is a dangerous part (S603), a pattern that can avoid the dangerous part is generated based on the dangerous part extraction pattern (S604). The process up to this point is the same as in the first to fifth embodiments. Then, a process simulation is performed based on the avoidable pattern to generate a finished pattern (S605). Subsequently, the layout pattern is changed based on the finished pattern (S606). Thus, the layout pattern can be changed based on the finished pattern without changing the layout pattern based on the avoidable pattern.

  FIG. 26 shows a pattern in which the edge of the OPC pattern 71a is moved away from the OPC pattern 70a by x1 in order to extract the dangerous place from the dangerous place extraction pattern and avoid the extracted dangerous place. That is, FIG. 26 shows a pattern that can avoid a dangerous spot. The pattern that can avoid this dangerous spot is generated from the dangerous spot extraction pattern. In the first to fifth embodiments, x1 described above is used as the layout pattern change amount.

  Next, in the sixth embodiment, a process simulation is performed based on a pattern that can avoid this dangerous place, and a finished pattern 71b is generated. In the sixth embodiment, x2 which is the difference between the finished pattern 71b and the original (before change) layout pattern is used as the layout pattern change amount. FIG. 27 shows a layout pattern including a wiring pattern 70 and a wiring pattern 71, and shows a state in which the edge of the wiring pattern 71 is changed by x2 described above. Thus, the layout pattern change amount can also be determined based on the finished pattern.

(Embodiment 7)
In the mask forming method according to the seventh embodiment, the automatic layout pattern change in consideration of manufacturability is performed, and the result of the OPC process based on the changed layout pattern, that is, the last when the dangerous part disappears in FIG. The dangerous part extraction pattern is also output.

  FIG. 28 is a flowchart showing a mask forming method according to the seventh embodiment. In FIG. 28, first, a layout pattern indicating a circuit pattern is created on the design side (S701). Subsequently, the automatic layout pattern in consideration of manufacturability is changed to form a changed layout pattern, and an OPC process is performed based on the changed layout pattern (S702). After design verification is performed (S703), sign-off is performed (S704), and the layout pattern after the change and the pattern subjected to the OPC process are stored in the database (S705).

  Subsequently, on the manufacturing side, a mask is formed based on the pattern subjected to the OPC process (S706), and the formed mask is used in the wafer process (S707). As described above, in the seventh embodiment, the layout pattern is changed in advance on the design side, and a pattern subjected to the OPC process based on the changed layout pattern is also formed. Manufacturing verification can be omitted. As described above, according to the seventh embodiment, it is possible to shorten the work period for forming the mask.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  In the above-described embodiment, an example in which a layout pattern is automatically changed after designing a layout pattern has been described. However, one invention disclosed in the present application is not limited to this, for example, at the stage of cell design. Is also applicable.

  Moreover, in the said embodiment, although the wiring pattern arrange | positioned so that it mutually cross | intersects was demonstrated to the example, one invention disclosed by this application is not limited to this, For example, it is mutually parallel The present invention can also be applied to the wiring pattern arranged in the above. Furthermore, one invention disclosed in the present application can be applied to a pattern for forming a gate electrode, a source region, a drain region, and the like of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), for example.

  One invention disclosed in the present application can be widely used in the manufacturing industry for forming a mask.

It is the figure which showed an example of the layout pattern of this invention. It is the figure which showed the result of having performed model base OPC with respect to a layout pattern. It is the figure which showed the result of having performed the prediction simulation of a finish with respect to the result after model base OPC. It is the figure which showed the result of having performed contrast verification of light intensity as an example of process margin verification. 3 is a flowchart showing a mask forming method in the first embodiment. It is a block diagram which shows the structure for implement | achieving the change of a layout pattern automatically. It is the flowchart which showed the method of the layout pattern automatic change. It is the flowchart which showed an example which calculates the change amount of a layout pattern. It is the figure which showed the relationship between light intensity and a position. It is the figure which showed the wiring pattern in the vicinity of a measurement point. It is the figure which showed the movement amount of the edge from which the value of the light intensity in a measurement point becomes below a setting value. It is the figure which showed the layout pattern changed automatically. It is the figure which showed the relationship between the light intensity at the time of performing model base OPC with respect to the changed layout pattern, and a position. 6 is a diagram showing an example of a layout pattern used in the second embodiment. FIG. It is the figure which showed the result of having performed the process simulation, after producing | generating the pattern for dangerous location extraction based on a layout pattern. FIG. 10 is a flowchart for calculating a layout pattern change amount in consideration of process margins with other layers in consideration of dimensional variation due to exposure amount variation; FIG. It is the figure which showed the result of the process simulation between an edge location and a 2nd layer (plug). It is the figure which showed the layout pattern changed automatically. 10 shows a layout pattern in the third embodiment. It is a flowchart in the case of changing a layout pattern. It is a figure which shows the layout pattern which moved the 2nd layer (plug) by the same amount as a wiring pattern. It is a figure which shows the example which changed the 1st layer into the layer of the other layer. FIG. 10 is a diagram showing a configuration in a fourth embodiment. FIG. 10 is a diagram showing a configuration in a fifth embodiment. 18 is a flowchart showing a method for automatically changing a layout pattern in the sixth embodiment. It is the figure which showed the pattern which can avoid a dangerous location. It is the figure which showed the example which changes a layout pattern based on a finishing pattern. 18 is a flowchart showing a mask forming method in the seventh embodiment. It is the flowchart which showed the formation method of the mask which the present inventors examined.

Explanation of symbols

1-9 Wiring pattern 1a-9a OPC pattern 10 direction 11 direction 12 width 20-23 dangerous place 30 layout pattern holding means 31 dangerous place extraction pattern generating means 32 dangerous place extracting means 32A-32N dangerous place extracting means 33 process information holding Means 34 Layout pattern change amount calculation means 34A to 34N Change amount calculation means 35 Design rule holding means 36 Layout pattern change means 37 Changed layout pattern holding means 38 Layout change amount optimization means 40 to 42 Wiring pattern 42a pattern 43 Wiring pattern 44 to 45 plug 45a pattern 46 plug 47 edge part 48 edge part 49 peripheral edge part 49a peripheral edge part 49b peripheral edge part 50 wiring pattern 51 plug 52 part 53 part 54 plug 55 wiring pattern 60 layout information storage means 61 layout information holding means 62 layout information classification means 63 design rule holding means 64 process information holding means 65 simulation model verification means 66 design rule analysis means 67 new model holding means 68 new design rule holding Means 70 Wiring pattern 70a OPC pattern 71 Wiring pattern 71a OPC pattern 71b Finish pattern

Claims (15)

Method for forming a mask comprising the following steps:
(A) creating a layout pattern indicating a circuit pattern;
(B) searching for a dangerous location leading to a defect in the layout pattern, and if the dangerous location exists, automatically changing the layout pattern to form a modified layout pattern;
(C) a step of verifying design based on the changed layout pattern;
(D) storing the modified layout pattern in a data storage unit;
(E) a process of forming an optical proximity correction pattern by correcting the optical layout effect stored in the data storage unit and correcting the optical proximity effect;
(F) A step of performing manufacturing verification based on the optical proximity correction pattern,
(G) A step of forming a mask based on the optical proximity correction pattern when the result of the manufacturing verification is good. Method for forming a mask comprising the following steps:
(A) creating a layout pattern indicating a circuit pattern;
(B) A search is made as to whether or not there is a dangerous place leading to a defect in the layout pattern, and when the dangerous place exists, the layout pattern is automatically changed to form a changed layout pattern, and the changed layout pattern is lighted A step of forming an optical proximity correction pattern corrected for proximity,
(C) design verification based on the modified layout pattern and the optical proximity correction pattern;
(D) storing the changed layout pattern and the optical proximity correction pattern in a data storage unit;
(E) A step of forming a mask based on the optical proximity correction pattern. A method of forming a mask according to claim 1 or 2,
The step (b)
(B1) forming a dangerous part extraction pattern for extracting the dangerous part from the layout pattern;
(B2) extracting the dangerous location based on the dangerous location extraction pattern;
(B3) calculating a layout change amount for avoiding the dangerous part extracted in the step (b2);
(B4) A method of forming a mask, comprising: forming a changed layout pattern based on the layout change amount calculated in the step (b3). A method of forming a mask according to claim 1 or 2,
The step (b)
(B1) forming a dangerous part extraction pattern for extracting the dangerous part;
(B2) extracting the dangerous location based on the dangerous location extraction pattern;
(B3) calculating a layout change amount for avoiding the dangerous part extracted in the step (b2);
(B4) including a step of changing the layout pattern based on the layout change amount calculated in the step (b3),
A method of forming a mask that finally forms the modified layout pattern from the layout pattern by repeatedly executing the steps (b1) to (b4). A method of forming a mask according to claim 3 or claim 4, wherein
The method of forming a mask, wherein the dangerous part extraction pattern in the step (b1) is a pattern obtained by correcting the layout pattern with an optical proximity effect. A method of forming a mask according to claim 3 or claim 4, wherein
The step (b2) is a mask forming method in which a process simulation is performed based on the dangerous part extraction pattern, and the dangerous part is extracted based on a light intensity distribution calculated by the process simulation. A method of forming a mask according to claim 6,
The step (b3)
(B3-1) The difference between the light intensity threshold value to be satisfied at the measurement point and the light intensity calculated by the process simulation is calculated at the measurement point in the dangerous place extracted from the dangerous place extraction pattern. And a process of
(B3-2) a step of calculating a fluctuation amount of the light intensity at the measurement point when the edge of the dangerous part extraction pattern in the dangerous place is moved;
(B3-3) The case where the edge of the dangerous part extraction pattern is moved by the unit movement amount by dividing the amount of fluctuation of the light intensity at the measurement point by the movement amount of the edge of the dangerous part extraction pattern. Calculating the amount of variation in light intensity at the measurement point;
(B3-4) By dividing the difference calculated in the step (b3-1) by the fluctuation amount of the light intensity at the measurement point when the edge of the dangerous part extraction pattern is moved by the unit movement amount, Calculating the amount of movement of the edge of the pattern for extracting the dangerous part to be moved in order to put the light intensity at the measurement point within an allowable range;
(B3-5) a step of performing predetermined weighting on the movement amount calculated in the step (b3-4);
(B3-6) a step of checking whether or not the design rule is violated when the edge of the layout pattern is moved by the moving amount weighted in the step (b3-5);
(B3-7) If the design rule is not violated, the amount of movement weighted in the step (b3-5) is set as the layout change amount. On the other hand, if the design rule is violated, the step (b3-5) is performed. Calculating a movement amount in a range not violating the design rule from a weighted movement amount, and setting the movement amount in a range not violating the design rule as the layout change amount. A method of forming a mask according to claim 3 or claim 4, wherein
The step (b2) is a mask forming method in which a process simulation is performed based on the dangerous part extraction pattern, and the dangerous part is extracted based on a variation in exposure amount calculated by the process simulation. A method of forming a mask according to claim 3 or claim 4, wherein
The step (b3) is a mask for determining the layout change amount so that an overlapping area with a plug connected to the first pattern is within an allowable range when the first pattern in the layout pattern is moved. Forming method. A method of forming a mask according to claim 3 or claim 4, wherein
In the step (b3), the mask forming method for determining the layout change amount so that the plug connected to the first pattern in the layout pattern is also moved in the same direction as the direction in which the first pattern is moved. . A method of forming a mask according to claim 3 or claim 4, wherein
In the step (b3), when the layout change amount in the same layer cannot be determined between the first pattern and the second pattern in the same layer in the layout pattern, the first pattern in the second pattern A method of forming a mask, wherein the layout change amount is determined so that a portion that may be connected to the first and second layers is detoured to an upper layer or a lower layer through a plug. The method of forming a mask according to claim 3 or 4, further comprising:
A step of verifying whether the simulation model for extracting the dangerous spot used in the step (b2) reflects an actual process and generating a new simulation model for extracting the dangerous spot so as to reflect the actual process is provided. Mask forming method. The method of forming a mask according to claim 3 or 4, further comprising:
A mask forming method comprising a step of forming a new design rule by analyzing the modified layout pattern. A method of forming a mask according to claim 3 or claim 4, wherein
In the step (b2), a process simulation is performed based on the dangerous part extraction pattern, a first dangerous part is extracted based on at least a first parameter calculated by the process simulation, and the process simulation Extracting a second dangerous point based on the calculated second parameter,
The step (b3) includes a step of calculating a first layout change amount for avoiding the first dangerous place extracted based on the first parameter, and a second dangerous place extracted based on the second parameter. Calculating a second layout change amount for avoiding
Further, the mask forming method includes a step of optimizing the change amount based on the first layout change amount and the second layout change amount. A method of forming a mask according to claim 1 or 2,
The step (b)
(B1) forming a dangerous part extraction pattern for extracting the dangerous part from the layout pattern;
(B2) extracting the dangerous location based on the dangerous location extraction pattern;
(B3) generating a pattern capable of avoiding the dangerous spot extracted in the step (b2) based on the dangerous spot extraction pattern;
(B4) performing a process simulation based on the pattern capable of avoiding the dangerous place generated in the step (b3), and forming a finished pattern;
(B5) A method for forming a mask, comprising: forming the modified layout pattern based on the finished pattern.