JP2015121809A - Mask pattern correction method, mask pattern correction apparatus, and circuit design apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a mask pattern correction method for accurately transferring a circuit pattern based on circuit design data.SOLUTION: The mask pattern correction method causes a computer to dispose a first evaluation point on each of the opposing pattern edges in a mask pattern, compare a first light intensity of each of the first evaluation points with a first threshold value to determine a first correction quantity with respect to the optical proximity effect at the respective positions of the opposing pattern edges, correct the respective positions of the opposing pattern edges on the basis of the first correction quantity, dispose a second evaluation point between a pattern containing one of the opposing pattern edges and a pattern containing the other of the opposing pattern edges, compare a second light intensity of the second evaluation point with a second threshold value smaller than the first threshold value to determine a second correction quantity with respect to the optical proximity effect for each of the opposing pattern edges, and correct the respective positions of the opposing pattern edges on the basis of the second correction quantity.

Description

  The present invention relates to a mask pattern correction method, a mask pattern correction device, a circuit design device, and a program for correcting a mask pattern.

  2. Description of the Related Art Conventionally, with the miniaturization of a semiconductor device, correction for the optical proximity effect of a circuit mask pattern used for photolithography has been performed.

  In photolithography, a target circuit pattern based on circuit design data is transferred to a resist layer on a wafer. On the other hand, with the miniaturization of the semiconductor device, the pattern width transferred to the resist layer is equal to or less than the exposure wavelength, and due to the interference of light that exposes adjacent patterns, In some cases, the target circuit pattern is displaced.

  Such a deviation of the transfer pattern from the target circuit pattern due to optical factors is called an optical proximity effect. In view of this, a transfer pattern shift due to the optical proximity effect is corrected in advance with respect to the circuit mask pattern of the photomask. For example, the position of the edge of the pattern in the circuit mask pattern is moved to correct the optical proximity effect.

JP 2003-257842 A JP-A-6-349718

  The optical proximity effect also occurs between the edges of opposing patterns in the circuit mask pattern. Due to the effect of the optical proximity effect, the transfer patterns of the resist layer may come into contact with each other or a disconnection may occur in the transfer pattern. A location where pattern contact or disconnection occurs is also referred to as a dangerous location.

  FIG. 1A is a diagram illustrating an example of a dangerous portion of a circuit mask pattern, and FIG. 1B is a diagram illustrating the light intensity of the dangerous portion.

  FIG. 1A shows a circuit mask pattern 120 having a pattern 121 and a pattern 122. An evaluation point A for evaluating the light intensity is arranged at each of the edges of the opposing pattern 121 and pattern 122. The light intensity at the position of the resist layer corresponding to the evaluation point A when the circuit mask pattern is projected onto the resist layer is calculated, and based on this light intensity, light is emitted to the edges of the opposing pattern 121 and pattern 122. Corrections for proximity effects have been made.

  In FIG. 1A, an evaluation point B for evaluating the light intensity is arranged at a position between two evaluation points A on the edges of the opposing patterns 121 and 122. The evaluation point B is arranged between the pattern 121 and the pattern 122. That is, the evaluation point B is located between the end edge of the opposing pattern 121 and the end edge of the pattern 122.

  FIG. 1B shows the light intensity in the resist layer when the circuit mask pattern is projected onto the resist layer along the line connecting the two evaluation points A and B. Here, the resist layer is resolved at a portion of light intensity greater than the threshold value S101. Since the light intensity at the position of the resist layer corresponding to the two evaluation points A is larger than the threshold value S101, the resist layer is resolved.

  In the example shown in FIG. 1B, since the light intensity at the position of the resist layer corresponding to the evaluation point B is larger than the threshold value S101, the opposing pattern 121 and pattern 122 have two evaluation points A and evaluation points. It is resolved along the line connecting B and comes into contact. A place like the evaluation point B is called a dangerous place (hot spot).

  FIG. 2A is a diagram illustrating another example of a dangerous portion of the circuit mask pattern, and FIG. 2B is a diagram illustrating the light intensity of the dangerous portion.

  In FIG. 2A, the evaluation point B is located between the two end edges of the opposing pattern 121. The evaluation point B is arranged in the pattern 121.

  FIG. 2B shows the light intensity in the resist layer when the circuit mask pattern is projected onto the resist layer along a line connecting the two evaluation points A and B. Since the light intensity at the position of the resist layer corresponding to the two evaluation points A is larger than the threshold value S101, the resist layer is resolved.

  In the example shown in FIG. 2B, since the light intensity at the position of the resist layer corresponding to the evaluation point B is smaller than the threshold value S101, the central portion of the pattern 121 is not resolved. Is formed.

  As described above, the optical proximity effect also occurs between the edges of the opposing patterns in the circuit mask pattern. Therefore, the target circuit pattern based on the circuit design data is accurately determined in order to prevent the formation of a dangerous place. A circuit mask pattern to be transferred is desired.

  For example, the light intensity at three evaluation points on the edge of the opposing pattern in the circuit mask pattern and in and near the edge of the edge of the circuit mask pattern is obtained, and the position between the edges of the opposing pattern in the circuit mask pattern is determined. It has been proposed to correct the optical proximity effect. In this proposal, in order to correct the optical proximity effect on the position between the edges of the opposing patterns in the circuit mask pattern, the evaluation points of the opposite edges of the patterns are determined based on the light intensity of the three evaluation points. Only one of the included edges is subject to correction. On the other hand, the other edge is not a correction target. Therefore, in order to sufficiently correct the influence of the optical proximity effect on the position between the edges of the opposing patterns in the circuit mask pattern, the light intensity of the three evaluation points is similarly applied to the other opposing edges. Need to be calculated.

  In this specification, in order to solve the above-described problem, an object is to provide a mask pattern correction method.

  It is another object of the present specification to provide a mask pattern correction apparatus in order to solve the above-described problems.

  It is another object of the present specification to provide a circuit design apparatus in order to solve the above-described problems.

  Furthermore, the present specification aims to provide a program for correcting a mask pattern in order to solve the above-described problem.

  According to one aspect of the mask pattern correction method disclosed in this specification, an evaluation point for obtaining light intensity is arranged between edges of opposing patterns in the mask pattern, and the light intensity of the evaluation point is obtained. Determining a correction amount for the optical proximity effect at each edge of the opposing pattern based on the obtained light intensity of the evaluation point, and determining each of the edges of the opposing pattern based on the correction amount. The computer performs the position correction.

  Further, according to one embodiment of the mask pattern correction device disclosed in the present specification, the storage unit that stores the mask pattern and the mask pattern stored in the storage unit are read out, and the edges of the opposing patterns in the mask pattern are read out. An evaluation point for determining the light intensity is arranged between them, the light intensity of the evaluation point is determined, and the optical proximity of each edge of the opposing pattern is determined based on the calculated light intensity of the evaluation point. A calculation unit that determines a correction amount for the effect and corrects the position of each edge of the opposing pattern based on the correction amount.

  Further, according to one embodiment of the circuit design device disclosed in the present specification, a mask pattern is designed based on the circuit design data read from the storage unit that stores the circuit design data, and the mask pattern is opposed to the mask pattern. An evaluation point for obtaining the light intensity is arranged between the edges of the pattern to be obtained, the light intensity of the evaluation point is obtained, and each edge of the opposing pattern is determined based on the obtained light intensity of the evaluation point. A calculation unit that determines a correction amount for each optical proximity effect and corrects the position of each edge of the opposing pattern based on the correction amount.

  Furthermore, according to one form of the program for correcting a mask pattern disclosed in this specification, an evaluation point for obtaining light intensity is arranged between edges of opposing patterns in the mask pattern, and the light of the evaluation point is arranged. Determine the intensity, determine a correction amount for the optical proximity effect at each edge of the opposing pattern based on the calculated light intensity of the evaluation point, and determine the edge of the opposing pattern based on the correction amount. Causes the computer to correct the position of each edge.

  According to one aspect of the mask pattern correction method disclosed in the present specification described above, a mask pattern for accurately transferring a circuit pattern based on circuit design data can be obtained.

  In addition, according to one aspect of the mask pattern correction device disclosed in the present specification, a mask pattern for accurately transferring a circuit pattern based on circuit design data can be obtained.

  Further, according to one embodiment of the circuit design apparatus disclosed in the present specification, a mask pattern for accurately transferring a circuit pattern based on circuit design data can be obtained.

  Further, according to one form of the program for correcting a mask pattern disclosed in the present specification, a mask pattern for accurately transferring a circuit pattern based on circuit design data can be obtained.

  The objects and advantages of the invention will be realized and obtained by means of the elements and combinations particularly pointed out in the appended claims.

  Both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention as claimed.

(A) is a figure which shows the example of the dangerous location of a circuit mask pattern, (B) is a figure which shows the light intensity of a dangerous location. (A) is a figure which shows the other example of the dangerous location of a circuit mask pattern, (B) is a figure which shows the light intensity of a dangerous location. 1 is a diagram illustrating a first embodiment of a circuit design device disclosed in this specification. FIG. It is a flowchart (the 1) explaining operation | movement of the circuit design apparatus disclosed by this specification. It is a flowchart (the 2) explaining operation | movement of the circuit design apparatus disclosed by this specification. It is a flowchart (the 3) explaining operation | movement of the circuit design apparatus disclosed by this specification. (A) is a figure which shows the circuit mask pattern of the photomask produced based on circuit design data, (B) is a figure which shows the circuit mask pattern by which the pre-bias correction | amendment was carried out. (A) is a figure which shows the circuit mask pattern by which the edge division | segmentation was carried out, (B) is a figure which shows the circuit mask pattern by which the 1st evaluation point is arrange | positioned. It is a figure which shows the circuit mask pattern by which the 2nd evaluation score is arrange | positioned. (A) is a figure explaining the example 1 by which the light intensity of a 2nd evaluation point is compared with a 2nd threshold value, (B) is a figure which moves the position of the edge of an opposing pattern by correction | amendment. . It is a figure explaining the example 2 with which the light intensity of a 2nd evaluation point is compared with a 2nd threshold value. (A) is a figure explaining the example 3 by which the light intensity of a 2nd evaluation point is compared with a 2nd threshold value, (B) is a figure which moves the position of the edge of an opposing pattern by correction | amendment. . It is a flowchart explaining operation | movement of the modification of the circuit design apparatus disclosed to this specification. It is a flowchart explaining operation | movement of 2nd Embodiment of the circuit design apparatus disclosed by this specification. It is a figure which shows the example 1 of correction | amendment when the edge of the pattern which opposes has a correction | amendment priority. It is a figure which shows the example 2 of a correction | amendment when the edge of the pattern which opposes has a correction | amendment priority. It is a figure which shows the example 3 of a correction | amendment when the edge of the pattern which opposes has a correction priority. It is a figure which shows the example 4 of a correction | amendment when the edge of the pattern which opposes has a correction priority.

  Hereinafter, a preferred embodiment of a circuit design apparatus disclosed in this specification will be described with reference to the drawings. However, the technical scope of the present invention is not limited to these embodiments, but extends to the invention described in the claims and equivalents thereof.

  FIG. 3 is a diagram illustrating a first embodiment of a circuit design device disclosed in this specification.

  The circuit design device 10 of this embodiment designs a circuit mask pattern of a photomask based on circuit design data. In addition, the circuit design device 10 corrects the optical proximity effect on the designed circuit mask pattern. In this way, the circuit design apparatus 10 creates a circuit mask pattern so that the target circuit pattern based on the circuit design data is accurately transferred to a resist layer or the like on the wafer in photolithography. Then, based on the circuit mask pattern created by the circuit design apparatus 10, a photomask having a mask pattern corresponding to the type of the negative or positive resist layer is formed.

  As illustrated in FIG. 3, the circuit design device 10 includes a calculation unit 11 that executes a predetermined program, and a storage unit 12 that stores a predetermined program, circuit design data, and the like. In addition, the circuit design device 10 includes a display unit 13 that displays calculation results of the calculation unit 11, an input unit 14 that inputs information to the circuit design device 10, and a communication unit 15 that communicates with an external network or the like. And have. The communication unit 15 may have an interface function for connecting peripheral devices to the circuit design device 10.

  The storage unit 12 may store a predetermined program stored in the storage medium by installing it in the storage unit 12. Alternatively, a predetermined program may be installed and stored in the storage unit 12 via a network.

  The circuit design device 10 can be formed using, for example, a computer such as a server or a personal computer, or a state machine.

  Next, the operation of the circuit design device 10 of the present embodiment described above will be described below with reference to the drawings. Each operation of the circuit design device 10 is executed by the arithmetic unit 11 executing a predetermined program stored in the storage unit 12.

  FIG. 4 is a flowchart (part 1) for explaining the operation of the circuit design apparatus disclosed in this specification. FIG. 5 is a flowchart (part 2) for explaining the operation of the circuit design apparatus disclosed in this specification. FIG. 6 is a flowchart (part 3) for explaining the operation of the circuit design apparatus disclosed in this specification.

  First, in step S10, circuit design data is read from the storage unit 12, and a circuit mask pattern is designed.

  FIG. 7A shows a circuit mask pattern of a photomask created based on circuit design data.

  In the example shown in FIG. 7A, a circuit mask pattern 20 having a pattern 21 and a pattern 22 is formed. The pattern 21 has a U-shape. The pattern 22 has an I-shape and is arranged so as to extend into the recess of the pattern 21. Each of the pattern 21 and the pattern 22 is formed by being surrounded by a plurality of edges.

  Next, in step S12, pre-bias correction is performed on the circuit mask pattern 20.

  FIG. 7B is a diagram showing a circuit mask pattern subjected to pre-bias correction.

  When the exposed transfer pattern of the resist layer on the wafer is etched, a shift due to a process such as dimensional variation occurs with respect to the target circuit pattern. Therefore, the pre-bias correction is performed on the circuit mask pattern to correct in advance the deviation caused by the process. The pre-bias correction value for the circuit mask pattern is stored in the rule table as a correction value for each pattern width, for example, and the pre-bias correction is performed on the circuit mask pattern with reference to this rule table.

  Next, in step S <b> 14, edge division is performed on each pattern of the circuit mask pattern 20.

  FIG. 8A is a diagram showing a circuit mask pattern obtained by dividing the edge.

  In the edge division, the edge of the pattern is divided into correction units for correcting the optical proximity effect. The same correction value is applied to one edge-divided portion. In the patterns 21 and 22 shown in FIG. 8A, a short line intersecting the end edge is described for each correction unit, and a portion of one end edge divided is shown.

  Next, in step S <b> 16, first evaluation points A for determining the light intensity are arranged at the edge of each pattern of the circuit mask pattern 20.

  FIG. 8B is a diagram showing a circuit mask pattern in which the first evaluation points are arranged.

  The first evaluation point A corresponds to a position where the light intensity of the resist layer when the circuit mask pattern is projected onto the resist layer on the wafer is calculated. One or a plurality of first evaluation points A may be arranged for one correction unit obtained by dividing the edge.

  Next, between step S18 and step S24, a second evaluation point for determining the light intensity is arranged between the edges of the opposing patterns with respect to the edges of the opposing patterns of the circuit mask pattern 20. The

  First, in step S20, it is determined whether the distance between the edges of the opposing patterns is shorter than a predetermined distance. The predetermined distance can be determined as a distance at which contact or disconnection may occur in the circuit pattern transferred to the resist layer on the wafer based on, for example, process conditions such as exposure wavelength and process capability. When the distance between the edges of the opposing patterns is shorter than the predetermined distance, the process proceeds to step S22.

  In step S22, the second evaluation point is arranged at a position intermediate between the edges of the opposing patterns. Note that the position where the second evaluation point is arranged is not necessarily between the edges of the opposing patterns as long as it is between the edges of the opposing patterns.

  FIG. 9 is a diagram showing a circuit mask pattern in which the second evaluation points are arranged.

  In FIG. 9, since the distance L1 between the edges of the opposing patterns is shorter than a predetermined distance, the second evaluation point B1 is arranged at an intermediate position between the two opposing first evaluation points A. In addition, since the distance L2 between the edges of the opposing patterns is shorter than the predetermined distance, the second evaluation point B2 is arranged at an intermediate position between the first evaluation point A and the opposing edge. Further, since the distance L3 between the edges of the opposing patterns is shorter than the predetermined distance, the second evaluation point B3 is arranged at an intermediate position between the corner of the pattern 21 and the corner of the pattern 22. As described above, the edge of the pattern includes a corner portion formed by connecting the two edges. The second evaluation points B <b> 1 to B <b> 3 are examples in which the second evaluation point is arranged between the pattern 21 and the pattern 22.

  In FIG. 9, since the distance L4 between the edges of the opposing patterns is shorter than a predetermined distance, the second evaluation point B4 is arranged at an intermediate position between the two opposing first evaluation points A. The second evaluation point B4 is an example in which the second evaluation point is arranged in one pattern.

  In FIG. 9, only a part of the second evaluation points is shown for easy understanding.

  On the other hand, in step S20, if the distance between the edges of the opposing patterns is not shorter than the predetermined distance, the process proceeds to step S24 without placing the second evaluation point between the edges.

  Thus, in the present embodiment, the second evaluation points are not unconditionally arranged between the edges of all the opposing patterns. Accordingly, since the number of second evaluation points for obtaining the light intensity by calculation can be suppressed, the calculation time required for correcting the optical proximity effect is reduced.

  Next, between steps S26 and S34, after the light intensity is obtained for each first evaluation point, the position of the edge of the pattern is corrected if necessary.

  First, in step S28, the light intensity at the position corresponding to the first evaluation point of the resist layer when the circuit mask pattern 20 is projected onto the resist layer on the wafer is calculated. In this way, the light intensity at each position of the edge of the opposing pattern can be obtained. A known method can be used as a method for calculating the light intensity. For example, the light intensity can be obtained using a table that defines conditions such as exposure wavelength and exposure intensity. Hereinafter, in this specification, the light intensity at the position corresponding to the first evaluation point of the resist layer when the circuit mask pattern 20 is projected onto the resist layer on the wafer is also simply referred to as the light intensity of the first evaluation point. .

  Next, in step S30, the obtained light intensity is compared with the first threshold value to determine whether or not the optical proximity effect is corrected. The first threshold value may be defined as a predetermined range having an upper limit value and a lower limit value. If it is determined that the light intensity is larger or smaller than the first threshold value, it is determined that the optical proximity effect needs to be corrected, and the process proceeds to step S32. On the other hand, if it is determined in step S30 that correction for the optical proximity effect is not necessary, the process proceeds to step S34. The first threshold value can be determined based on, for example, process conditions such as pattern width and exposure wavelength, process capability, and the like.

  Next, in step S32, a first correction amount for the optical proximity effect at each position of the edge of the opposing pattern is determined, and the position of each edge of the opposing pattern is determined based on the first correction amount. Is corrected. The first correction amount is determined so that an appropriate light intensity can be obtained based on the difference between the light intensity obtained in step S28 and the first threshold value, as well as the process conditions such as the exposure wavelength and the process capability. obtain.

  After the first evaluation point is newly arranged on the edge of the pattern whose edge position is corrected in this way, the process returns to step S28 again, and the light intensity corresponding to the first evaluation point is obtained.

  If it is determined in step S30 that correction for the optical proximity effect is not necessary, the process proceeds to step S34. On the other hand, if it is determined again that correction for the optical proximity effect is necessary, the process proceeds to step S32 again, and the processes of steps S32 to S30 are repeated. From the viewpoint of preventing the process from diverging by repeating the processes of steps S32 to S30, an upper limit value may be provided for the first correction amount determined in step S32.

  Next, after the light intensity is obtained for each second evaluation point between step S36 and step S44, the position of each edge of the opposing pattern is corrected if necessary.

  First, in step S38, the light intensity at the position corresponding to the second evaluation point of the resist layer when the circuit mask pattern 20 is projected onto the resist layer on the wafer is calculated. In this way, the light intensity at the position corresponding to the second evaluation point of the resist layer can be obtained. A known method can be used as a method for calculating the light intensity. For example, the light intensity can be obtained using a table that defines conditions such as exposure wavelength and exposure intensity. Hereinafter, in this specification, the light intensity at the position corresponding to the second evaluation point of the resist layer when the circuit mask pattern 20 is projected onto the resist layer on the wafer is also simply referred to as the light intensity of the second evaluation point. .

  Next, in step S40, the obtained light intensity is compared with the second threshold value to determine whether or not the optical proximity effect is corrected. The second threshold value may be defined as a predetermined range having an upper limit value and a lower limit value. If it is determined that the light intensity is larger or smaller than the second threshold value, it is determined that the optical proximity effect needs to be corrected, and the process proceeds to step S42. On the other hand, if it is determined in step S40 that correction for the optical proximity effect is not necessary, the process proceeds to step S44. The second threshold value can be determined based on, for example, process conditions such as pattern width and exposure wavelength, process capability, and the like.

  Next, in step S42, a second correction amount of the optical proximity effect for each edge of the opposing pattern is determined, and the position of each edge of the opposing pattern is corrected based on this second correction amount. The second correction amount is determined so that an appropriate light intensity can be obtained based on the difference between the light intensity obtained in step S38 and the second threshold, as well as the process conditions such as the exposure wavelength and the process capability. obtain.

  After correcting the positions of the edges of the opposing patterns across the second evaluation point in this way, the process returns to step S38 again to determine the light intensity at the second evaluation point. Here, since the position of the second evaluation point is determined with respect to the target circuit pattern, it is the same before and after the correction of the position of each edge of the opposing pattern.

  If it is determined in step S40 that correction for the optical proximity effect is not necessary, the process proceeds to step S44. On the other hand, if it is determined again that the optical proximity effect needs to be corrected, the process proceeds to step S42 again, and the processes of steps S42 to S40 are repeated. From the viewpoint of preventing the process from diverging by repeating the processes in steps S42 to S40, an upper limit value may be provided for the second correction amount determined in step S42.

  Next, an example of comparing the light intensity at the second evaluation point with the second threshold value will be described below with reference to the drawings.

  FIG. 10A is a diagram for explaining Example 1 in which the light intensity at the second evaluation point is compared with the second threshold value, and FIG. 10B moves the position of the edge of the opposing pattern by correction. It is a figure to do.

  FIG. 10A shows the light intensity C1 on the resist layer with respect to the position along the line M in FIG. The light intensity at the second evaluation point B1 is compared with a second threshold value S2 having a value different from the first threshold value S1. When the second evaluation point B1 is located between the patterns, the second threshold value S2 is preferably set smaller than the first threshold value S1.

  In the example shown in FIG. 10A, since the light intensity at the second evaluation point B1 is larger than the second threshold value S2, the second resist layer when the circuit mask pattern 20 is projected onto the resist layer on the wafer. It is determined that the position corresponding to the evaluation point B1 is resolved. Accordingly, in order to reduce the light intensity of the second evaluation point B1 so that the position corresponding to the second evaluation point B1 is not resolved, as shown in FIG. The position of each edge of the pattern is corrected.

  Here, the reason why the light intensity at the second evaluation point B1 is compared with the second threshold value S2 having a value different from the first threshold value S1 will be described below.

  When the light intensity at the second evaluation point B1 is compared with the first threshold value S1, the light intensity at the second evaluation point B1 is smaller than the first threshold value S1. Therefore, it is determined that the position corresponding to the second evaluation point B1 of the resist layer when the circuit mask pattern 20 is projected onto the resist layer on the wafer is not resolved. However, experience has shown that the position corresponding to the second evaluation point B1 may be resolved even if the light intensity of the second evaluation point B1 is smaller than the first threshold value S1. Therefore, in the present embodiment, the light intensity at the second evaluation point B1 is compared with the second threshold value S2 having a value different from the first threshold value S1. As described above, the second threshold value can be determined based on the process conditions such as the pattern width and the exposure wavelength, the process capability, and the like. For example, the second threshold value can be 5% smaller than the first threshold value.

  In FIG. 10A, the light intensity of each of the two first evaluation points A is larger than the first threshold value S1, and the resist when the circuit mask pattern 20 is projected onto the resist layer on the wafer. It is determined that the position corresponding to the two first evaluation points A of the layer is resolved.

  FIG. 11 is a diagram for explaining an example 2 in which the light intensity at the second evaluation point is compared with the second threshold value.

  In the example shown in FIG. 11, the magnitude of the exposure intensity is increased with respect to the exposure intensity used to obtain the light intensity in FIG. 10, and the light intensity at the second evaluation point in step S38 is obtained. FIG. 11 shows the light intensity C2 on the resist layer relative to the position along line M in FIG. The exposure intensity used for obtaining the light intensity in FIG. 11 is increased by a magnitude corresponding to the ratio of the first threshold value S1 to the second threshold value S2 in FIG. In FIG. 11, the light intensity at the second evaluation point B1 is compared with the first threshold value S1 as the second threshold value. That is, in the example shown in FIG. 11, the second threshold value has the same value as the first threshold value. Also in FIG. 11, since the light intensity of the second evaluation point B1 is larger than the first threshold value S1, it corresponds to the second evaluation point B1 of the resist layer when the circuit mask pattern 20 is projected onto the resist layer on the wafer. It is determined that the position to be resolved is resolved. That is, the example shown in FIG. 11 has the same contents as FIG. In the example shown in FIG. 11, the light intensity at the second evaluation point is determined as the threshold value as in FIG. 10, but the light intensity is obtained instead of using the second threshold value having a value different from the first threshold value. Therefore, the value of the exposure intensity used is changed.

  FIG. 12A is a diagram for explaining Example 3 in which the light intensity at the second evaluation point is compared with the second threshold value, and FIG. 12B is a diagram in which the position of the edge of the opposing pattern is moved by correction. It is a figure to do.

  FIG. 12A shows the light intensity C3 on the resist layer with respect to the position along the line N in FIG. The light intensity of the second evaluation point B4 is compared with the second threshold value S2 having a value different from the first threshold value S1, but when the second evaluation point B4 is located in one pattern, the second threshold value S2 is preferably set to a value larger than the first threshold value S1.

  In the example shown in FIG. 12A, since the light intensity at the second evaluation point B4 is smaller than the second threshold value S2, the second resist layer when the circuit mask pattern 20 is projected onto the resist layer on the wafer. It is determined that the position corresponding to the evaluation point B4 is not resolved. Therefore, in order to increase the light intensity corresponding to the second evaluation point B4 so that the position corresponding to the second evaluation point B4 is resolved, the second evaluation point B4 is sandwiched as shown in FIG. Thus, the position of each edge of the opposing pattern is corrected.

  Here, the reason why the light intensity at the second evaluation point B1 is compared with the second threshold value S2 having a value different from the first threshold value S1 will be described below.

  When the light intensity at the second evaluation point B4 is compared with the first threshold value S1, the light intensity corresponding to the second evaluation point B4 is greater than the first threshold value S1. Therefore, it is determined that the position corresponding to the second evaluation point B4 of the resist layer when the circuit mask pattern 20 is projected onto the resist layer on the wafer is resolved. However, experience has shown that the position corresponding to the second evaluation point B4 may not be resolved even if the light intensity of the second evaluation point B4 is greater than the first threshold value S1. Therefore, in the present embodiment, the light intensity at the second evaluation point B4 is compared with the second threshold value S2 having a value different from the first threshold value S1. As described above, the second threshold value can be determined based on the process conditions such as the pattern width and the exposure wavelength, the process capability, and the like. For example, the second threshold value can be increased by 5% relative to the first threshold value.

  In FIG. 12A, the light intensity of each of the two first evaluation points A is larger than the first threshold value S1, and the resist when the circuit mask pattern 20 is projected onto the resist layer on the wafer. It is determined that the position corresponding to the two first evaluation points A of the layer is resolved.

  Further, the first threshold value shown in FIG. 10A and the first threshold value shown in FIG. 12A may be the same value or different values.

  According to the above-described circuit design apparatus of the present embodiment, the target circuit pattern based on the circuit design data is prevented from being shifted from the transfer pattern due to process factors such as etching and optical factors of the optical proximity effect. Correction for this is performed on the circuit mask pattern. Therefore, by using such a circuit mask pattern, the target circuit pattern based on the circuit design data can be accurately transferred to the resist layer on the wafer.

  Next, a modification of the circuit design device of the first embodiment described above will be described below with reference to the drawings.

  FIG. 13 is a flowchart for explaining the operation of a modified example of the circuit design apparatus disclosed in this specification.

  This modification specifically explains how to determine the second correction amount in FIG. 6 described above. Therefore, differences from the flowchart shown in FIG. 6 will be described below with reference to FIG.

  First, if it is determined in step S40 that the light intensity at the second evaluation point is larger or smaller than the second threshold value, it is determined that correction for the optical proximity effect is necessary, and the process proceeds to step S46.

  Next, in step S46, the position of each edge of the opposing pattern is moved by a distance corresponding to one lattice. The position of the edge of the pattern shown in FIG. 9 is discretely arranged, and one grid is the smallest unit for determining the position where the edge of the pattern is arranged.

  In this way, after the positions of the edges of the opposing patterns are moved across the second evaluation point, the second evaluation points are arranged at a position intermediate between the edges of the opposing patterns. And it returns to step S38 again and the light intensity of a 2nd evaluation point is calculated | required.

  If it is determined in step S40 that correction for the optical proximity effect is not necessary, the process proceeds to step S48. On the other hand, if it is determined again that the optical proximity effect needs to be corrected, the process proceeds again to step S46, and the processes of steps S46 to S40 are repeated.

  When the process proceeds to step S48, the distance corresponding to the number of lattices moved at the positions of the edges of the opposing pattern is set as the second correction amount, and then the process proceeds to step S44.

  Other processes in the present modification are the same as those in the first embodiment described above.

  Next, a second embodiment of the circuit design apparatus described above will be described below with reference to FIGS. For points that are not particularly described in the other embodiments, the description in detail regarding the first embodiment is applied as appropriate. Moreover, the same code | symbol is attached | subjected to the same component.

  In the circuit design device of this embodiment, each edge of the opposing pattern has a correction priority, and when determining the second correction amount, the first edge of the pattern with the lower correction priority is determined. 2 Set the correction amount to zero. In other words, each edge of the opposing pattern is the object of correction, but the second correction amount of the edge of the pattern with the lower correction priority is set to zero, and the edge of the edge of the pattern with the higher correction priority is set to zero. 2 Correction amount is determined. Then, the position of the edge of the pattern having the higher correction priority is moved based on the determined second correction amount.

  Hereinafter, the operation of the circuit design apparatus according to the present embodiment will be described with reference to the drawings.

  FIG. 14 is a flowchart for explaining the operation of the second embodiment of the circuit design apparatus disclosed in this specification.

  The operation of the circuit design apparatus according to the present embodiment is different from the process in FIG. 13 in the case where it is determined in the flowchart shown in FIG. 13 that correction for the optical proximity effect in step S40 is necessary. Therefore, differences from the processing shown in FIG. 13 will be described below.

  First, if it is determined in step S40 in FIG. 13 that correction for the optical proximity effect is necessary, the process proceeds to step S50 in FIG.

  In step S50, the second correction amount of the edge of the pattern having the lower correction priority is determined to be zero. In the following processing, the second correction amount of the edge of the pattern having the higher correction priority is determined.

  Next, in step S52, the position of the edge of the pattern having the higher correction priority is moved by a distance corresponding to one lattice. And it progresses to step S38 and the light intensity in a 2nd evaluation point is calculated | required again. The following processing is the same as the processing shown in FIG.

  Next, a correction example in the case where each edge of the opposing pattern has a correction priority will be described below with reference to the drawings.

  FIG. 15 is a diagram illustrating a correction example 1 in a case where the edges of the opposing patterns have the correction priority order.

  In the example shown in FIG. 15, the line width W1 of the pattern 21 to which the edge of the pattern having the first evaluation point A1 belongs is narrower than the line width W2 of the pattern 22 to which the edge of the pattern having the first evaluation point A2 belongs. .

  In this embodiment, from the viewpoint of preventing disconnection, the correction priority order of the edge of the pattern having the narrower line width of the pattern to which the edge of the pattern belongs is the edge of the other pattern. Is set lower than the correction priority order.

  That is, the correction priority of the edge of the pattern 21 having the first evaluation point A1 is set lower than the correction priority of the edge of the pattern 22 having the first evaluation point A2. Therefore, the second correction amount of the edge of the pattern 21 having the first evaluation point A1 is determined to be zero.

  On the other hand, the second correction amount is determined for the edge of the pattern 22 having the first evaluation point A2, and the position of the edge of the pattern 22 having the first evaluation point A2 is moved as indicated by an arrow.

  FIG. 16 is a diagram illustrating a correction example 2 in a case where the edges of the opposing patterns have the correction priority order.

  In the example shown in FIG. 16, the pattern 21 and the pattern 22 are arranged in a T shape. The pattern 22 has a contact layer 24 that is electrically connected to other layers. On the other hand, the pattern 21 does not have such a contact layer.

  In the present embodiment, when the pattern to which the edge of one pattern belongs has a contact layer at the edge of the opposing pattern, the correction priority of the edge of one pattern is set to the edge of the edge of the other pattern. It is set lower than the correction priority. This is to secure the area of the wiring portion around the contact layer and to ensure the electrical conductivity between the wiring and the contact layer.

  That is, the correction priority of the edge of the pattern 22 having the first evaluation point A2 is set lower than the correction priority of the edge of the pattern 21 having the first evaluation point A1. Therefore, the second correction amount of the edge of the pattern 22 having the first evaluation point A2 is determined to be zero.

  On the other hand, the second correction amount is determined for the edge of the pattern 21 having the first evaluation point A1, and the position of the edge of the pattern 21 having the first evaluation point A1 is moved as indicated by an arrow.

  FIG. 17 is a diagram illustrating a third correction example in a case where the edges of the opposing patterns have the correction priority order.

  In the example shown in FIG. 17, the pattern 21 and the pattern 22 are arranged so as to face each other in an I shape. The pattern 21 has a contact layer 24 that is electrically connected to other layers. On the other hand, the pattern 22 does not have such a contact layer.

  Similarly to the example shown in FIG. 16, the second correction amount of the edge of the pattern 21 having the first evaluation point A1 is determined to be zero. On the other hand, the second correction amount is determined for the edge of the pattern 22 having the first evaluation point A2, and the position of the edge of the pattern 22 having the first evaluation point A2 is moved as indicated by an arrow.

  FIG. 18 is a diagram illustrating a correction example 4 in a case where the edges of the opposing patterns have the correction priority order.

  In the example shown in FIG. 18, the pattern 21 and the pattern 22 are arranged so as to face each other in an I-shape. Each of the pattern 21 and the pattern 22 has a contact layer 24 that is electrically connected to another layer. Therefore, the correction priority of the edge of the pattern 21 having the first evaluation point A1 is set to be the same as the correction priority of the edge of the pattern 22 having the first evaluation point A2.

  When the edges of the opposing patterns have the same correction priority, the second correction amount is determined for the edges of both patterns, and the positions of the edges of the opposing patterns are indicated by arrows. It is corrected as shown in.

  In the present invention, the circuit mask pattern correction method, the circuit mask pattern correction apparatus, the circuit design apparatus, and the circuit mask pattern correction program according to the above-described embodiment can be appropriately changed without departing from the spirit of the present invention. . In addition, the configuration requirements of one embodiment can be applied to other embodiments as appropriate.

  For example, in each of the embodiments described above, the circuit design apparatus has a function of correcting the optical proximity effect on the circuit mask pattern. However, a circuit mask pattern correction device that exists separately from the circuit design device corrects the circuit mask pattern designed by the circuit design device based on the circuit design data so as to correct the influence of the optical proximity effect. Also good.

  All examples and conditional words mentioned herein are intended for educational purposes to help the reader deepen and understand the inventions and concepts contributed by the inventor. All examples and conditional words mentioned herein are to be construed without limitation to such specifically stated examples and conditions. Also, such exemplary mechanisms in the specification are not related to showing the superiority and inferiority of the present invention. While embodiments of the present invention have been described in detail, it should be understood that various changes, substitutions or modifications can be made without departing from the spirit and scope of the invention.

  Regarding the above-described embodiments, the following additional notes are disclosed.

(Appendix 1)
An evaluation point for determining the light intensity is arranged between the edges of the opposing patterns in the mask pattern,
Obtain the light intensity of the evaluation point,
Based on the obtained light intensity of the evaluation point, determine the correction amount for the optical proximity effect of each edge of the opposing pattern,
A mask pattern correction method in which a computer executes correction of the position of each edge of an opposing pattern based on the correction amount.

(Appendix 2)
The mask pattern correction method according to supplementary note 1, wherein the evaluation points are arranged at locations where the distance between the edges of the opposing patterns is greater than a predetermined distance.

(Appendix 3)
3. The mask pattern correction method according to appendix 1 or 2, wherein the evaluation point is arranged at a middle position between edges of the opposing patterns.

(Appendix 4)
The light intensity at each position of the opposite edge of the pattern is obtained, and the obtained light intensity is compared with the second threshold value to compare the light intensity at the position of each edge of the opposite pattern with respect to the optical proximity effect. 2 is determined, and based on the second correction amount, the position of each edge of the opposing pattern is corrected,
Note that the light intensity at the obtained evaluation point is compared with a first threshold value different from the second threshold value to determine the correction amount for the optical proximity effect at each edge of the opposing pattern. The mask pattern correction method according to any one of claims 1 to 3.

(Appendix 5)
The mask pattern correction method according to supplementary note 4, wherein the first threshold value is smaller than the second threshold value when the evaluation point is located between patterns.

(Appendix 6)
The mask pattern correction method according to supplementary note 4, wherein the first threshold value is larger than the second threshold value when the evaluation point is located in the pattern.

(Appendix 7)
Each of the edges of the opposing patterns has a correction priority, and the correction amount of the edge of the pattern having the lower correction priority is set to zero. Correction method.

(Appendix 8)
Note 7: At the edge of the opposite pattern, the correction priority of the pattern edge having the narrower line width of the pattern to which the pattern edge belongs is set lower than the correction priority of the edge of the other pattern. The mask pattern correction method described in 1.

(Appendix 9)
When the pattern to which the edge of one pattern belongs has a contact layer at the edge of the opposing pattern, the correction priority of the edge of one pattern is set to the correction priority of the edge of the other pattern. The mask pattern correction method according to appendix 7, wherein the mask pattern is made lower.

(Appendix 10)
A storage unit for storing a mask pattern;
Read the mask pattern stored in the storage unit, place an evaluation point for obtaining the light intensity between the edges of the opposing pattern in the mask pattern,
Obtain the light intensity of the evaluation point,
Based on the obtained light intensity of the evaluation point, determine the correction amount for the optical proximity effect of each edge of the opposing pattern,
An arithmetic unit for correcting the position of each edge of the opposing pattern based on the correction amount;
A mask pattern correction apparatus comprising:

(Appendix 11)
A storage unit for storing circuit design data;
Design a mask pattern based on the circuit design data read from the storage unit,
An evaluation point for determining the light intensity is arranged between the edges of the opposing patterns in the mask pattern,
Obtain the light intensity of the evaluation point,
Based on the obtained light intensity of the evaluation point, determine the correction amount for the optical proximity effect of each edge of the opposing pattern,
An arithmetic unit for correcting the position of each edge of the opposing pattern based on the correction amount;
A circuit design apparatus comprising:

(Appendix 12)
An evaluation point for determining the light intensity is arranged between the edges of the opposing patterns in the mask pattern,
Obtain the light intensity of the evaluation point,
Based on the obtained light intensity of the evaluation point, determine the correction amount for the optical proximity effect of each edge of the opposing pattern,
A program for correcting a mask pattern that causes a computer to correct the position of each edge of an opposing pattern based on the correction amount.

(Appendix 13)
A method for correcting an optical proximity effect of a mask pattern created based on circuit design data for transferring a circuit pattern onto a resist,
An evaluation point for determining the light intensity is arranged between the edges of the opposing patterns in the mask pattern,
Obtain the light intensity at a position corresponding to the evaluation point on the resist on which the mask pattern is projected,
Based on the light intensity at the position corresponding to the obtained evaluation point, determine a correction amount for the optical proximity effect of each edge of the opposing pattern,
A mask pattern correction method in which a computer executes correction of the position of each edge of the opposing pattern in the mask pattern based on the correction amount.

DESCRIPTION OF SYMBOLS 10 Circuit design apparatus 11 Computation part 12 Storage part 13 Display part 14 Input part 15 Communication part 20 Circuit mask pattern 21,22 Pattern 24 Contact layer A, A1, A2 1st evaluation point B, B1, B2 on the edge of a pattern , B3, B4 Second evaluation points between the edges of the opposing patterns L1, L2, L3, L4 Distances between the edges of the opposing patterns M, N Connect two opposing first evaluation points and second evaluation points Line S1 First threshold S2 Second threshold C1, C2, C3 Light intensity curve W1, W2 Pattern width

Claims (5)

A first evaluation point is arranged at each of the opposite edges of the mask pattern;
A first light intensity at each of the first evaluation points is obtained, and the obtained first light intensity is compared with a first threshold value to compare the first light intensity with respect to the optical proximity effect at each position of the edge of the opposing pattern. 1 correction amount is determined, and based on the 1 correction amount, the position of each edge of the opposing pattern is corrected,
A second evaluation point is arranged between a pattern including one edge of the opposing pattern and a pattern including the other edge of the opposing pattern;
Determining a second light intensity of the second evaluation point;
The obtained second light intensity is compared with a second threshold value that is smaller than the first threshold value to determine a second correction amount for the optical proximity effect at each edge of the opposing pattern,
Based on the second correction amount, the position of each edge of the opposing pattern is corrected,
A mask pattern correction method executed by a computer.   The mask pattern correction method according to claim 1, wherein the second evaluation point is arranged at a location where a distance between edges of the opposing patterns is shorter than a predetermined distance.   3. The mask pattern correction method according to claim 1, wherein the second evaluation point is arranged at an intermediate position between edges of the opposing patterns. A storage unit for storing a mask pattern;
The mask pattern stored in the storage unit is read out, and a first evaluation point is arranged on each edge of the opposing pattern in the mask pattern,
A first light intensity at each of the first evaluation points is obtained, and the obtained first light intensity is compared with a first threshold value to compare the first light intensity with respect to the optical proximity effect at each position of the edge of the opposing pattern. 1 correction amount is determined, and based on the 1 correction amount, the position of each edge of the opposing pattern is corrected,
A second evaluation point is arranged between a pattern including one edge of the opposing pattern and a pattern including the other edge of the opposing pattern;
Determining a second light intensity of the second evaluation point;
The obtained second light intensity is compared with a second threshold value that is smaller than the first threshold value to determine a second correction amount for the optical proximity effect at each edge of the opposing pattern,
An arithmetic unit that corrects the position of each edge of the opposing pattern based on the second correction amount;
A mask pattern correction apparatus comprising: A storage unit for storing circuit design data;
Designing a mask pattern based on the circuit design data read from the storage unit,
A first evaluation point is disposed on each of the opposite edges of the mask pattern;
A first light intensity at each of the first evaluation points is obtained, and the obtained first light intensity is compared with a first threshold value to compare the first light intensity with respect to the optical proximity effect at each position of the edge of the opposing pattern. 1 correction amount is determined, and based on the 1 correction amount, the position of each edge of the opposing pattern is corrected,
A second evaluation point is arranged between a pattern including one edge of the opposing pattern and a pattern including the other edge of the opposing pattern;
Determining a second light intensity of the second evaluation point;
The obtained second light intensity is compared with a second threshold value that is smaller than the first threshold value to determine a second correction amount for the optical proximity effect at each edge of the opposing pattern,
An arithmetic unit that corrects the position of each edge of the opposing pattern based on the second correction amount;
A circuit design apparatus comprising:

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