JP2004004941A - Method for creating lsi mask data and method for forming lsi pattern - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To surely perform proximity effect correction to LSIs (large-scale integrated circuits) to permit formation of circuit patterns which can be operated while making desired scale down possible. <P>SOLUTION: First, design rules, basic process conditions, etc., are set (SB1). The circuit patterns are created in accordance with the set design rules (SB2) and thereafter whether the created design patterns satisfy the design rules or not is verified (SB3). Next, specifications for creating OPC (optical proximity correction) patterns are set (SB5) and the OPC patterns are created from the respective circuit patterns based on the specifications for forming the OPC patterns (SB6). Whether an OPC effect can be obtained or not is verified (SB10). When the circuit pattern arrangement by which the OPC effect is not obtained is judged to exist (SB11), the design rules are corrected so as not to produce the circuit pattern arrangement by which the OPC effect is not obtained. <P>COPYRIGHT: (C)2004,JPO

Description

(4) The present invention relates to an LSI pattern layout creation method, a mask data creation method, and an LSI pattern formation method using the same, which can surely perform proximity effect correction.

2. Description of the Related Art In recent years, with the miniaturization of the size of a large-scale integrated circuit device (hereinafter, referred to as LSI) using a semiconductor, a reticle or the like is produced by an optical proximity effect (optical proximity effect) in a lithography process which is one of LSI manufacturing processes. The difference between the dimension of the formed design pattern (mask dimension) and the dimension of the transfer pattern formed by transferring the design pattern on the resist (working dimension) has become more significant. As a result, if the dimensions of the design pattern are made to correspond to the mask dimensions as they are, there arises a problem that the processing dimensions do not match the desired design dimensions. This problem has become particularly noticeable in transistors that determine whether or not an LSI operates normally.

Furthermore, LSIs have a generational change that requires discontinuous dimensional changes. For example, the dimension represented by the gate length of the transistor is changed at a reduction rate of about 70% so that the process technology changes from the 0.25 μm generation to the 0.18 μm generation. At this time, not only the gate length but also the cell area for realizing the same circuit is expected to be reduced by the square of 70%, that is, about 50% in area ratio. This reduction is achieved by introducing new exposure tools with shorter wavelength exposure light sources and by improving the processing process.

However, in recent years, it has become impossible to satisfy this reduction rate only by introducing new equipment and improving the processing process. This is because the size variation of the processing dimension with respect to the mask dimension has increased, and the dimensions of the design rules such as the gate protrusion dimension and contact margin set to guarantee the circuit operation can satisfy the 70% reduction rate of the previous generation. Because it is gone.

FIG. 20A shows a design pattern 100A and a processing pattern (transfer pattern) 100B of a general transistor (FET). As shown in FIG. 20A, the design pattern 100A includes a gate pattern 101 serving as a gate layer and an activation layer pattern 102 serving as an activation layer. In the gate pattern 111 of the processing pattern 100B, both end portions 111a of the gate pattern 111 disappear because the gate width is smaller than the design dimension. In this manner, the transistor does not operate normally in a state where the overlap between the activation layer pattern 112 and the gate pattern 111 has disappeared.

In order to prevent this, as shown in a design pattern 100C in FIG. 20B, protrusions 101a protruding from the activation layer pattern 102 in the gate width direction are provided at both ends of the gate pattern 101. The disappearance size at both ends of the gate pattern 101 increases as the size of the line pattern called the gate length 101b decreases. Therefore, the protrusion dimension 101c of the protrusion 101a is not reduced in proportion to the gate length 101b. Therefore, when the gate length 101b is reduced, the protrusion 101c of the gate pattern 101 must be increased in order to guarantee the operation of the transistor. As a result, it has become increasingly difficult for the design rule regarding the protrusion dimension 101c to satisfy the 70% reduction ratio of the previous generation.

Despite such a current situation, the design rule is determined based on the dimensional variation of the processing dimension with respect to the mask dimension, and is defined, for example, at a 70% reduction ratio of the previous generation. Therefore, even for a pattern that cannot completely satisfy the design rule, such as the protrusion dimension 101c of the gate pattern 101, the design rule with a 70% reduction ratio is preferentially adopted in order to reduce the circuit pattern area. .

(4) After that, a cell library is created from the circuit pattern designed according to the design rules. LSI chip data is created from the created cell library, and final process conditions for manufacturing are determined. Based on the final process condition, the amount of change in the processing dimension caused by the proximity effect with respect to the mask dimension is evaluated, and data in which the mask layout is corrected so that the processing dimension does not change with respect to the design dimension is created. At this time, the processing dimensions for each mask dimension are evaluated using an empirical model for processing dimension evaluation taking various conditions into account so that the processing dimensions can be evaluated under the process conditions that have already been determined.

For example, in a circuit pattern, a portion where the processing size is smaller than the mask size has a larger mask pattern size than the design size, and a portion where the processing size is larger than the mask size has a mask pattern size larger than the design size. Is corrected to be thin. Such a mask pattern considering the optical proximity effect is referred to as an optical proximity correction (Optical Proximity Correction: OPC) pattern.

However, the conventional method of creating mask data for an LSI has a problem that an OPC pattern may not be created because an OPC pattern is created for the first time in a mask pattern data creation stage after all circuit patterns are determined. are doing.

For example, as shown in FIG. 20A, when the edge of the gate pattern 101 disappears, the mask size of the protruding portion 101a of the gate pattern 101 is adjusted so that the value of the processing size matches the circuit pattern size. In some cases, the space between the protruding portion 101a and the pattern around the protruding portion 101a may already be the minimum dimension determined from the resolution limit. In such a case, it is impossible to change the protrusion dimension 101c of the gate pattern 101.

Furthermore, the conventional mask data creation method has various problems as described below.

(1) A design rule that does not consider proximity effect correction in advance has a problem that a pattern dimension becomes unnecessarily large.

近 接 As described above, the proximity effect correction for the gate pattern is not limited to the method of extending the protruding portion. For example, if the space between the gates is set relatively large, a hammerhead pattern may be added to the protruding portion of the gate pattern that is not located on the activation layer of the transistor. This hammer head pattern does not extend the protruding portion but expands only the end portion of the protruding portion in the gate length direction, thereby preventing the processing dimension of the gate pattern end from shrinking in the gate width direction. As described above, the proximity effect correction can be realized not only by compensating the variation in the processing dimension from the mask dimension, but also by suppressing the variation. For this reason, simply estimating the dimensional variation without evaluating the dimensional variation due to the OPC pattern and determining the design rule based on the dimensional variation will result in the determination that a dimension larger than necessary is necessary.

(2) Generally, circuit patterns are created based on basic pattern arrangement rules. The process conditions are determined so that variations in the processing dimensions of the created pattern and variations from the mask dimensions are reduced. On the other hand, since the arrangement rule of the OPC pattern is different from the pattern arrangement rule used when determining the process condition, there is a problem that the used process condition is not always optimal with respect to the OPC pattern arrangement rule.

For example, when a circuit pattern is designed so that the space between the patterns is the minimum value, it is assumed that the processing dimension of the space is larger than the design value. In this case, since the size of the space in the OPC pattern is made smaller than the size of the circuit pattern, the minimum space between the OPC patterns becomes smaller than the minimum value of the space between the patterns when the process conditions are first set. ing. Therefore, if the process conditions do not change at all, the processing pattern by the OPC pattern should match the circuit pattern size well. However, in practice, the process conditions fluctuate at the time of manufacturing, so that variations in processing dimensions occur due to the fluctuations. This is because, in general, when the processing size is reduced, the optimum process condition for suppressing the size variation due to the change in the process condition changes. In an extreme case, in order to suppress the dimensional variation, it is necessary to change to a basic exposure method such as a super-resolution or phase shift mask.

(3) Although the final process conditions of the LSI are not determined until immediately before manufacturing, there is a problem that the details of the OPC pattern cannot be determined until the details of the process conditions are determined.

When developing an LSI, the circuit pattern design of the cell library starts more than six months before the LSI manufacturing. However, since the process conditions are determined immediately before the manufacturing, the details of the OPC pattern are determined early. Can not. Therefore, it is difficult to design the circuit pattern of the cell library in consideration of the final OPC pattern in order to solve the problem (1).

(4) The OPC pattern is created using only the difference between the design dimension of the circuit pattern and the processing dimension under predetermined process conditions. It is assumed that the circuit pattern uses a design rule defined by a reduction rate of 70% of the previous generation. However, in some LSIs, it is desirable that the reduction ratios are not the same.

For example, if the LSI has the same function, the chip area may be realized at a reduction rate of 50% of the previous generation. Furthermore, in actual circuit patterns, it is not required that the processing dimensions match the design dimensions at all locations. In some parts, it is required that the dimensions match the design dimensions with high accuracy in the operation of the circuit, and in others, some dimensional fluctuations are allowed. Therefore, designing all the processing dimensions at a reduction rate of 70% of the previous generation imposes unnecessarily difficult conditions on the manufacture of the LSI, and makes it difficult to realize a desired LSI.

The object of the present invention is to solve the above-mentioned conventional problems and to surely perform proximity effect correction for forming a circuit pattern capable of operating while achieving desired miniaturization of an LSI.

In order to achieve the above object, the present invention provides a method of creating a layout of an LSI pattern or a method of creating mask data for an LSI, which is capable of creating a proximity effect correction pattern serving as mask data of the circuit pattern when designing the circuit pattern. And In addition, a design rule for enabling the proximity effect correction pattern is set at the time of designing a circuit pattern.

More specifically, an LSI pattern layout creating method according to the present invention includes a circuit pattern design step of designing a plurality of circuit patterns in an LSI pattern including a plurality of circuit patterns, and an initial step of performing an initial arrangement of the designed circuit patterns. The placement step, by performing the proximity effect correction on the circuit patterns that are arranged adjacent or intersecting with each other among the circuit patterns initially arranged, the proximity effect correction pattern is obtained from the circuit patterns arranged adjacent or intersecting with each other. Proximity effect correction pattern creation step to be created, correction effect determination step to determine whether proximity effect correction is valid, and circuit pattern so that proximity effect correction is valid when it is determined to be invalid Design rule change process to change the design rules to be performed, and initial placement based on the changed design rules And a circuit pattern rearrangement step of rearranging the circuit pattern.

According to the LSI pattern layout creating method of the present invention, after the proximity effect correction pattern is created, the design rule that defines the circuit pattern is changed so that the proximity effect correction is effective. Can be prevented from being able to perform the proximity effect correction on the mask pattern to which is transferred.

In the method for creating a layout of an LSI pattern according to the present invention, the proximity effect correction pattern creation step includes a step of setting a correction pattern creation specification for creating the proximity effect correction pattern. It is preferable to include a step of changing the correction pattern creation specification so that the proximity effect correction becomes effective when it is determined to be invalid.

In the LSI pattern layout creation method according to the present invention, the circuit pattern rearrangement step includes a step of creating a plurality of relocation patterns and selecting a relocation pattern having a small circuit area from the created plurality of relocation patterns. Is preferred.

The LSI pattern layout creating method of the present invention further includes a design rule creating step of creating a design rule for performing a layout so that the proximity effect correction is effective, and the initial arrangement step or the circuit pattern rearrangement step includes: It is preferable to include a step of arranging a plurality of circuit patterns based on a design rule.

In this case, it is preferable that the design rule creating step includes a step of setting a plurality of design rules and selecting a design rule that can reduce a circuit area among the set design rules.

In this case, the method for creating a layout of an LSI pattern according to the present invention includes the steps of setting a correction pattern creation specification for creating a proximity effect correction pattern, and enabling the proximity effect correction in the proximity effect correction pattern to be effective. Preferably, the method further includes a step of creating a correction pattern arrangement rule and a step of determining a design rule by creating a proximity effect correction pattern based on the correction pattern creation specification and the correction pattern arrangement rule.

In this case, the LSI pattern layout creation method of the present invention includes a step of determining whether proximity effect correction is valid for a circuit pattern arranged based on a design rule, and a step of determining whether the proximity effect correction is invalid. In such a case, it is preferable that the method further includes a step of correcting the correction pattern creation specification or the correction pattern arrangement rule so that the proximity effect correction becomes effective.

In the method for creating a layout of an LSI pattern according to the present invention, the correction effect determination step performs a process simulation including at least one of a lithography step and an etching step to determine whether a predicted value of a processing dimension satisfies a predetermined value. Is preferably determined.

In this case, in the lithography step in the process simulation, it is preferable to determine whether or not the predicted value of the processing dimension when the exposure amount or the focus position changes beyond the process allowance satisfies a predetermined value.

In this case, it is preferable that the determination of the process simulation includes a step of determining the dimension of the transistor in the gate length direction.

In this case, it is preferable that the judgment of the process simulation includes a step of judging a protrusion dimension of the gate of the transistor from the active layer in the gate width direction.

A first method for forming an LSI pattern according to the present invention includes a circuit pattern design step of designing a plurality of circuit patterns in an LSI pattern including a plurality of circuit patterns, and an initial arrangement step of performing an initial arrangement of the designed circuit pattern. And performing the proximity effect correction on the circuit patterns arranged adjacent or intersecting with each other among the circuit patterns initially arranged, thereby creating the proximity effect correction pattern from the circuit patterns arranged adjacent or intersecting with each other. A proximity effect correction pattern creating step, a correction effect determination step of determining whether the proximity effect correction is valid under predetermined process conditions, and a circuit for enabling the proximity effect correction to be enabled when it is determined to be invalid. Based on the design rule change process of changing the design rule that defines the pattern and the changed design rule, A circuit pattern rearrangement step of rearranging the arranged circuit pattern; a mask manufacturing step of manufacturing a mask using the proximity effect correction pattern; and a mask manufacturing step of using the manufactured mask on the semiconductor substrate under predetermined process conditions. And a pattern forming step of forming a plurality of circuit patterns.

According to the first method for forming an LSI pattern, a circuit pattern (processed pattern) is formed on a resist film, for example, by a mask manufactured by using the LSI pattern layout creation method of the present invention, so that the operation is reliably performed. The circuit pattern of the circuit to be performed can be obtained.

The first method of forming an LSI pattern includes a step of evaluating an expected value of a processing yield when a manufactured mask is used under predetermined process conditions after a mask manufacturing step, and a step of estimating the expected value to reach a target value. If not, it is preferable that the method further includes a step of resetting predetermined process conditions so that the expected value reaches the target value, and repeating the process from the circuit pattern designing step again.

A first method of creating mask data for LSI according to the present invention includes a first correction pattern group that does not change a pattern shape of a plurality of circuit patterns included in an LSI according to a change in process conditions; A correction pattern group classifying step of classifying a plurality of circuit patterns into a second correction pattern group that changes a pattern shape in accordance with the pattern shape, and a cell-level proximity effect correction pattern from the first correction pattern group when designing a plurality of circuit patterns A cell-level correction pattern data generating step of generating data; and a chip-level correction pattern data generating step of generating chip-level proximity effect correction pattern data from a second correction pattern group when generating chip data from a plurality of circuit patterns. Process.

According to the first method of creating mask data for LSI, a plurality of circuit patterns included in an LSI are divided into a first correction pattern group whose pattern shape is not changed according to a change in process conditions, and a plurality of circuit patterns included in the LSI in accordance with changes in process conditions. Since the first correction pattern group is classified into the second correction pattern group whose pattern shape is changed, the first correction pattern group can be registered as a library even if the proximity effect correction is performed in advance. Further, since the first correction pattern group greatly affects the area of the cell, the proximity effect correction pattern at the cell level can be determined at the cell design stage. It is possible to reliably evaluate the cell area of the proximity effect correction pattern that is created. Furthermore, since the proximity effect correction at the cell level can be performed on a cell-by-cell basis, it is also possible to determine the specifications for creating the proximity effect correction pattern on a cell-by-cell or block-by-block basis.

In the first method for creating LSI mask data, the step of creating cell level correction pattern data includes the step of determining whether proximity effect correction in the created cell level proximity effect correction pattern data is valid, Is determined, the proximity effect correction pattern data at the cell level or the circuit pattern corresponding to the proximity effect correction pattern data is corrected so that the proximity effect correction becomes effective. It is preferable to include a step of determining again and a step of registering the cell-level proximity effect correction pattern data in a cell library when the pattern is determined to be valid.

According to a second method of generating mask data for LSI according to the present invention, a plurality of circuit patterns included in an LSI are corrected in a first correction pattern group that does not change a pattern shape in accordance with a change in process conditions; And a step of classifying the first correction pattern group into a cell-level correction pattern generation specification for generating a cell-level proximity effect correction pattern for the first correction pattern group. Setting, designing a plurality of circuit patterns, and determining the effectiveness of the proximity effect correction in the cell level proximity effect correction pattern created by the cell level correction pattern creation specification for the first correction pattern group. A step of determining the presence or absence, and when the proximity effect correction is determined to be invalid, the proximity effect correction is determined to be invalid so that the proximity effect correction is valid. After correcting the circuit pattern, re-determining the validity of the proximity effect correction, and, when the proximity effect correction is determined to be valid, registering the circuit pattern belonging to the first correction pattern group in the cell library. A step of registering a circuit pattern belonging to the second correction pattern group in the cell library; a step of generating chip-level pattern data from the circuit pattern registered in the cell library; Setting a chip-level correction pattern creation specification for creating a chip-level proximity effect correction pattern, and, based on the cell-level correction pattern creation specification, converting a circuit pattern belonging to the first correction pattern group to a cell-level correction pattern. Based on the process of creating proximity effect correction pattern data and the chip level correction pattern creation specification And a step of creating a proximity effect correction pattern data of the chip-level from the circuit pattern belonging to the second correction pattern group.

According to the second method of creating mask data for LSI, a plurality of circuit patterns included in an LSI are divided into a first correction pattern group that does not change the pattern shape in accordance with a change in process conditions, and a plurality of circuit patterns included in the LSI in accordance with changes in process conditions. If the proximity effect correction pattern set with the cell level correction pattern creation specification is determined to be valid, the original pattern of the proximity effect correction pattern determined to be valid is classified into a second correction pattern group for changing the pattern shape. Register the circuit pattern in the cell library. Thereafter, in a step of creating mask data, cell-level proximity effect correction pattern data and chip-level proximity effect correction pattern data are created from the cell library. Therefore, it is not necessary to create the proximity effect correction pattern data having an extremely large data amount even at the time of creating the mask data, so that management of a large amount of data becomes easy.

A third method of generating mask data for LSI according to the present invention includes a first correction pattern group that does not change a pattern shape of a plurality of circuit patterns included in an LSI according to a change in process conditions; And a step of classifying the first correction pattern group into a cell-level correction pattern generation specification for generating a cell-level proximity effect correction pattern for the first correction pattern group. Setting, designing a plurality of circuit patterns, and determining the effectiveness of the proximity effect correction in the cell level proximity effect correction pattern created by the cell level correction pattern creation specification for the first correction pattern group. A step of determining the presence or absence, and when the proximity effect correction is determined to be invalid, the proximity effect correction is determined to be invalid so that the proximity effect correction is valid. After correcting the circuit pattern or the cell-level correction pattern creation specification of the circuit pattern, re-determining the validity of the proximity effect correction. If the proximity effect correction is determined to be valid, the first correction pattern Registering the circuit pattern belonging to the group and the cell level correction pattern creation specification corresponding to the circuit pattern in the cell library, and registering the circuit pattern belonging to the second correction pattern group in the cell library; Generating chip-level pattern data from the obtained circuit patterns, and generating cell-level proximity effect correction pattern data from the circuit patterns belonging to the first correction pattern group based on the cell-level correction pattern generation specifications. , A second correction pattern based on a predetermined chip level correction pattern creation specification. From the circuit patterns belonging to emission group and a step of creating a proximity effect correction pattern data of the chip level.

In the first to third LSI mask data creation methods, the step of determining the validity of the proximity effect correction is performed when a plurality of circuit pattern layouts for which the proximity effect correction is determined to be valid exist. It is preferable to include a step of selecting a layout in which the circuit area is equal to or smaller than a predetermined value.

In this case, it is preferable that the cell-level proximity effect correction pattern data include a serif pattern, a hammerhead pattern, or an insection pattern.

According to a fourth method for generating LSI mask data according to the present invention, a first correction pattern group in which a circuit pattern is determined by a pattern arrangement over a plurality of layers, among a plurality of circuit patterns included in an LSI, A step of classifying a correction pattern group into a second correction pattern group determined by a pattern arrangement in one layer; and a step of classifying a plurality of circuit patterns from the proximity of the inter-layer from the first correction pattern group. An inter-layer correction pattern data generation step of generating effect correction pattern data, and an intra-layer correction of generating intra-layer proximity effect correction pattern data from a second correction pattern group when generating chip data from a plurality of circuit patterns. Pattern data creating step.

According to the fourth LSI mask data creation method, a plurality of circuit patterns included in an LSI are divided into a first correction pattern group in which circuit patterns are determined by a pattern arrangement over a plurality of layers, and a circuit pattern in one layer. The first correction pattern group can be registered as a library even if the first correction pattern group has been subjected to the proximity effect correction in advance, since it is classified into the second correction pattern group determined by the pattern arrangement. Further, since the first correction pattern group greatly affects the area of the cell, the proximity effect correction pattern at the cell level can be determined at the cell design stage. It is possible to reliably evaluate the cell area of the proximity effect correction pattern that is created. Furthermore, since the proximity effect correction at the cell level can be performed on a cell-by-cell basis, it is also possible to determine the specifications for creating the proximity effect correction pattern on a cell-by-cell or block-by-block basis.

In the fourth method of generating mask data for LSI, the step of generating interlayer correction pattern data includes the step of determining whether proximity effect correction in the generated proximity effect correction pattern data of the interlayer is valid, When it is determined that the proximity effect correction is effective, the proximity effect correction pattern data of the interlayer or the circuit pattern corresponding to the proximity effect correction pattern data is corrected so that the proximity effect correction becomes effective. It is preferable to include a step of determining again and a step of registering the proximity effect correction pattern data of the interlayer in the cell library when it is determined to be valid.

According to a fifth LSI mask data generation method according to the present invention, a first correction pattern group in which a circuit pattern is determined by a pattern arrangement over a plurality of layers among a plurality of circuit patterns included in an LSI; A step of classifying into a second correction pattern group determined by a pattern arrangement in one layer, and an inter-layer correction pattern for creating an inter-layer proximity effect correction pattern for the first correction pattern group A step of setting creation specifications; a step of designing a plurality of circuit patterns; and a proximity effect correction in the proximity effect correction pattern of the interlayer, which is created by the interlayer correction pattern generation specification for the first correction pattern group. Determining whether or not the proximity effect correction is valid; and determining that the proximity effect correction is valid when the proximity effect correction is determined to be invalid. Thus, after the circuit pattern determined to be invalid is corrected, the validity of the proximity effect correction is determined again, and when the proximity effect correction is determined to be valid, the pattern belongs to the first correction pattern group. Registering the circuit patterns in the cell library and registering the circuit patterns belonging to the second correction pattern group in the cell library; and creating chip-level pattern data from the circuit patterns registered in the cell library; Setting an intra-layer correction pattern creation specification for creating an intra-layer proximity effect correction pattern for the second correction pattern group; and a first correction pattern group based on the inter-layer correction pattern creation specification. Generating proximity effect correction pattern data for an interlayer from circuit patterns belonging to Based on ya correction pattern creation specifications, and a step of creating a proximity effect correction pattern data of the intra-layer from the circuit pattern belonging to the second correction pattern group.

According to the fifth LSI mask data creation method, a plurality of circuit patterns included in the LSI are divided into a first correction pattern group determined by a pattern arrangement of a plurality of layers, and a circuit pattern in one layer. And a second correction pattern group determined by the pattern arrangement, and when it is determined that the proximity effect correction pattern in which the inter-layer correction pattern is set is valid, the original proximity effect correction pattern determined to be valid Register the circuit pattern in the cell library. Thereafter, in the step of creating mask data, the proximity effect correction pattern data of the inter layer and the proximity effect correction pattern data of the intra layer are created from the cell library. Therefore, it is not necessary to create the proximity effect correction pattern data having an extremely large data amount even at the time of creating the mask data, so that management of a large amount of data becomes easy.

According to a sixth LSI mask data generation method according to the present invention, a first correction pattern group in which a circuit pattern is determined by a pattern arrangement over a plurality of layers, among a plurality of circuit patterns included in the LSI, A step of classifying into a second correction pattern group determined by a pattern arrangement in one layer, and an inter-layer correction pattern for creating an inter-layer proximity effect correction pattern for the first correction pattern group A step of setting creation specifications; a step of designing a plurality of circuit patterns; and a proximity effect correction in the proximity effect correction pattern of the interlayer, which is created by the interlayer correction pattern generation specification for the first correction pattern group. Determining whether or not the proximity effect correction is valid; and determining that the proximity effect correction is valid when the proximity effect correction is determined to be invalid. As described above, after correcting the circuit pattern determined to be invalid or the specification for creating an interlayer correction pattern of the circuit pattern, a step of again determining the validity of the proximity effect correction and the step of determining that the proximity effect correction is valid In this case, the circuit patterns belonging to the first correction pattern group and the specifications for creating an interlayer correction pattern corresponding to the circuit patterns are registered in the cell library, and the circuit patterns belonging to the second correction pattern group are registered in the cell library. A step of creating chip-level pattern data from the circuit patterns registered in the cell library; and a step of creating an interlayer proximity effect from the circuit patterns belonging to the first correction pattern group based on the interlayer correction pattern creation specification. A step of creating correction pattern data and a predetermined intra-layer correction pattern Based on the formation specification, and a step of creating a proximity effect correction pattern data of the intra-layer from the circuit pattern belonging to the second correction pattern group.

In the fourth to sixth LSI mask data creation methods, the step of determining the validity of the proximity effect correction is performed when a plurality of circuit pattern layouts for which the proximity effect correction is determined to be valid exist. It is preferable to include a step of selecting a layout in which the circuit area is equal to or smaller than a predetermined value.

In this case, it is preferable that the specification for creating an interlayer correction pattern is determined by an arrangement rule that defines one layer including the gate of the transistor and another layer including the active region.

In this case, the inter-layer correction pattern creation specification defines an arrangement that defines a first wiring layer and a layer including a contact that electrically connects the second wiring layer different from the first wiring layer. Preferably, it is determined by rules.

In this case, the process of determining the effectiveness of the proximity effect correction includes performing a process simulation including at least one of a lithography process and an etching process to determine whether a predicted value of a processing dimension satisfies a predetermined value. Is preferably determined.

In the lithography step in the process simulation in this case, it is preferable to determine whether or not the predicted value of the processing dimension when the exposure amount or the focus position changes beyond the process allowance satisfies a predetermined value.

In this case, it is preferable that the determination of the process simulation includes a step of determining the dimension of the transistor in the gate length direction.

In this case, it is preferable that the judgment of the process simulation includes a step of judging a protrusion of the gate of the transistor from the active layer in the gate width direction.

In the second to seventh LSI pattern forming methods according to the present invention, a mask is manufactured by using any of the first to sixth LSI mask data creating methods according to the present invention, and the manufactured mask is used as a mask. Forming a plurality of circuit patterns on a semiconductor substrate using the method.

According to the LSI pattern layout creating method according to the present invention, after the proximity effect correction pattern is created, the design rule that defines the circuit pattern is changed so that the proximity effect correction is effective. By using a design pattern created by the following design rule and a mask pattern created by the design pattern, the proximity effect correction can be surely performed.

According to the method of generating LSI mask data according to the present invention, a circuit pattern that greatly affects the area of a cell is a cell-level proximity effect correction pattern or an interlayer proximity effect correction pattern. The proximity effect correction pattern can be determined. For this reason, the cell area of the proximity effect correction pattern that is finally created can be reliably evaluated.

(First Embodiment)
A first embodiment according to the present invention will be described with reference to the drawings.

In the first embodiment, when manufacturing an LSI, a design rule including a condition for generating an OPC pattern in which a proximity effect correction (OPC) effect is effective is determined, and a circuit pattern of the circuit pattern is determined using the determined design rule. Design and creation of mask pattern data are performed.

Further, an OPC pattern is created from a circuit pattern according to a design rule in which the OPC effect is effective, and an optimum basic process condition is determined based on the created OPC pattern. Note that the OPC effect in this specification refers to a circuit transferred to a region having an occupied area substantially equal to the occupied area (circuit area) of the original circuit pattern by the created OPC pattern. An effect that can realize a processing pattern.

FIG. 1 shows a creation flow of an LSI mask data creation method according to the first embodiment of the present invention. As shown in FIG. 1, first, in step SA1, a design rule for designing a circuit pattern of a circuit to be included in an LSI, basic process conditions, a creation specification for creating an OPC pattern from a circuit pattern, and an OPC pattern arrangement rule are respectively determined. I do. Here, the basic process conditions are, for example, in the case of a lithography step, various conditions such as a wavelength of an exposure light source, a degree of interference of exposure light, a focus position, an exposure amount, and a numerical aperture of a lens. Including selection. For example, whether or not to use an annular exposure method, whether to use a phase shift mask, and the like. The design rule is a rule that must be observed when designing a circuit pattern in order to obtain a circuit that actually operates. The OPC pattern arrangement rule is a rule to be satisfied by the OPC pattern so that the transfer pattern exposed on the wafer becomes a processable pattern. Therefore, this rule is a design rule in the OPC pattern, and includes a rule that defines a basic pattern arrangement such as a minimum line width and a minimum space of the OPC pattern. Thus, the design rule that guarantees the processing pattern can be applied to the OPC pattern serving as the mask pattern, and the design rule can be set for the circuit pattern on the assumption that the OPC pattern is created. As a result, it is possible to select the optimum condition even after the OPC pattern is determined for the basic process condition.

(4) Next, in step SA2, a circuit pattern is created for each cell which is a basic circuit constituting the LSI.

Next, in step SA3, it is verified whether the circuit pattern created in step SA2 satisfies the design rule. If the circuit pattern does not satisfy the design rule, the process proceeds to step SA4, where a portion of the circuit pattern that does not satisfy the design rule is corrected, and the process is repeated from step SA2. If the verified circuit pattern satisfies the design rule, the process proceeds to step SA5.

Next, in step SA5, the circuit pattern created for each cell is registered in the cell library, thereby accumulating the basic cells constituting the LSI chip pattern.

Next, in step SA6, circuit pattern data necessary for the LSI is extracted from the cell library, and LSI chip data is created using the extracted circuit pattern data.

(4) Next, in step SA7, final process conditions for manufacturing LSI chip data are determined. At this time, if the OPC pattern placement rule needs to be changed due to the final process condition, the OPC pattern placement rule is changed. This is for the following reason. That is, when developing an LSI, it generally takes one year or more from the determination of a design rule to the creation of a required cell library, whereas the period required to create LSI chip data from the cell library is longer. Is at most a few months. For this reason, despite the fact that the optimum process conditions have been determined for the design rules, the introduction of new resist materials and new equipment at the time when the cell library is completed and the LSI chip data is created The determined process conditions may not always be optimal. For this reason, in order to further improve the productivity, it is desirable to finally determine the process conditions at the stage of creating the LSI chip data.

Next, in step SA8, a required OPC pattern is created from the LSI chip data based on the OPC pattern creation specification. Specifically, the amount of change in the processing dimension caused by the optical proximity effect with respect to the mask dimension is evaluated under the final process conditions, and data in which the mask layout is corrected so that the processing dimension does not change with respect to the design dimension is created.

Next, in step SA9, it is verified whether the OPC pattern created in step SA8 satisfies the OPC pattern arrangement rule. If the OPC pattern placement rule is not satisfied, the process proceeds to step SA10, where the portion of the OPC pattern that does not satisfy the OPC pattern placement rule is corrected, and the process is repeated from step SA8. If the verified OPC pattern satisfies the OPC pattern arrangement rule, the flow advances to the next Step SA11 to create mask pattern data using the OPC pattern.

A mask or reticle is manufactured using the mask pattern data created as described above, and an operable circuit pattern is transferred to, for example, a resist film formed on a semiconductor substrate using the manufactured mask or reticle. can do.

As described above, in the conventional LSI development, the design rule is determined in the upstream process, and the OPC pattern is determined in the downstream process. Changing the design rules was virtually impossible. However, according to the present embodiment, since the design rule can be changed so that the OPC pattern is effective when the design rule is determined, the circuit pattern and the mask data based on the changed design rule reliably exhibit the OPC effect. it can.

Hereinafter, the details of the processing in step SA1 shown in FIG. 1 will be described with reference to the drawings.

FIG. 2 shows an example of a procedure for determining a basic process condition and a design rule applied to a cell library in a method for creating an LSI pattern layout according to the present embodiment. As shown in FIG. 2, first, in step SB1, initial settings of a design rule, basic process conditions, and an OPC pattern arrangement rule determined by the basic process conditions are performed. These initial values are provided so as to be some typical samples of the cell library created in step SA6 shown in FIG.

(4) Next, in step SB2, a circuit pattern is created based on the set design rules.

Next, in step SB3, it is verified whether the created circuit pattern satisfies the design rule. If the circuit pattern does not satisfy the design rule, the process proceeds to step SB4, where the portion of the circuit pattern that does not satisfy the design rule is corrected and the process is repeated from step SB2.

(5) Next, in step SB5, an OPC pattern creation specification that defines the specification for creating a required OPC pattern from the circuit pattern is set. The OPC pattern creation specification may be rule-based or model-based (= simulation-based), and a known method may be used. That is, as long as the circuit patterns are the same, any method that can create the same OPC pattern may be used. The rule base is a method of defining OPC pattern creation rules for each pattern category in a circuit pattern, and creating an OPC pattern according to the defined creation rules. The model base is a method of calculating the dimensions of a mask pattern using a model formula for simulating the processing dimensions so that the processing patterns match the circuit patterns.

Next, in step SB6, an OPC pattern is created from each circuit pattern based on the set OPC pattern creation specifications.

Here, specific examples of the circuit pattern and the OPC pattern will be described with reference to the drawings.

FIG. 3 shows an example of a circuit pattern. As shown in FIG. 3, the circuit pattern showing the transistor circuit has a rectangular activation layer pattern 11 having a cutout on one side of a long side. On the activation layer pattern 11, a first gate pattern 12 that crosses a long side of the activation layer pattern 11 and straddles a region that does not include the cutout portion, and is parallel to the first gate pattern 12, respectively. A second gate pattern 13 and a third gate pattern 14 are arranged so as to straddle the notch of the activation layer pattern 11, respectively, and are arranged in parallel with the long side having the notch in the activation layer pattern 11 at an interval. An extended wiring pattern 15 is arranged.

The third gate pattern 14 includes a transistor portion 14a functioning as a gate electrode of the transistor, and a gate wiring portion 14b having a bent portion that bends and extends on a peripheral region (isolation region) of the activation layer pattern 11. ing.

FIG. 4 shows an example of an OPC pattern created based on the circuit pattern shown in FIG. Here, as shown in FIG. 4, as the OPC pattern creation specification, for example, a hammer head is provided at an end of the first gate pattern 12, the second gate pattern 13, and the third gate pattern 14 on the wiring pattern 15 side. The patterns 12h, 13h, and 14h are added, and the width (gate length) of a portion located on the activation layer pattern 11 is changed according to the distance between adjacent gate patterns.

Next, in step SB7, it is verified whether or not the OPC pattern created in step SB6 shown in FIG. 2 satisfies the OPC pattern arrangement rule set in step SB1. The verification target area 17 shown in FIG. 4 shows an example in which the interval between the patterns is smaller than the minimum space width in the OPC pattern arrangement rule. As described above, when the OPC pattern arrangement rule is not satisfied, the process proceeds to step SB8 shown in FIG. 2, and the OPC pattern creation specification is modified so that the verification target area 17 satisfies the OPC pattern arrangement rule in step SB8. Thereafter, the process is repeated from step SB8. In order to eliminate the violation of the rule of the verification target area 17 shown in FIG. 4, a specification for changing the shape of each OPC pattern 12 to 14 according to the distance between mutually adjacent patterns such as the hammer head patterns 12h to 14h is added. Is required. FIG. 5 shows an OPC pattern in which an OPC pattern is re-created based on the OPC pattern creation specification whose specification has been changed. As shown in the verification target area 17 in FIG. 5, the end of the second gate pattern 13 on the wiring pattern 15 side is obtained by erasing the hammer head pattern 13h, and the end is replaced by the first and third gates. The patterns 12 and 14 are extended so as to be aligned with the ends of the respective hammer head patterns 12h and 14h.

Next, after the placement verification of the OPC pattern is completed, in SB9 shown in FIG. 2, CD verification is performed to determine whether or not the dimension of the processed pattern obtained from the OPC pattern, that is, the critical dimension matches the circuit pattern. Perform This is a step of confirming whether an effective OPC pattern can be created. Here, it is difficult to verify whether or not the dimensions of the circuit pattern match the dimensions of the processing pattern using an actual circuit. Therefore, a simulation method that is excellent in reproducibility of an actual circuit is used. However, the CD verification does not need to be performed for all portions of one circuit pattern, but is performed for a portion such as a gate length in a gate pattern, in which a processing dimension needs to match a design dimension with high accuracy. . If it is determined that the CD verification does not match, the process proceeds to step SB8, where the OPC pattern creation specification is corrected so that the mismatching portion in the OPC pattern is eliminated, and the process is repeated again from step SB5.

Next, in step SB10, it is verified whether or not the OPC effect appears for the OPC pattern for which the CD verification has been completed. Here, it is verified whether or not the processing pattern dimension satisfies the condition for operating the circuit normally, not whether or not the processing pattern dimension exactly matches the design pattern dimension. The verification method verifies, for example, a processing pattern of a protruding portion of a gate of a circuit pattern by a simulation method having excellent reproducibility similarly to step SB9. As a specific example, whether or not the end portion of the gate pattern satisfies the dimension on the circuit pattern, the protrusion of the gate pattern disappears in the overlapping region of the activation layer pattern and the gate pattern in the processing pattern. Then, it is checked whether the activation layer pattern is exposed from the overlap region. Furthermore, even in the case where the processing pattern of the protruding portion of the gate pattern is longer than a predetermined dimension, unless the protruding portion that is longer short-circuits with another pattern and hinders the operation of the circuit. No problem. However, in the verification of the OPC effect, when a failure occurs, the circuit does not operate. Therefore, in consideration of the variation of the process conditions in the manufacturing process, not only the predetermined process conditions, but also the margin of each process is included in the process conditions. It is necessary to verify that there is no problem including the above.

FIG. 6 shows an example of a simulation result of a processing pattern in the verification of the OPC effect in step SB10. As shown in FIG. 6, the corners of each corner and the notch in the activation layer pattern 11A are rounded, and the protruding portion of the second gate pattern 13A on the side of the wiring pattern 15A has almost disappeared. From this simulation result, as shown in the first verification target region 17A, the source region and the drain region in the active layer pattern 11A of the transistor are substantially short-circuited because the gate width of the second gate pattern 13A is reduced. And normal operation cannot be obtained. Further, as shown in the second verification target area 18A, the shape of the bent portion of the third gate pattern 14A becomes dull, so that the gate length locally increases near the side of the activation layer pattern 11A. A predetermined operation cannot be obtained. However, here, an example in which the process conditions have a margin is not shown. In practice, a process pattern is simulated after giving a predetermined margin to the process conditions.

As shown in FIG. 6, when it is determined that the OPC effect cannot be obtained, that is, when it is determined that the normal operation of the circuit cannot be expected, the process proceeds to step SB11 shown in FIG. It is checked whether there is any circuit pattern arrangement that cannot be obtained.

(4) If it is determined in step SB11 that there is no pattern arrangement in which the OPC effect cannot be obtained, the process is repeated from step SB8 again, and the OPC pattern creation specification is corrected so as to obtain the OPC effect. On the other hand, when it is determined in step SB11 that there is a circuit pattern arrangement in which the OPC effect cannot be obtained, the process proceeds to step SB12, and the design rule is corrected so that the circuit pattern arrangement in which the OPC effect cannot be obtained does not occur. Thereafter, the process is repeated from step SB4.

FIG. 7 shows the result of correcting the pattern arrangement in which the OPC effect cannot be obtained in step SB4. Here, as a modified example of the design rule, a rule of providing a predetermined interval between the gate pattern and the activation layer pattern is added. As a result, the portion of the third gate pattern 14B extending in parallel with the long side of the activation layer pattern 11B in the gate wiring portion 14b has an interval larger than the initial value between the long side of the activation layer pattern 11B. Provided. Similarly, the end of the notch between the first gate pattern 12 and the second gate pattern 13 in the activation layer pattern 11B is larger than the initial value between the notch and the side surface of the second gate pattern 13. An interval is provided. In FIG. 7, the contours of the third gate pattern 14 and the activation layer pattern 11 before correction are indicated by broken lines.

8 shows an OPC pattern obtained based on the circuit pattern shown in FIG. 7, and FIG. 9 shows a processed pattern showing a simulation result obtained based on the OPC pattern shown in FIG. As shown in FIG. 9, the protruding portion at the end of the second gate pattern 13A on the wiring pattern 15A side is extended to such an extent that a predetermined gate length is secured. Further, the gate length of the transistor portion 14a in the third gate pattern 14C is substantially constant. As described above, by changing the design rule by verifying the OPC effect, it is possible to create a circuit pattern that can reliably obtain the OPC effect without generating a rework man-hour.

Next, in step SB13 shown in FIG. 2, the circuit area (cell area) of the circuit pattern that can obtain the OPC effect and the expected value of the yield of normal operation of the circuit in the processed pattern obtained from the OPC pattern of the circuit pattern To evaluate. As a method of evaluating the expected value of the yield, for example, a method of evaluating the normal operation probability of a transistor in a cell as described in JP-A-10-284608 or JP-A-11-121345 may be used. . This is because the operation probability of normal operation of the transistor can be regarded as an expected value of the yield of the circuit pattern. More specifically, a processing dimension that enables normal operation of the transistor is expressed as a response surface function using a process condition or a dimension of a mask pattern representing the transistor as a variable. Furthermore, this method is a method of calculating the probability that a transistor will have a working dimension in which a transistor can normally operate in a manufacturing process by substituting a variation distribution of process conditions predicted in the manufacturing process into this response phase function. Generally, the reduction of the circuit pattern area and the expected value of the yield at which the circuit can operate normally have a conflicting relationship.

If it is determined in step SB13 that the pattern area of the circuit is larger than the design value, the flow advances to step SB14 to change the design rule and the corresponding OPC pattern placement rule so that a smaller circuit pattern can be obtained. Repeat from step SB1. Also, in step SB13, when it is determined that the expected value of the yield of the normal operation is lower than the target value, the process proceeds to step SB14 to improve the basic process conditions and to improve the design rule and the OPC pattern placement rule related thereto. The size is changed to be enlarged, and the process is repeated from step SB1.

On the other hand, if both the circuit pattern area and the expected value of the yield satisfy the target values, the process proceeds to step SB15, where the design rule, the basic process condition, the OPC pattern arrangement rule, the OPC pattern creation specification, and the circuit pattern data are respectively finalized. It will be decided to.

As described above, according to the present embodiment, by creating a plurality of circuits (cells) serving as typical samples to be registered as a cell library, it is possible to achieve a circuit area targeted by the current generation of the cell library. Thus, it is possible to determine basic process conditions and design rules for which an expected value of normal operation is secured for the created circuit. Needless to say, as the number of samples increases, more optimal design rules, OPC pattern arrangement rules, and OPC pattern creation specifications can be determined.

効果 Hereinafter, the effects of the present embodiment will be listed.

(A) In order to determine a design rule that satisfies the condition for obtaining the OPC effect and to design a circuit pattern based on the determined design rule, a necessary OPC pattern is created at the stage of creating mask pattern data in the final process. You can't do it.

(B) For a circuit pattern belonging to a plurality of typical categories, the final design rule is determined by reflecting the condition of the design rule for which the OPC effect is effective in the design rule used for circuit pattern design. It is possible to build highly design rules.

(C) When determining the design rule, the predetermined cell area is set to be half the area of the circuit included in the previous generation LSI, so that the predetermined cell area is achieved as a condition for obtaining the OPC effect. , The design rule does not become unnecessarily large.

(D) Since the design rule is reduced not based on the size of the processing pattern based on each circuit pattern defined by the design rule but on the basis of the reduction of the circuit area, a pattern that is more difficult to realize than necessary is designed. Is avoided.

(E) The basic process conditions are assumed to be the OPC pattern to be created and are reset so as to improve the productivity as shown in step SB14, so that the basic process conditions are inappropriate for the final process conditions. And never.

(Second embodiment)
Hereinafter, a second embodiment of the present invention will be described with reference to the drawings. Also in the present embodiment, similarly to the first embodiment, a design rule including conditions for generating a necessary OPC pattern is determined, and a circuit pattern is designed and mask pattern data is generated based on the determined design rule. Do. In particular, in the present embodiment, since the OPC effect can be individually verified at the time of designing each cell (basic circuit), the cell area can be made smaller for each cell.

FIGS. 10 and 11 show a processing flow of an LSI mask data creation method according to the second embodiment of the present invention.

First, in step SC1 shown in FIG. 10, design rules, basic process conditions, and OPC pattern arrangement rules are determined. Among them, the design rule and the basic process condition are determined by the same method as in step SA1 shown in FIG. On the other hand, the OPC pattern placement rules classify the OPC patterns into a first category that does not need to be sensitively changed according to a change in process conditions, and a second category that needs to be changed sensitively.

Here, specific examples of the first and second categories will be described with reference to FIGS. 12 (a) and 12 (b). FIG. 12A shows a first pattern 21A including a wiring portion 21a and a protruding portion 21b which protrudes relatively largely from one side of the wiring portion 21a, and a wiring pattern 22a and one side of the wiring portion 22a. A second pattern 22A composed of a relatively small protruding portion 22b and a second pattern 22A are arranged such that the wiring portions 21a and 22a are parallel and spaced apart from each other. In this case, for example, the OPC pattern for changing the processing size of the wiring width in each of the wiring portions 21a and 22a needs to be changed sensitively to a change in the process condition, and is therefore classified into the second category. Although not shown, as another example, the processing dimension of the gate length in the gate pattern is a pattern that must exactly match the design dimension, and is classified into the second category.

On the other hand, as shown in FIG. 12B, the hammer head pattern 21c provided at the end of the protruding portion 21b in the first OPC pattern 21B created based on the first pattern 21A, and the wiring portion 21a The insection pattern 21d, which is removed so that the connection with the protruding portion 21b is narrowed, does not need to be changed sensitively to a change in process conditions, and is classified into the first category. Similarly, serif patterns 22c provided at both corners of the end of the protruding portion 22b in the second OPC pattern 22B created based on the second pattern 22A are also classified into the first category. Here, the hammer head pattern 21c and the serif pattern 22c prevent the edges of the original pattern from disappearing, and the in-section pattern 21d prevents the corners of the connecting portions of the patterns from being rounded.

In general, an OPC pattern that is important in determining the circuit pattern area (cell area), that is, an OPC pattern that exhibits an OPC effect with a reduced cell area, belongs to the first category. Therefore, the OPC pattern belonging to the first category is referred to as a cell-level OPC pattern because the proximity effect correction can be performed even at the stage of designing a cell library in which the final process conditions have not been determined. On the other hand, for the second category in which the OPC pattern cannot be created unless the final process conditions are determined, the proximity effect correction is performed after the LSI chip data is completed and after the final process conditions are determined. Let's call it a pattern.

Next, in step SC2 shown in FIG. 10, a circuit pattern is created for each cell without depending on the category based on the design rule determined in step SC1.

Next, in step SC3, it is verified whether the created circuit pattern satisfies the design rule. If the circuit pattern does not satisfy the design rule, the process proceeds to step SC4, in which a portion of the circuit pattern that does not satisfy the design rule is corrected, and the process is repeated from step SC2. If the circuit pattern data satisfies the design rule, the process proceeds to step SC5.

Next, in step SC5, a cell-level OPC pattern is created from the circuit patterns belonging to the first category among the created circuit patterns. The rule-based method is preferably used for creating the cell-level OPC pattern. That is, a rule for creating a cell-level OPC pattern is created for each circuit pattern, and a cell-level OPC pattern is created according to the created rules. Here, in order to create an OPC pattern for obtaining the OPC effect, not a design of the OPC pattern for matching the processing dimensions and the circuit pattern dimensions, but a processing pattern for operating the circuit pattern normally in its area is realized. It is necessary to create an optimal OPC pattern so that it can be performed. For this reason, as for the processing dimensions of the portion that does not cause a defect in the circuit operation, an OPC pattern that improves the expected value of the circuit operation yield may be created even if the circuit pattern dimension is ignored. Therefore, in order to realize this, a method called a rule base that can define a rule that can create an OPC pattern for each circuit pattern is suitable as a model for creating an OPC pattern. This is because the model base realizes the processing dimensions appearing in the circuit pattern as they are.

Next, in step SC6, it is verified whether or not the created cell-level OPC pattern satisfies the OPC pattern arrangement rule. If the cell-level OPC pattern does not satisfy the OPC pattern arrangement rule, the process proceeds to step SC7. In step SC7, a portion of the cell-level OPC pattern that does not satisfy the OPC pattern arrangement rule is corrected, and the process is repeated from step SC5.

Next, in step SC8, it is verified whether the OPC effect is obtained for the cell-level OPC pattern satisfying the OPC pattern arrangement rule. The verification method is the same as step SB10 of the first embodiment, and is performed by a simulation method that is excellent in the reproducibility of an actual circuit. As a specific example, the protrusion of the gate pattern disappears in the overlap region between the activation layer pattern and the gate pattern in the processed pattern regardless of whether the end of the gate pattern satisfies the dimensions on the circuit pattern. It is checked whether or not the activation layer pattern is exposed from the overlap region. However, as described above, since the circuit does not operate when a defect occurs, the OPC effect is verified not only by the predetermined process conditions but also by the process conditions in consideration of the variation of the process conditions in the manufacturing process. It is necessary to verify that no problem occurs, including the margin for each process.

If it is determined in step SC8 that the OPC effect cannot be obtained, that is, the circuit cannot be expected to operate normally, the process proceeds to step SC9. Check if there is.

(4) If it is determined in step SC9 that there is no pattern arrangement in which the OPC effect cannot be obtained, the process is repeated from step SC7 again, and a cell-level OPC pattern is created again so as to obtain the OPC effect. On the other hand, if it is determined in step SC9 that there is a circuit pattern arrangement in which the OPC effect cannot be obtained, the process proceeds to step SC4, and the circuit pattern is corrected so that the circuit pattern arrangement in which the OPC effect cannot be obtained does not occur. Thereafter, the process is repeated from step SC2.

Next, in step SC10, it is determined whether the cell area of each circuit pattern is smaller than a target value. If the cell area is larger than the target value, the process proceeds to step SC4, where the circuit pattern is modified so as to reduce the cell area. On the other hand, if the cell area is equal to or smaller than the target value, the process proceeds to step SC11 shown in FIG.

Next, in step SC11 shown in FIG. 11, the cell level OPC pattern created for each cell is registered as a mask pattern cell library of each circuit pattern. The circuit patterns belonging to the second category are registered in the cell library as they are. Thus, a set of basic circuits constituting the LSI chip pattern is accumulated.

Next, in step SC12, circuit pattern data necessary for the LSI is extracted from the cell library, and LSI chip data is created using the extracted circuit pattern data.

(4) Next, in step SC13, final process conditions for manufacturing LSI chip data are determined.

Next, in step SC14, based on the final process conditions, the amount of change in the processing dimension caused by the proximity effect with respect to the mask dimension is evaluated in more detail. As a result, a chip-level OPC pattern is created for a cell belonging to the second category, for example, a portion where the processing dimension of the gate length in the gate pattern must exactly match the design dimension. The OPC pattern creation method at this time can use a rule base or a model base.

Next, in step SC15, CD verification is performed to determine whether the dimensions of the processed pattern created from the chip-level OPC pattern match the dimensions of the circuit pattern. Also in this case, the finished dimensions are verified using a simulation method capable of sufficiently reproducing an actual circuit. The CD verification in this step also does not need to verify all the parts of one circuit pattern, but is performed on the parts whose processing dimensions need to match the design dimensions with high accuracy. If it is determined that the CD verification does not match, the process proceeds to step SC16, in which the chip level OPC pattern is corrected so as to eliminate the mismatching portion in the OPC pattern, and the process is repeated from step SC14 again. If a model base is used in step SC14, the CD verification need not be performed.

Next, in SC17, mask pattern data is created by using the created cell-level and chip-level OPC patterns. A mask or reticle is manufactured from the mask pattern data, and an operable circuit pattern can be transferred to a resist film or the like formed on a semiconductor substrate using the manufactured mask or reticle.

(Modification of Second Embodiment)
Hereinafter, a modified example of the second embodiment of the present invention will be described with reference to the drawings.

FIGS. 13 and 14 show a processing flow of an LSI mask data creating method according to a modification of the second embodiment of the present invention. In the second embodiment, as shown in step SC11, the cell level OPC pattern is directly registered in the cell library. In this modification, when a cell-level OPC pattern is created based on a rule base, a step of creating a cell-level OPC pattern includes a step of setting the creation specification, and a step of creating a cell-level OPC pattern based on the creation specification. The case where the operation is performed separately will be described. As a result, instead of the cell level OPC pattern, a circuit pattern and a cell level OPC pattern creation specification for the circuit pattern can be separately registered in the cell library.

In FIG. 13, the difference from the second embodiment is that the generation of the cell level OPC pattern in step SC5 shown in FIG. 10 differs from the second embodiment in that the cell level OPC pattern generation specification for each circuit cell shown in step SD5A is used. And the creation of the cell level OPC pattern shown in step SD5B.

In FIG. 14, the difference from the second embodiment is that in step SD11 for creating a cell library, the object to be registered in the cell library is not an OPC pattern, but each circuit pattern and its corresponding cell-level OPC pattern creation specification. Is to register each combination.

A further significant difference is that in step SD14, a cell-level OPC pattern is created according to the created cell-level OPC pattern creation specification, and simultaneously a chip-level OPC pattern is created according to a rule-based or model-based chip-level OPC pattern creation specification. The point to do.

In this way, it is not necessary to process the cell-level and chip-level OPC patterns composed of a large amount of complicated pattern data until immediately before the creation of the mask data, and the process of handling a large amount of data can be unified.

{Circle around (2)} Since the cells registered in the cell library need to represent not only the mask data of the mask production but also the circuit configuration, it is desirable that a circuit pattern representing a processed pattern, not an OPC pattern, be registered. Also, when changing the registered circuit pattern, it is more convenient to register the circuit pattern instead of the OPC pattern.

As described above, according to the second embodiment and its modifications, the circuit patterns are classified into the first category that strongly affects the cell area and the second category that is not strongly affected by the first category. Can be determined at the cell design stage. For this reason, the circuit pattern can be designed while considering the OPC effect and reducing the cell area, so that it is possible to eliminate a pattern arrangement in which the OPC effect cannot be obtained at the stage of designing each circuit pattern. Accordingly, when the target cell area is achieved, the circuit pattern that is difficult to realize and the circuit pattern that includes a useless margin are not mixed, so that the cell area is reliably reduced to the target value while The expected value of the yield at which the LSI operates normally can also be improved.

(Third embodiment)
Hereinafter, a third embodiment of the present invention will be described with reference to the drawings.

This embodiment is different from the second embodiment in that the circuit pattern includes a first layer including an activation layer pattern like a transistor and a second layer including a gate pattern extending over the activation layer pattern. An OPC pattern defined by a plurality of layers is created in an upstream cell design process, and an OPC pattern defined only by a single layer, such as a gate pattern, is created in a downstream mask data processing process.

A circuit (cell) includes a plurality of components. In designing a circuit pattern that determines the arrangement of the plurality of components, a circuit that greatly affects the cell area among various circuits is usually a single layer. Rather, it is defined by patterns contained in multiple layers. Since the arrangement of circuit components can be changed for each layer in the OPC pattern defined by the plurality of layers, the OPC pattern defined by the plurality of layers is considered in the cell design stage, so that the circuit area can be reduced with a smaller cell area. Can be arranged.

FIGS. 15 and 16 show a processing flow of an LSI mask data creating method according to the third embodiment of the present invention.

First, in step SE1 shown in FIG. 15, similarly to step SC1 according to the second embodiment, a design rule, a basic process condition, and an OPC pattern arrangement rule are determined. Further, as a feature of this embodiment, an OPC pattern defined by a plurality of layers, that is, an inter-layer OPC pattern, which is important in determining a cell area, is classified as a first category, and an OPC pattern defined by a single layer is defined. Patterns, ie, intra-layer patterns, are classified as a second category.

Next, in steps SE2, SE3, and SE4, each circuit pattern is created, and after verifying the design rules, in step SE5, an interlayer OPC pattern is created for each cell.

Here, the interlayer OPC pattern will be described with reference to the drawings.

FIG. 17A shows a plan configuration of a transistor circuit for describing a circuit pattern according to the present embodiment, and FIG. 17B shows a transistor circuit for describing an interlayer OPC pattern of FIG. 17A. 2 shows a planar configuration. As shown in FIG. 17A, a first circuit pattern 31A including a rectangular activation layer pattern 31a and a gate layer pattern 31b straddling the center of the long side of the activation layer pattern 31a, and a rectangular circuit And a second circuit pattern 32A composed of an active layer pattern 32a and a gate layer pattern 32b straddling the center of the long side of the active layer pattern 32a. The long sides of the activation layer patterns 31a and 32a are spaced from each other by about 0.3 μm, and the opposing ends of the gate layer patterns 31b and 32b are arranged so as not to overlap with each other.

Thus, for example, the first circuit pattern 31A has an overlapping portion where the activation layer pattern 31a and the gate layer pattern 31b overlap. Therefore, when the activation layer pattern 31a is formed on the semiconductor substrate, a channel region is generated in the overlapping portion to function as a transistor circuit. For this reason, there is an arrangement rule between the activation layer pattern 31a and the gate layer pattern 31b. Therefore, changes in the positional relationship between the activation layer pattern 31a and the gate layer pattern 31b affect each other. The same applies to the second circuit pattern 32A.

第 The first OPC pattern 31B and the second OPC pattern 32B shown in FIG. 17B correspond to the first circuit pattern 31A and the second circuit pattern 32A shown in FIG. 17A, respectively. As shown in FIG. 17B, here, an example is shown in which hammer head patterns having different shapes are added to both ends of each of the gate layer patterns 31b and 32b. Specifically, at one end of each of the gate layer patterns 31b and 32b on the side facing each other, the distance between the active layer patterns 31a and 32a is 0.2 μm, which is smaller than that in the case of the circuit pattern. The shape of the hammer head pattern is smaller than the other end.

Although not shown, an OPC pattern based on a contact pattern for connecting wires included in different layers to each other also includes a wiring OPC pattern created from the wiring pattern and a contact OPC pattern created from the contact pattern. A pattern is defined by a plurality of layers.

Next, in steps SE6, SE8, and SE10 shown in FIG. 15, whether the created interlayer OPC pattern satisfies the OPC pattern arrangement rule, whether the OPC effect can be obtained, and whether the cell area satisfies a predetermined value. Verify whether or not there is. The verification method may be performed by the method described in the second embodiment. If the verification result is unsatisfactory, the inter-layer OPC pattern is corrected in step SE7, or the circuit pattern is corrected for each layer and the rearrangement of circuit components is performed in step SE4 so as to obtain the OPC effect. Do.

Next, in step SE11 shown in FIG. 16, the interlayer OPC pattern created for each cell is registered as a mask pattern cell library of each circuit pattern. The circuit patterns belonging to the second category are registered in the cell library as they are. As a result, a set of basic circuits constituting the LSI chip pattern is accumulated.

Next, in step SE12, circuit pattern data required for the LSI is extracted from the cell library, and LSI chip data is created using the extracted circuit pattern data. In the next step SE13, a final process of manufacturing the LSI chip data Determine the conditions.

Next, in step SE14, the amount of change in the processing dimension caused by the proximity effect with respect to the mask dimension is evaluated in more detail based on the final process conditions. As a result, an intra-layer OPC pattern belonging to the second category is created. At this time, the OPC pattern creation method may be either rule-based or model-based.

Next, in step SE15, CD verification is performed to determine whether or not the dimensions of the processing pattern created from the intra-layer OPC pattern match the dimensions of the circuit pattern. Also in this case, the finished dimensions are verified using a simulation method capable of sufficiently reproducing an actual circuit. Also in the present embodiment, it is not necessary to verify all the portions of one circuit pattern, and the process is performed on a portion where the processing dimensions need to match the design dimensions with high accuracy. If it is determined that the CD verification does not match, the process proceeds to step SE16, in which the intra-layer OPC pattern is corrected so as to eliminate the mismatching portion in the OPC pattern, and the process is repeated again from step SE14. When the model base is used in step SE14, the CD verification need not be performed.

Next, in SE17, mask pattern data is created using the created OPC patterns of the inter-layer and intra-layer. A mask or reticle is manufactured from the mask pattern data, and an operable circuit pattern can be transferred to a resist film or the like formed on a semiconductor substrate using the manufactured mask or reticle.

In the present embodiment, in step SE14, the creation of the intra-layer OPC pattern belonging to the second category is performed after the creation of the LSI chip data in step SE12. In the first category of the cell level OPC pattern. Therefore, a circuit in which such a cell-level OPC pattern is generated may be designed in step SE2.

(Modification of Third Embodiment)
Hereinafter, a modified example of the third embodiment of the present invention will be described with reference to the drawings.

FIGS. 18 and 19 show a processing flow of an LSI mask data creating method according to a modification of the third embodiment of the present invention. In the third embodiment, as shown in step SE11, the interlayer OPC pattern is directly registered in the cell library. In the present modification, when an interlayer OPC pattern is created by a rule base, a step of creating an interlayer OPC pattern includes a step of setting the creation specification, and a step of creating an interlayer OPC pattern based on the creation specification. The case where the operation is performed separately will be described. Thus, instead of the inter-layer OPC pattern, a circuit pattern and an inter-layer OPC pattern creation specification for the circuit pattern can be separately registered in the cell library.

In FIG. 18, the difference from the third embodiment is that the creation of an interlayer OPC pattern in step SE5 shown in FIG. 15 is different from the third embodiment in that the specifications of the interlayer OPC pattern creation specification for each circuit cell in step SF5A are different. This is a point separated into two processes of setting and creating an interlayer OPC pattern in step SF5B.

In FIG. 19, the difference from the third embodiment is that in step SF11 for creating a cell library, the object to be registered in the cell library is not an OPC pattern, but each circuit pattern and its corresponding interlayer OPC pattern creation specification. Is to register each combination.

A further significant difference is that in step SF14, an inter-layer OPC pattern is created according to the created inter-layer OPC pattern creation specification, and simultaneously, an intra-layer OPC pattern is created according to a rule-based or model-based intra-layer OPC pattern creation specification. The point to do.

In this way, it is not necessary to process the OPC patterns of the inter-layer and the intra-layer composed of a large amount of complicated pattern data until immediately before the creation of the mask data, and the process of handling a large amount of data can be unified.

{Circle around (2)} Since the cells registered in the cell library need to represent not only the mask data of the mask production but also the circuit configuration, it is desirable that a circuit pattern representing a processed pattern, not an OPC pattern, be registered. Also, when changing the registered circuit pattern, it is more convenient to register the circuit pattern instead of the OPC pattern.

As described above, according to the third embodiment and its modifications, the circuit patterns are classified into the first category that strongly affects the cell area and the second category that is not strongly affected by the first category. Can be determined at the cell design stage. For this reason, the circuit pattern can be designed while considering the OPC effect and reducing the cell area, so that it is possible to eliminate a pattern arrangement in which the OPC effect cannot be obtained at the stage of designing each circuit pattern. Accordingly, when the target cell area is achieved, the circuit pattern that is difficult to realize and the circuit pattern that includes a useless margin are not mixed, so that the cell area is reliably reduced to the target value while The expected value of the yield at which the LSI can operate normally can also be improved.

In steps SE4 and SF4, the components of the circuit may be rearranged using a tool called a compactor. If a compactor is used, it is not necessary to repeat verification and correction as in the present embodiment. Furthermore, if the OPC effect of the inter-layer OPC pattern is added to the rearrangement function of the compactor in a ruled manner, the cell pattern can be automatically synthesized.

3 is a flowchart illustrating a method for creating LSI mask data according to the first embodiment of the present invention. 3 is a flowchart illustrating a method for creating an LSI pattern layout according to the first embodiment of the present invention. FIG. 2 is a plan view showing an example of a circuit pattern in the LSI pattern layout creating method according to the first embodiment of the present invention. FIG. 4 is a plan view showing an LSI pattern layout creating method according to the first embodiment of the present invention, and showing an example of an OPC pattern created from the circuit pattern shown in FIG. 3. FIG. 4 is a plan view illustrating a method for creating a layout of an LSI pattern according to the first embodiment of the present invention, and illustrating another example of an OPC pattern created from the circuit pattern illustrated in FIG. 3. FIG. 6 is a plan view illustrating a method for creating a layout of an LSI pattern according to the first embodiment of the present invention, and illustrating an example of a processed pattern obtained from the OPC pattern illustrated in FIG. 5. FIG. 4 is a plan view showing a method for creating a layout of an LSI pattern according to the first embodiment of the present invention, in which the circuit pattern shown in FIG. 3 is modified. FIG. 8 is a plan view showing an LSI pattern layout creating method according to the first embodiment of the present invention, showing an example of an OPC pattern created from the circuit pattern shown in FIG. 7. FIG. 9 is a plan view illustrating an LSI pattern layout creation method according to the first embodiment of the present invention, and illustrating an example of a processed pattern obtained from the OPC pattern illustrated in FIG. 8. 6 is a flowchart illustrating a method for creating LSI mask data according to a second embodiment of the present invention. 9 is a flowchart illustrating a method for creating LSI mask data according to a second embodiment of the present invention. (A) and (b) show patterns for explaining categories in an LSI mask data creation method according to a second embodiment of the present invention, and (a) shows a chip-level circuit belonging to the second category. FIG. 4B is a plan view showing a pattern, and FIG. 4B is a plan view showing a cell-level circuit pattern belonging to a first category. 15 is a flowchart illustrating a method of generating LSI mask data according to a modification of the second embodiment of the present invention. 15 is a flowchart illustrating a method of generating LSI mask data according to a modification of the second embodiment of the present invention. 13 is a flowchart illustrating a method for creating LSI mask data according to a third embodiment of the present invention. 13 is a flowchart illustrating a method for creating LSI mask data according to a third embodiment of the present invention. (A) and (b) show patterns for explaining categories in the method of generating LSI mask data according to the third embodiment of the present invention, and (a) shows an inter-layer circuit belonging to the first category It is a top view showing a pattern, and (b) is a top view showing an example of the OPC pattern created from (a). 15 is a flowchart illustrating a method for creating LSI mask data according to a modification of the third embodiment of the present invention. 15 is a flowchart illustrating a method for creating LSI mask data according to a modification of the third embodiment of the present invention. 7A and 7B are plan views showing a conventional LSI mask data creation method, showing a design pattern and a processing pattern of a transistor.

Explanation of reference numerals

Reference Signs List 11 activation layer pattern 11A activation layer pattern 11B activation layer pattern 11C activation layer pattern 12 first gate pattern 12A first gate pattern 12h hammer head pattern 13 second gate pattern 13A second gate pattern 13h hammer Head pattern 14 Third gate pattern 14A Third gate pattern 14B Third gate pattern 14C Third gate pattern 14a Transistor part 14b Gate wiring part 14h Hammerhead pattern 15 Wiring pattern 15A Wiring pattern 17 Verification target area 17A First Verification target area 18A second verification target area 21A first pattern 21B first OPC pattern 21a wiring portion 21b protrusion 21c hammerhead pattern 21d insection pattern 22A second pattern 22B second OPC pattern 22a wiring portion 22b projecting portion 22c serif pattern 31A first circuit pattern 31B first OPC pattern 31a activation layer pattern 31b gate layer pattern 32A second circuit pattern 32B second OPC pattern 32a Active layer pattern 32b Gate layer pattern

Claims (23)

A plurality of circuit patterns included in the LSI are divided into a first correction pattern group that does not change the pattern shape according to a change in process conditions, and a second correction pattern group that changes the pattern shape according to a change in process conditions. A correction pattern group classification process for classification;
A cell level correction pattern data generating step of generating cell level proximity effect correction pattern data from the first correction pattern group when designing the plurality of circuit patterns;
A step of generating chip-level proximity effect correction pattern data from the second correction pattern group when generating chip data from the plurality of circuit patterns. How to create LSI mask data. The cell level correction pattern data creating step includes:
Determining whether the proximity effect correction in the created cell-level proximity effect correction pattern data is valid,
When it is determined that the proximity effect correction is invalid, the proximity effect correction pattern data or the circuit pattern corresponding to the proximity effect correction pattern data is corrected so that the proximity effect correction becomes effective. Determining the validity again;
2. The method according to claim 1, further comprising the step of registering the cell-level proximity effect correction pattern data in a cell library when it is determined that the pattern is valid. A plurality of circuit patterns included in the LSI are divided into a first correction pattern group that does not change the pattern shape according to a change in process conditions, and a second correction pattern group that changes the pattern shape according to a change in process conditions. Classifying,
Setting a cell-level correction pattern creation specification for creating a cell-level proximity effect correction pattern for the first correction pattern group;
A step of designing the plurality of circuit patterns;
Determining whether or not the proximity effect correction is effective in the cell-level proximity effect correction pattern created by the cell level correction pattern creation specification for the first correction pattern group;
When the proximity effect correction is determined to be invalid, the correction of the circuit pattern determined to be invalid is performed so that the proximity effect correction is valid, and then the validity of the proximity effect correction is determined again. ,
Registering a circuit pattern belonging to the first correction pattern group in a cell library and registering a circuit pattern belonging to the second correction pattern group in the cell library when the proximity effect correction is determined to be valid; When,
A step of creating chip-level pattern data from the circuit patterns registered in the cell library;
Setting a chip-level correction pattern creation specification for creating a chip-level proximity effect correction pattern for the second correction pattern group;
Creating cell-level proximity effect correction pattern data from the circuit patterns belonging to the first correction pattern group based on the cell-level correction pattern creation specification;
Generating chip-level proximity effect correction pattern data from the circuit patterns belonging to the second correction pattern group based on the chip-level correction pattern generation specification. How to make. A plurality of circuit patterns included in the LSI are divided into a first correction pattern group that does not change the pattern shape according to a change in process conditions, and a second correction pattern group that changes the pattern shape according to a change in process conditions. Classifying,
Setting a cell-level correction pattern creation specification for creating a cell-level proximity effect correction pattern for the first correction pattern group;
A step of designing the plurality of circuit patterns;
Determining whether or not the proximity effect correction is effective in the cell-level proximity effect correction pattern created by the cell level correction pattern creation specification for the first correction pattern group;
When the proximity effect correction is determined to be invalid, the circuit pattern determined to be invalid or the cell-level correction pattern creation specification of the circuit pattern is corrected so that the proximity effect correction becomes valid. Re-determining the effectiveness of the effect correction;
When it is determined that the proximity effect correction is valid, the circuit pattern belonging to the first correction pattern group and the cell level correction pattern creation specification corresponding to the circuit pattern are registered in a cell library, and the second correction pattern is registered. Registering a circuit pattern belonging to a group in the cell library;
A step of creating chip-level pattern data from the circuit patterns registered in the cell library;
Creating cell-level proximity effect correction pattern data from the circuit patterns belonging to the first correction pattern group based on the cell-level correction pattern creation specification;
Generating chip-level proximity effect correction pattern data from circuit patterns belonging to the second correction pattern group based on predetermined chip-level correction pattern generation specifications. How to create The step of determining the validity of the proximity effect correction includes the step of, when there are a plurality of layouts of the circuit pattern for which the proximity effect correction is determined to be valid, selecting a layout having a circuit area of a predetermined value or less from the plurality of layouts. 5. The method of generating mask data for LSI according to claim 2, wherein the method comprises: 6. The method of claim 1, wherein the cell-level proximity effect correction pattern data includes a serif pattern, a hammerhead pattern, or an insection pattern. 7. Among a plurality of circuit patterns included in the LSI, a first correction pattern group in which the circuit pattern is determined by a pattern arrangement over a plurality of layers, and a second correction pattern in which the circuit pattern is determined by a pattern arrangement in one layer A correction pattern group classification step of classifying the correction pattern into groups;
An inter-layer correction pattern data creating step of creating inter-layer proximity effect correction pattern data from the first correction pattern group when designing the plurality of circuit patterns;
An intra-layer correction pattern data generating step of generating intra-layer proximity effect correction pattern data from the second correction pattern group when generating chip data from the plurality of circuit patterns. How to create LSI mask data. The interlayer correction pattern data creation step includes:
A step of determining whether proximity effect correction in the created proximity effect correction pattern data of the interlayer is valid,
When the proximity effect correction is determined to be invalid, the proximity effect correction pattern data of the interlayer or the circuit pattern corresponding to the proximity effect correction pattern data is corrected so that the proximity effect correction becomes effective. Determining the validity again;
8. The method according to claim 7, further comprising the step of: registering the proximity effect correction pattern data of the interlayer in a cell library when it is determined that the pattern is valid. Among a plurality of circuit patterns included in the LSI, a first correction pattern group in which the circuit pattern is determined by a pattern arrangement over a plurality of layers, and a second correction pattern in which the circuit pattern is determined by a pattern arrangement in one layer Classifying into groups and
Setting an interlayer correction pattern creation specification for creating an interlayer proximity effect correction pattern for the first correction pattern group;
A step of designing the plurality of circuit patterns;
A step of determining whether or not the proximity effect correction is effective in the proximity effect correction pattern of the interlayer, which is created based on the interlayer correction pattern creation specification for the first correction pattern group;
When the proximity effect correction is determined to be invalid, the correction of the circuit pattern determined to be invalid is performed so that the proximity effect correction is valid, and then the validity of the proximity effect correction is determined again. ,
Registering a circuit pattern belonging to the first correction pattern group in a cell library and registering a circuit pattern belonging to the second correction pattern group in the cell library when the proximity effect correction is determined to be valid; When,
A step of creating chip-level pattern data from the circuit patterns registered in the cell library;
Setting an intra-layer correction pattern creation specification for creating an intra-layer proximity effect correction pattern for the second correction pattern group;
Creating proximity effect correction pattern data for an interlayer from circuit patterns belonging to the first correction pattern group based on the interlayer correction pattern creation specification;
Generating the proximity effect correction pattern data of the intra layer from the circuit patterns belonging to the second correction pattern group based on the intra layer correction pattern generation specification. How to make. Among a plurality of circuit patterns included in the LSI, a first correction pattern group in which the circuit pattern is determined by a pattern arrangement over a plurality of layers, and a second correction pattern in which the circuit pattern is determined by a pattern arrangement in one layer Classifying into groups and
Setting an interlayer correction pattern creation specification for creating an interlayer proximity effect correction pattern for the first correction pattern group;
A step of designing the plurality of circuit patterns;
A step of determining whether or not the proximity effect correction is effective in the proximity effect correction pattern of the interlayer, which is created based on the interlayer correction pattern creation specification for the first correction pattern group;
When the proximity effect correction is determined to be invalid, the circuit pattern determined to be invalid or an interlayer correction pattern creation specification of the circuit pattern is corrected so that the proximity effect correction becomes valid. Re-determining the effectiveness of the effect correction;
When it is determined that the proximity effect correction is valid, the circuit pattern belonging to the first correction pattern group and an interlayer correction pattern creation specification corresponding to the circuit pattern are registered in a cell library, and the second correction pattern is registered. Registering a circuit pattern belonging to a group in the cell library;
A step of creating chip-level pattern data from the circuit patterns registered in the cell library;
Creating proximity effect correction pattern data for an interlayer from circuit patterns belonging to the first correction pattern group based on the interlayer correction pattern creation specification;
Generating mask data for an intra-layer proximity effect correction pattern from circuit patterns belonging to the second correction pattern group based on predetermined intra-layer correction pattern generation specifications. How to create The step of determining the validity of the proximity effect correction includes the step of, when there are a plurality of layouts of the circuit pattern for which the proximity effect correction is determined to be valid, selecting a layout having a circuit area of a predetermined value or less from the plurality of layouts. The method for generating mask data for LSI according to any one of claims 8 to 10, further comprising: 12. The specification according to claim 9, wherein the specification for creating an interlayer correction pattern is determined by an arrangement rule that defines one layer including a gate of a transistor and another layer including an active region. 2. The method for creating LSI mask data according to claim 1. The specification for creating an interlayer correction pattern is determined by an arrangement rule that defines a first wiring layer and a layer including a contact that electrically connects a second wiring layer different from the first wiring layer. 12. The method of generating mask data for LSI according to claim 9, wherein: The step of determining the effectiveness of the proximity effect correction includes performing a process simulation including at least one of a lithography step and an etching step to determine whether a predicted value of a processing dimension satisfies a predetermined value. The method for generating mask data for LSI according to any one of claims 2 to 6, and 8 to 11, wherein: 15. The lithography step in the process simulation, wherein it is determined whether or not a predicted value of a processing dimension when the exposure amount or the focus position changes beyond a process margin satisfies the predetermined value. 3. The method of creating mask data for LSI described in 1. above. 16. The method according to claim 14, wherein the determination of the process simulation includes a step of determining a dimension of the transistor in a gate length direction. 16. The method according to claim 14, wherein the determination of the process simulation includes a step of determining a protrusion dimension of a gate of the transistor from an active layer in a gate width direction. A plurality of circuit patterns included in the LSI are divided into a first correction pattern group that does not change the pattern shape according to a change in process conditions, and a second correction pattern group that changes the pattern shape according to a change in process conditions. Classifying,
Creating a cell-level proximity effect correction pattern from the first correction pattern group when designing the plurality of circuit patterns;
A step of generating chip-level proximity effect correction pattern data from the second correction pattern group when generating chip data from the plurality of circuit patterns;
A mask manufacturing process of manufacturing a mask using the created proximity effect correction pattern data,
A pattern forming step of forming the plurality of circuit patterns on a semiconductor substrate using a manufactured mask. A plurality of circuit patterns included in the LSI are divided into a first correction pattern group that does not change the pattern shape according to a change in process conditions, and a second correction pattern group that changes the pattern shape according to a change in process conditions. Classifying,
Setting a cell-level correction pattern creation specification for creating a cell-level proximity effect correction pattern for the first correction pattern group;
A step of designing the plurality of circuit patterns;
Determining whether or not the proximity effect correction is effective in the cell-level proximity effect correction pattern created by the cell level correction pattern creation specification for the first correction pattern group;
When the proximity effect correction is determined to be invalid, the correction of the circuit pattern determined to be invalid is performed so that the proximity effect correction is valid, and then the validity of the proximity effect correction is determined again. ,
Registering a circuit pattern belonging to the first correction pattern group in a cell library and registering a circuit pattern belonging to the second correction pattern group in the cell library when the proximity effect correction is determined to be valid; When,
A step of creating chip-level pattern data from the circuit patterns registered in the cell library;
Setting a chip-level correction pattern creation specification for creating a chip-level proximity effect correction pattern for the second correction pattern group;
Creating cell-level proximity effect correction pattern data from the circuit patterns belonging to the first correction pattern group based on the cell-level correction pattern creation specification;
Creating chip-level proximity effect correction pattern data from the circuit patterns belonging to the second correction pattern group based on the chip-level correction pattern creation specification;
A mask manufacturing process of manufacturing a mask using the created proximity effect correction pattern data,
A pattern forming step of forming the plurality of circuit patterns on a semiconductor substrate using a manufactured mask. A plurality of circuit patterns included in the LSI are divided into a first correction pattern group that does not change the pattern shape according to a change in process conditions, and a second correction pattern group that changes the pattern shape according to a change in process conditions. Classifying,
Setting a cell-level correction pattern creation specification for creating a cell-level proximity effect correction pattern for the first correction pattern group;
A step of designing the plurality of circuit patterns;
Determining whether or not the proximity effect correction is effective in the cell-level proximity effect correction pattern created by the cell level correction pattern creation specification for the first correction pattern group;
When the proximity effect correction is determined to be invalid, the circuit pattern determined to be invalid or the cell-level correction pattern creation specification of the circuit pattern is corrected so that the proximity effect correction becomes valid. Re-determining the effectiveness of the effect correction;
When it is determined that the proximity effect correction is valid, the circuit pattern belonging to the first correction pattern group and the cell level correction pattern creation specification corresponding to the circuit pattern are registered in a cell library, and the second correction pattern is registered. Registering a circuit pattern belonging to a group in the cell library;
A step of creating chip-level pattern data from the circuit patterns registered in the cell library;
Creating cell-level proximity effect correction pattern data from the circuit patterns belonging to the first correction pattern group based on the cell-level correction pattern creation specification;
Generating chip-level proximity effect correction pattern data from the circuit patterns belonging to the second correction pattern group based on predetermined chip-level correction pattern generation specifications;
A mask manufacturing process of manufacturing a mask using the created proximity effect correction pattern data,
A pattern forming step of forming the plurality of circuit patterns on a semiconductor substrate by using a manufactured mask. Among a plurality of circuit patterns included in the LSI, a first correction pattern group in which the circuit pattern is determined by a pattern arrangement over a plurality of layers, and a second correction pattern in which the circuit pattern is determined by a pattern arrangement in one layer A correction pattern group classification step of classifying the correction pattern into groups;
An inter-layer correction pattern data creating step of creating inter-layer proximity effect correction pattern data from the first correction pattern group when designing the plurality of circuit patterns;
An intra-layer correction pattern data creating step of creating an intra-layer proximity effect correction pattern data from the second correction pattern group when creating chip data from the plurality of circuit patterns;
Using the created proximity effect correction pattern data of the interlayer and the intra layer, a mask manufacturing process of manufacturing a mask,
A pattern forming step of forming the plurality of circuit patterns on a semiconductor substrate using a manufactured mask. Among a plurality of circuit patterns included in the LSI, a first correction pattern group in which the circuit pattern is determined by a pattern arrangement over a plurality of layers, and a second correction pattern in which the circuit pattern is determined by a pattern arrangement in one layer Classifying into groups and
Setting an interlayer correction pattern creation specification for creating an interlayer proximity effect correction pattern for the first correction pattern group;
A step of designing the plurality of circuit patterns;
A step of determining whether or not the proximity effect correction is effective in the proximity effect correction pattern of the interlayer, which is created based on the interlayer correction pattern creation specification for the first correction pattern group;
When the proximity effect correction is determined to be invalid, the correction of the circuit pattern determined to be invalid is performed so that the proximity effect correction is valid, and then the validity of the proximity effect correction is determined again. ,
Registering a circuit pattern belonging to the first correction pattern group in a cell library and registering a circuit pattern belonging to the second correction pattern group in the cell library when the proximity effect correction is determined to be valid; When,
A step of creating chip-level pattern data from the circuit patterns registered in the cell library;
Setting an intra-layer correction pattern creation specification for creating an intra-layer proximity effect correction pattern for the second correction pattern group;
Creating proximity effect correction pattern data for an interlayer from circuit patterns belonging to the first correction pattern group based on the interlayer correction pattern creation specification;
Creating intra-layer proximity effect correction pattern data from the circuit patterns belonging to the second correction pattern group based on the intra-layer correction pattern creation specification;
Using the created proximity effect correction pattern data of the interlayer and the intra layer, a mask manufacturing process of manufacturing a mask,
A pattern forming step of forming the plurality of circuit patterns on a semiconductor substrate using a manufactured mask. Among a plurality of circuit patterns included in the LSI, a first correction pattern group in which the circuit pattern is determined by a pattern arrangement over a plurality of layers, and a second correction pattern in which the circuit pattern is determined by a pattern arrangement in one layer Classifying into groups and
Setting an interlayer correction pattern creation specification for creating an interlayer proximity effect correction pattern for the first correction pattern group;
A step of designing the plurality of circuit patterns;
A step of determining whether or not the proximity effect correction is effective in the proximity effect correction pattern of the interlayer, which is created based on the interlayer correction pattern creation specification for the first correction pattern group;
When the proximity effect correction is determined to be invalid, the circuit pattern determined to be invalid or an interlayer correction pattern creation specification of the circuit pattern is corrected so that the proximity effect correction becomes valid. Re-determining the effectiveness of the effect correction;
When it is determined that the proximity effect correction is valid, the circuit pattern belonging to the first correction pattern group and an interlayer correction pattern creation specification corresponding to the circuit pattern are registered in a cell library, and the second correction pattern is registered. Registering a circuit pattern belonging to a group in the cell library;
A step of creating chip-level pattern data from the circuit patterns registered in the cell library;
Creating proximity effect correction pattern data for an interlayer from circuit patterns belonging to the first correction pattern group based on the interlayer correction pattern creation specification;
Creating a proximity effect correction pattern data of an intra layer from a circuit pattern belonging to the second correction pattern group based on a predetermined intra layer correction pattern creation specification;
Using the created proximity effect correction pattern data of the interlayer and the intra layer, a mask manufacturing process of manufacturing a mask,
A pattern forming step of forming the plurality of circuit patterns on a semiconductor substrate using a manufactured mask.

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