JP2005293177A - Memory controller and flash memory system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To configure a master flash memory system and a slave flash memory system by using one memory controller. <P>SOLUTION: A master flash memory 33 and a slave flash memory 34 are connected to the memory controller 32 via an internal bus 36. The memory controller 32 accesses either the master flash memory 33 or the slave flash memory 34 according to information provided by a host system 31 connected thereto via an external bus 36. The memory controller 32 determines the chip of the flash memory to be accessed according to information supplied from the host system 31 that designates a destination for writing it. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a memory controller and a flash memory system.

  In recent years, flash memories have been widely adopted as semiconductor memories used in memory systems such as memory cards and silicon disks. A flash memory is a kind of nonvolatile memory. Data stored in the flash memory is required to be retained even when power is not supplied.

  A NAND flash memory is a type of flash memory that is particularly frequently used in the above memory system. Each of the plurality of memory cells included in the NAND flash memory receives a logical value “0” from an erased state in which data indicating a logical value “1” is stored, independently of the other memory cells. It is possible to change to a writing state in which the indicated data is stored. In contrast, when changing from the written state to the erased state, each memory cell cannot change independently of the other memory cells. At this time, all of a predetermined number of memory cells called blocks are simultaneously erased. This batch erase operation is generally called “block erase”. The writing process or the reading process for the NAND flash memory is performed in units of a predetermined number of memory cells called pages. A block which is a unit of erasure processing is composed of a plurality of pages.

  If a page in the NAND flash memory corresponds to a sector in the magnetic disk device, the magnetic disk device can be replaced with a memory system using the NAND flash memory relatively easily. For this reason, a memory system using a NAND flash memory is often used to replace a conventional magnetic disk device.

For example, a disk device composed of a master disk and a slave disk disclosed in Patent Document 1 (Japanese Patent Laid-Open No. 2002-259130) is replaced with a memory system having the structure shown in FIG. In the memory system shown in FIG. 6, the memory controller 52 and the flash memory 53 constitute a master side memory system, and the memory controller 54 and the flash memory 55 constitute a slave side memory system. Therefore, if the host system 51 accesses the memory controller 52, the data stored in the flash memory 53 on the master side can be accessed. If the host system 51 accesses the memory controller 54, the data is stored in the flash memory 55 on the slave side. Data can be accessed.
JP 2002-259130 A

  Since the conventional flash memory system shown in FIG. 6 constitutes a flash memory system in which the master side and the slave side are independent, two memory controllers are required when configuring the master side and slave side flash memory systems. become. The host system side must access different memory controllers when accessing the flash memory system on the master side and when accessing the flash memory system on the slave side.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a memory controller capable of configuring a master flash memory system and a slave flash memory system with a single memory controller, and a flash memory system including the memory controller.

  An object of the present invention includes an information holding function for setting information about an access destination supplied from the host system side, and an access control function for controlling access to a plurality of flash memory chips. Is allocated to a setting area for information specifying the flash memory chip to be accessed.

  According to the present invention, it is preferable that the information holding function includes a cylinder register, a device head register, and a sector register.

  According to the present invention, it is preferable that the information specifying the flash memory chip to be accessed is set in the parameter setting area for the device of the device / head register.

  According to the present invention, it is preferable that the information holding function is a logical block address register.

  The object according to the present invention is also achieved by a flash memory system comprising the memory controller and a plurality of flash memory chips.

  An object of the present invention is to store an information holding function for setting information about an access destination supplied from the host system side, an access control function for controlling access to a plurality of flash memory chips, and master data. A first flash memory chip and a second flash memory chip in which slave data is stored, and a part of the information holding function stores information specifying the first flash memory chip or the second flash memory chip; This is also achieved by a flash memory system characterized in that it is allocated to a setting area.

  According to the present invention, it is preferable that the information holding function includes a cylinder register, a device head register, and a sector register.

  Further, according to the present invention, it is preferable that information specifying the first flash memory chip or the second flash memory chip is set in a parameter setting area for the device of the device / head register.

  According to the present invention, it is preferable that the information holding function is a logical block address register.

  According to the present invention, a flash memory system on the master side and a flash memory system on the slave side can be configured with a single memory controller. The host system side can access the data stored in the flash memory system on the master side and the data stored in the flash memory system on the slave side by accessing the same memory controller.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[Description of flash memory system 1]
FIG. 1 is a block diagram schematically showing the flash memory system 1. As shown in FIG. 1, the flash memory system 1 includes a flash memory 2 and a memory controller 3 that controls the flash memory 2. The flash memory system 1 is normally used by being detachably attached to the host system 4, and is used as a kind of external storage device for the host system 4.

  Examples of the host system 4 include various information processing apparatuses such as a personal computer and a digital still camera that process various information such as characters, sounds, and image information.

  The flash memory 2 is a device that executes reading or writing in units of pages and erasing in units of blocks. For example, one block is composed of 32 pages, and one page is a 512-byte user area and a 16-byte redundant area. It is configured.

  The memory controller 3 includes a host interface control block 5, a microprocessor 6, a host interface block 7, a work area 8, a buffer 9, a flash memory interface block 10, and an ECC (error collection code) block 11. And a flash memory sequencer block 12. The memory controller 3 constituted by these functional blocks is integrated on one semiconductor chip. The function of each block will be described below.

  The microprocessor 6 is a functional block that controls the operation of the entire functional blocks constituting the memory controller 3.

  The host interface control block 5 is a functional block that controls the operation of the host interface block 7. Here, the host interface control block 5 includes an operation setting register (not shown) for setting the operation of the host interface block 7, and the host interface block 7 operates based on the operation setting register.

  The host interface block 7 is a functional block that exchanges data, address information, status information, and external command information with the host system 4. That is, when the flash memory system 1 is attached to the host system 4, the flash memory system 1 and the host system 4 are connected to each other via the external bus 13, and in this state, the host system 4 connects to the flash memory system 1. The supplied data or the like is taken into the memory controller 3 using the host interface block 7 as an entrance, and the data or the like supplied from the flash memory system 1 to the host system 4 is sent to the host system 4 using the host interface block 7 as an exit. Supplied.

  The host interface block 7 further includes a task file register (not shown) that temporarily holds a host address and an external command supplied from the host system 4 and an error register (not shown) that is set when an error occurs. ) Etc. In the flash memory system 1 according to the present invention, a flash memory chip to be accessed is determined based on register information in which information related to a host address is set.

  The work area 8 is a work area in which data necessary for controlling the flash memory 2 is temporarily stored, and is a functional block configured by a plurality of SRAM (Static Random Access Memory) cells.

  The buffer 9 is a functional block that temporarily holds data read from the flash memory 2 and data to be written to the flash memory 2. That is, data read from the flash memory 2 is held in the buffer 9 until the host system 4 is ready to receive data, and data to be written into the flash memory 2 is held in the buffer 9 until the flash memory 2 is ready to write. The

  The flash memory sequencer block 12 is a functional block that controls the operation of the flash memory 2 based on internal commands. The flash memory sequencer block 12 includes a plurality of registers (not shown), and information necessary for executing an internal command is set in the plurality of registers. When information necessary for executing an internal command is set in the plurality of registers, the flash memory sequencer block 12 executes processing based on the information. Here, the “internal command” is a command given from the memory controller 3 to the flash memory 2 and is distinguished from an “external command” which is a command given from the host system 4 to the flash memory system 1.

  The flash memory interface block 10 is a functional block that exchanges data, address information, status information, internal command information, device ID information, and the like with the flash memory 2 via the internal bus 14.

  The ECC block 11 generates an error correction code to be added to data to be written to the flash memory 2, and detects and corrects errors included in the read data based on the error correction code added to the read data. Function block.

[Description of flash memory]
A NAND flash memory in which data is stored in a flash memory system is a non-volatile memory developed for use as a storage device (as an alternative to a hard disk). This NAND flash memory cannot perform random access, and writing and reading are performed in units of pages and erasing is performed in units of blocks. Since data cannot be overwritten, when data is written, data is written into the erased area.

  Since the NAND flash memory has such characteristics, normally, when data is rewritten, new data (data after rewriting) is written to the erased block that has been erased, and old data is written. A process of erasing a block in which (data before rewriting) has been written is performed. When such data is rewritten, the data after rewriting is written in a block different from that before rewriting, so the logical block address based on the address given from the host system side and the block in the flash memory The correspondence with the physical block address, which is an address, dynamically changes every time data is rewritten. The correspondence between the logical block address and the physical block address is normally managed by an address conversion table indicating the correspondence, and the address conversion table is created based on a corresponding logical block address described later.

  The configuration of the block and page differs depending on the specification of the flash memory. However, in a general flash memory, as shown in FIG. 2A, one block is composed of 32 pages (P0 to P31). A page is composed of a user area of 512 bytes and a redundant area of 16 bytes. As the storage capacity increases, as shown in FIG. 2B, one block is composed of 64 pages (P0 to P63), and each page is composed of a 2048-byte user area and a 64-byte redundant area. What is being provided is also provided.

  Here, the user area is mainly an area for storing data supplied from the host system, and the redundant area is for storing additional data such as an error correction code, a corresponding logical block address and a block status. It is an area. The error correction code is additional data for detecting and correcting an error included in data stored in the user area, and is generated by an external ECC block. The corresponding logical block address indicates to which logical block address the block corresponds when data is stored in the block. If no data is stored in the block, the corresponding logical block address is not stored. Therefore, whether or not the block is an erased block depends on whether or not the corresponding logical block address is stored. It can also be judged. That is, if the corresponding logical block address is not stored, it is determined that the block is an erased block. The block status is a flag indicating whether or not the block is a bad block (a block in which data cannot be normally written). If it is determined that the block is a bad block, the block status is bad. A flag indicating a block is set.

  Next, a circuit configuration of the NAND flash memory will be described. A general NAND flash memory includes a register for holding write data or read data and a memory cell array for storing data. The memory cell array includes a plurality of memory cell groups in which a plurality of memory cells are connected in series, and a specific memory cell in the memory cell group is selected by a word line. Data copying (copying from the register to the memory cell or copying from the memory cell to the register) is performed between the memory cell selected by the word line and the register.

  A memory cell constituting the memory cell array is composed of a MOS transistor having two gates. Here, the upper gate is called a control gate and the lower gate is called a floating gate. Data is written by injecting charges (electrons) into the floating gate or discharging charges (electrons) from the floating gate. Or data is erased. Since the floating gate is surrounded by an insulator, the injected electrons are held for a long period of time. When electrons are injected into the floating gate, a high voltage is applied so that the control gate is on the high potential side. When electrons are injected from the floating gate, electrons are injected on the floating gate. A voltage is applied to discharge electrons. Here, the state in which electrons are injected into the floating gate (write state) corresponds to the data of the logical value “0”, and the state in which electrons are discharged from the floating gate (erased state) is the logical value. Corresponds to the data of “1”.

[Description of access to flash memory]
In FIG. 3, the buffer 21 and the additional data register 22 are configured in the memory controller 20, and the buffer 21 holds data supplied from the host system or data read from the flash memory 23. Additional data such as an error correction code is set in the additional data register 22. On the other hand, the register 24 and the memory cell array 25 are configured in the flash memory 23, and the register 24 holds data supplied from the memory controller 20 or data output from the memory cell array 25. The memory cell array 25 stores data supplied from the memory controller 20.

  When the data supplied from the host system is written to the flash memory 23, the data supplied from the host system is held in the buffer 21, and an error correction code generated for the data held in the buffer 21 and other data Additional data is set in the additional data register 22. The user data held in the buffer 21 and the additional data set in the additional data register 22 are transferred to the flash memory 23 and held in the register 24 in the flash memory 23. The user data and additional data held in the register 24 are copied (stored) on a page designated by the memory controller 20.

  When data stored in the flash memory 23 is read, the data stored in the page specified by the memory controller 20 is output from the memory cell array 25 and held in the register 24. The data held in the register 24 is transferred to the memory controller 20 and held in the buffer 21 and the additional data register 22. Thereafter, the data held in the buffer 21 is transferred to the host system.

  In the flash memory system according to the present invention, a master flash memory 33 and a slave flash memory 34 are connected to a memory controller 32 via an internal bus 36 as shown in FIG. The memory controller 32 accesses the master-side flash memory 33 or the slave-side flash memory 34 in accordance with information supplied from the host system 31 connected via the external bus 35.

  In the flash memory system according to the present invention, a flash memory chip to be accessed is determined based on information indicating the write destination supplied from the host system 31. That is, the memory controller 32 determines the flash memory chip to be accessed based on the information indicating the write destination supplied from the host system 31.

  The information for instructing the write destination is usually supplied by a CHS (Cylinder Head Sector) method or an LBA (Logical Block Addressing) method. FIG. 5 shows a register in which information indicating the write destination is set. In the CHS (Cylinder Head Sector) method, information indicating the write destination is set in the cylinder register 41, the device head register 42, and the sector register 43. In the LBA (Logical Block Addressing) method, information indicating the write destination is set in the LBA register 44.

  In the case of the CHS (Cylinder Head Sector) system, for example, the cylinder register 41 is composed of 16 bits, the device head register 42 is composed of 8 bits, and the sector register 43 is composed of 8 bits. The device head register 42 is assigned 4 bits for device parameters and 4 bits for head parameters. Here, one of the bits allocated for the device parameter of the device head register 42 is a bit for selecting the flash memory 33 on the master side or the flash memory 34 on the slave side, and the logical value ( “0” and “1”) are assigned to selection instructions for the flash memory 33 on the master side or the flash memory 34 on the slave side. When the logical value “0” is used to select the flash memory 33 on the master side and the logical value “1” is used to select the flash memory 34 on the slave side, the memory controller 32 is set to the logical value “0”. Then, the flash memory 33 on the master side is accessed, and if the logical value “1” is set, the flash memory 34 on the slave side is accessed. Accordingly, the host system 31 can access the flash memory 33 on the master side and the flash memory 34 on the slave side by appropriately setting the logical values of the selection instruction bits.

  The LBA register 44 used in the LBA (Logical Block Addressing) method is composed of 28 bits or 48 bits. Similarly, in the case of this method, if one bit of the LBA register 44 is information for selecting the flash memory 33 on the master side or the flash memory 34 on the slave side, the flash memory 33 on the master side or the slave side An instruction to select the flash memory 34 can be issued.

  The register for setting the selection instruction is not particularly limited as long as it is a register accessible from the host system side. The number of bits allocated to the selection instruction and the correspondence between the logical value set for the bit and the content of the selection instruction are not particularly limited.

  In a system including master data and slave data, the master data is stored in the flash memory 33 on the master side, and the slave data is stored in the flash memory 34 on the slave side. If this master data is a system startup program, the system is normally started up using the master data stored in the flash memory 33 on the master side. It starts using the slave data stored in the memory 34. However, the data stored in the flash memory on the master side and the data stored in the flash memory 34 on the slave side are not particularly limited.

FIG. 1 is a block diagram schematically showing a flash memory system according to the present invention. FIG. 2 is a schematic diagram showing the configuration of blocks and pages in the flash memory. FIG. 3 is a schematic diagram for explaining access to the flash memory. FIG. 4 is a block diagram schematically showing a configuration in which a master-side flash memory and a slave-side flash memory are connected to a memory controller. FIG. 5 is a block diagram schematically showing a register in which information indicating the write destination is set. FIG. 6 is a block diagram schematically showing a conventional memory system.

Explanation of symbols

1 Flash memory system 2, 33, 34, 53, 55 Flash memory 3, 32, 52, 54 Memory controller 4, 31, 51 Host system 5 Host interface control block 6 Microprocessor 7 Host interface block 8 Work area 9 Buffer 10 Flash Memory interface block 11 ECC block 12 Flash memory sequencer block 13 External bus 14 Internal bus

Claims (9)

An information holding function in which information about the access destination supplied from the host system side is set;
An access control function for controlling access to a plurality of flash memory chips,
A memory controller, wherein a part of the information holding function is assigned to an information setting area for designating a flash memory chip to be accessed.   2. The memory controller according to claim 1, wherein the information holding function includes a cylinder register, a device head register, and a sector register.   3. The memory controller according to claim 2, wherein information for designating an access destination flash memory chip is set in a parameter setting area for a device of the device / head register.   2. The memory controller according to claim 1, wherein the information holding function is a logical block address register.   A flash memory system comprising: the memory controller according to claim 1; and a plurality of flash memory chips. An information holding function in which information about the access destination supplied from the host system side is set;
An access control function for controlling access to a plurality of flash memory chips;
A first flash memory chip in which master data is stored;
A second flash memory chip for storing slave data;
A flash memory system, wherein a part of the information holding function is assigned to an information setting area for designating a first flash memory chip or a second flash memory chip.   7. The flash memory system according to claim 6, wherein the information holding function includes a cylinder register, a device head register, and a sector register.   8. The flash memory system according to claim 7, wherein information designating the first flash memory chip or the second flash memory chip is set in a parameter setting area related to a device of the device head register.   7. The flash memory system according to claim 6, wherein the information holding function is a logical block address register.

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